Simultaneously efficient light absorption and charge separation in WO3/BiVO4 core/shell nanowire photoanode for photoelectrochemical water oxidation

We report a scalably synthesized WO3/BiVO4 core/shell nanowire photoanode in which BiVO4 is the primary light-absorber and WO3 acts as an electron conductor. These core/shell nanowires achieve the highest product of light absorption and charge separation efficiencies among BiVO4-based photoanodes to date and, even without an added catalyst, produce a photocurrent of 3.1 mA/cm(2) under simulated sunlight and an incident photon-to-current conversion efficiency of ∼ 60% at 300-450 nm, both at a potential of 1.23 V versus RHE.

Flash ignition of freestanding porous silicon films: effects of film thickness and porosity

We report the first successful xenon flash ignition of freestanding porous Si films in air. The minimum flash ignition energy (Emin) first decreases and then increases with increasing the porous Si film thickness due to the competition between light absorption and heat loss. The Emin is lower for higher porosity film because high porosity reduces both the heat capacity and the thermal conductivity, facilitating the temperature rise. These results are important for initiating controlled porous Si combustion and preventing their unwanted combustion for safety reasons.

Electroassisted transfer of vertical silicon wire arrays using a sacrificial porous silicon layer

An electroassisted method is developed to transfer silicon (Si) wire arrays from the Si wafers on which they are grown to other substrates while maintaining their original properties and vertical alignment. First, electroassisted etching is used to form a sacrificial porous Si layer underneath the Si wires. Second, the porous Si layer is separated from the Si wafer by electropolishing, enabling the separation and transfer of the Si wires. The method is further expanded to develop a current-induced metal-assisted chemical etching technique for the facile and rapid synthesis of Si nanowires with axially modulated porosity.

Shrinking and growing: grain boundary density reduction for efficient polysilicon thin-film solar cells

Polycrystalline Si (poly-Si) thin-film, due to its low Si consumption, low substrate cost, and good stability, is an attractive candidate for cost-effective solar cells, but the as-deposited poly-Si typically has a columnar structure with grain boundaries in between, severely limiting the efficiency of the poly-Si. Here, we report a micropillar poly-Si solar cell that utilizes the columnar structure of the as-deposited poly-Si grains. We first formed submicrometer diameter poly-Si pillars, smaller than the initial grain sizes, and used these pillars as the seeds for the subsequent epitaxial growth of Si, which effectively reduces grain boundary density in the final poly-Si crystal. In addition, the vertically aligned micropillar arrays form radial p-n junctions that further mitigate the grain boundary recombination losses by improving the light absorption and charge-carrier collection efficiencies. Consequently, the maximum efficiency of micropillar poly-Si thin-film solar cells is 6.4%, that is, ∼1.5 times higher than that of the planar cells.

Thermal conductivity in porous silicon nanowire arrays

The nanoscale features in silicon nanowires (SiNWs) can suppress phonon propagation and strongly reduce their thermal conductivities compared to the bulk value. This work measures the thermal conductivity along the axial direction of SiNW arrays with varying nanowire diameters, doping concentrations, surface roughness, and internal porosities using nanosecond transient thermoreflectance. For SiNWs with diameters larger than the phonon mean free path, porosity substantially reduces the thermal conductivity, yielding thermal conductivities as low as 1 W/m/K in highly porous SiNWs. However, when the SiNW diameter is below the phonon mean free path, both the internal porosity and the diameter significantly contribute to phonon scattering and lead to reduced thermal conductivity of the SiNWs.

Fabrication of flexible and vertical silicon nanowire electronics

Vertical silicon nanowire (SiNW) array devices directly connected on both sides to metallic contacts were fabricated on various non-Si-based substrates (e.g., glass, plastics, and metal foils) in order to fully exploit the nanomaterial properties for final applications. The devices were realized with uniform length Ag-assisted electroless etched SiNW arrays that were detached from their fabrication substrate, typically Si wafers, reattached to arbitrary substrates, and formed with metallic contacts on both sides of the NW array. Electrical characterization of the SiNW array devices exhibits good current-voltage characteristics consistent with the SiNW morphology.

Vertical transfer of uniform silicon nanowire arrays via crack formation

Vertical transfer of silicon nanowire (SiNW) arrays with uniform length onto adhesive substrates was realized by the assistance of creating a horizontal crack throughout SiNWs. The crack is formed by adding a water soaking step between consecutive Ag-assisted electroless etching processes of Si. The crack formation is related to the delamination, redistribution, and reattachment of the Ag film during the water soaking and subsequent wet etching steps. Moreover, the crack facilitates embedding SiNWs inside polymers.