Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits.
MICROMACHINES 2020;
11:mi11080741. [PMID:
32751538 PMCID:
PMC7464086 DOI:
10.3390/mi11080741]
[Citation(s) in RCA: 1] [Impact Index Per Article: 0.3] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Download PDF] [Figures] [Subscribe] [Scholar Register] [Received: 07/04/2020] [Revised: 07/28/2020] [Accepted: 07/30/2020] [Indexed: 11/16/2022]
Abstract
We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.
Collapse