Novel nanofluidic chemical cells based on self-assembled solid-state SiO2 nanotubes

Novel nanofluidic chemical cells based on self-assembled solid-state SiO₂ nanotubes on silicon-on-insulator (SOI) substrate have been successfully fabricated and characterized. The vertical SiO₂ nanotubes with a smooth cavity are built from Si nanowires which were epitaxially grown on the SOI substrate. The nanotubes have rigid, dry-oxidized SiO₂ walls with precisely controlled nanotube inner diameter, which is very attractive for chemical-/bio-sensing applications. No dispersion/aligning procedures were involved in the nanotube fabrication and integration by using this technology, enabling a clean and smooth chemical cell. Such a robust and well-controlled nanotube is an excellent case of developing functional nanomaterials by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth. These solid, smooth, clean SiO₂ nanotubes and nanofluidic devices are very encouraging and attractive in future bio-medical applications, such as single molecule sensing and DNA sequencing.

Redox-Active Molecular Nanowire Flash Memory for High-Endurance and High-Density Nonvolatile Memory Applications

In this work, high-performance top-gated nanowire molecular flash memory has been fabricated with redox-active molecules. Different molecules with one and two redox centers have been tested. The flash memory has clean solid/molecule and dielectric interfaces, due to the pristine molecular self-assembly and the nanowire device self-alignment fabrication process. The memory cells exhibit discrete charged states at small gate voltages. Such multi-bit memory in one cell is favorable for high-density storage. These memory devices exhibit fast speed, low power, long memory retention, and exceptionally good endurance (>10(9) cycles). The excellent characteristics are derived from the intrinsic charge-storage properties of the protected redox-active molecules. Such multi-bit molecular flash memory is very attractive for high-endurance and high-density on-chip memory applications in future portable electronics.

Direct measurement of Dirac point energy at the graphene/oxide interface

We report the direct measurement of the Dirac point, the Fermi level, and the work function of graphene by performing internal photoemission measurements on a graphene/SiO(2)/Si structure with a unique optical-cavity enhanced test structure. A complete electronic band alignment at the graphene/SiO(2)/Si interfaces is accurately established. The observation of enhanced photoemission from a one-atom thick graphene layer was possible by taking advantage of the constructive optical interference in the SiO(2) cavity. The photoemission yield was found to follow the well-known linear density-of-states dispersion in the vicinity of the Dirac point. At the flat band condition, the Fermi level was extracted and found to reside 3.3 eV ± 0.05 eV below the bottom of the SiO(2) conduction band. When combined with the shift of the Fermi level from the Dirac point, we are able to ascertain the position of the Dirac point at 3.6 eV ± 0.05 eV with respect to the bottom of the SiO(2) conduction band edge, yielding a work function of 4.5 eV ± 0.05 eV which is in an excellent agreement with theory. The accurate determination of the work function of graphene is of significant importance to the engineering of graphene-based devices, and the measurement technique we have advanced in this Letter will have significant impact on numerous applications for emerging graphene-like 2-dimensional material systems.

Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO(2) charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO(2) increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO(2) thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.

The large-scale integration of high-performance silicon nanowire field effect transistors

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.

Noise in ZnO nanowire field effect transistors

The noise power spectra in ZnO nanowire field effect transistors (FETs) were experimentally investigated and showed a classical 1/f dependence. A Hooge's constant of 5 x 10(-3) was estimated. This value is within the range reported for CMOS FETs with high-k dielectrics, supporting the concept that nanowires can be utilized for future beyond-CMOS electronic applications from the point of view of device noise properties. ZnO FETs measured in a dry O2 environment displayed elevated noise levels compared to in vacuum. At low temperature, random telegraph signals are observed in the drain current.