Flash-Based Computing-in-Memory Architecture to Implement High-Precision Sparse Coding

To address the concerns with power consumption and processing efficiency in big-size data processing, sparse coding in computing-in-memory (CIM) architectures is gaining much more attention. Here, a novel Flash-based CIM architecture is proposed to implement large-scale sparse coding, wherein various matrix weight training algorithms are verified. Then, with further optimizations of mapping methods and initialization conditions, the variation-sensitive training (VST) algorithm is designed to enhance the processing efficiency and accuracy of the applications of image reconstructions. Based on the comprehensive characterizations observed when considering the impacts of array variations, the experiment demonstrated that the trained dictionary could successfully reconstruct the images in a 55 nm flash memory array based on the proposed architecture, irrespective of current variations. The results indicate the feasibility of using Flash-based CIM architectures to implement high-precision sparse coding in a wide range of applications.

Over- and Undercoordinated Atoms as a Source of Electron and Hole Traps in Amorphous Silicon Nitride (a-Si3N4)

Silicon nitride films are widely used as the charge storage layer of charge trap flash (CTF) devices due to their high charge trap densities. The nature of the charge trapping sites in these materials responsible for the memory effect in CTF devices is still unclear. Most prominently, the Si dangling bond or K-center has been identified as an amphoteric trap center. Nevertheless, experiments have shown that these dangling bonds only make up a small portion of the total density of electrical active defects, motivating the search for other charge trapping sites. Here, we use a machine-learned force field to create model structures of amorphous Si3N4 by simulating a melt-and-quench procedure with a molecular dynamics algorithm. Subsequently, we employ density functional theory in conjunction with a hybrid functional to investigate the structural properties and electronic states of our model structures. We show that electrons and holes can localize near over- and under-coordinated atoms, thereby introducing defect states in the band gap after structural relaxation. We analyze these trapping sites within a nonradiative multi-phonon model by calculating relaxation energies and thermodynamic charge transition levels. The resulting defect parameters are used to model the potential energy curves of the defect systems in different charge states and to extract the classical energy barrier for charge transfer. The high energy barriers for charge emission compared to the vanishing barriers for charge capture at the defect sites show that intrinsic electron traps can contribute to the memory effect in charge trap flash devices.

An Efficient and Robust Partial Differential Equation Solver by Flash-Based Computing in Memory

Flash memory-based computing-in-memory (CIM) architectures have gained popularity due to their remarkable performance in various computation tasks of data processing, including machine learning, neuron networks, and scientific calculations. Especially in the partial differential equation (PDE) solver that has been widely utilized in scientific calculations, high accuracy, processing speed, and low power consumption are the key requirements. This work proposes a novel flash memory-based PDE solver to implement PDE with high accuracy, low power consumption, and fast iterative convergence. Moreover, considering the increasing current noise in nanoscale devices, we investigate the robustness against the noise in the proposed PDE solver. The results show that the noise tolerance limit of the solver can reach more than five times that of the conventional Jacobi CIM solver. Overall, the proposed flash memory-based PDE solver offers a promising solution for scientific calculations that require high accuracy, low power consumption, and good noise immunity, which could help to develop flash-based general computing.

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D₂) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D₂ annealing. The suggested curing is found to be effective in improving the device reliability.

High Pressure Deuterium Passivation of Charge Trapping Layer for Nonvolatile Memory Applications

In this study, the deuterium passivation effect of silicon nitride (Si₃N₄) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si₃N₄ as a charge trapping layer, deuterium (D₂) high pressure annealing (HPA) was applied after Si₃N₄ deposition. Flat band voltage shifts (ΔV_FB) in data retention mode were compared by CV measurement after D₂ HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si₃N₄. D₂ HPA reduces the amount of trap densities in the band gap range of 1.06-1.18 eV. SIMS profiles are used to analyze the D₂ profile in Si₃N₄. The results show that deuterium diffuses into the Si₃N₄ and exists up to the Si₃N₄-SiO₂ interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability.

Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory

In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increased under limited height of NAND string. In this context, finding a novel approach based on dielectric engineering seems timely and applicable. This paper covers the voltage interference characteristics in 3D NAND with respect to dielectrics, then proposes an alternative cell structure to suppress such interference.

Near-Infrared Artificial Synapses for Artificial Sensory Neuron System

The computing based on artificial neuron network is expected to break through the von Neumann bottleneck of traditional computer, and to greatly improve the computing efficiency, displaying a broad prospect in the application of artificial visual system. In the specific structural layout, it is a common method to connect the discrete photodetector with the artificial neuron in series, which enhances the complexity of signal recognition, conversion and storage. In this work, organic small molecule IR-780 iodide is inserted into the memory device as both the charge trapping layer and near-infrared (NIR) photoresponsive film. Through electrical and optical regulation, artificial synaptic functions including short-term plasticity, long-term plasticity, and spike rate dependence are realized. In the established artificial sensory neuron system, NIR optical pulses can significantly improve the spiking rate. Moreover, the spiking neural networks are further constructed by simulation for handwritten digit classification. This research may contribute to the development of light driven neural robots, optical signal encryption, and neural computing.

Controlling Native Oxidation of HfS2 for 2D Materials Based Flash Memory and Artificial Synapse

Two-dimensional (2D) materials based artificial synapses are important building blocks for the brain-inspired computing systems that are promising in handling large amounts of informational data with high energy-efficiency in the future. However, 2D devices usually rely on deposited or transferred insulators as the dielectric layer, resulting in various challenges in device compatibility and fabrication complexity. Here, we demonstrate a controllable and reliable oxidation process to turn 2D semiconductor HfS₂ into native oxide, HfO_x, which shows good insulating property and clean interface with HfS₂. We then incorporate the HfO_x/HfS₂ heterostructure into a flash memory device, achieving a high on/off current ratio of ∼10⁵, a large memory window over 60 V, good endurance, and a long retention time over 10³ seconds. In particular, the memory device can work as an artificial synapse to emulate basic synaptic functions and feature good linearity and symmetry in conductance change during long-term potentiation/depression processes. A simulated artificial neural network based on our synaptic device achieves a high accuracy of ∼88% in MNIST pattern recognition. Our work provides a simple and effective approach for integrating high-k dielectrics into 2D material-based memory and synaptic devices.

3D AND-Type Stacked Array for Neuromorphic Systems

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

Perovskite Flash Memory with a Single-Layer Nanofloating Gate

Here we use triple-cation metal-organic halide perovskite single crystals for the transistor channel of a flash memory device. Moreover, we design and demonstrate a 10 nm thick single-layer nanofloating gate. It consists of a ternary blend of two organic semiconductors, a p-type polyfluorene and an n-type fullerene that form a donor:acceptor interpenetrating network that serves as the charge storage unit, and of an insulating polystyrene that acts as the tunneling dielectric. Under such a framework, we realize the first non-volatile flash memory transistor based on a perovskite channel. This simplified, solution-processed perovskite flash memory displays unique performance metrics such as a large memory window of 30 V, an on/off ratio of 9 × 10⁷, short write/erase times of 50 ms, and a satisfactory retention time exceeding 10⁶ s. The realization of the first flash memory transistor using a single-crystal perovskite channel could be a valuable direction for perovskite electronics research.

Synthesis of Cyclopentadithiophene-Diketopyrrolopyrrole Donor-Acceptor Copolymers for High-Performance Nonvolatile Floating-Gate Memory Transistors with Long Retention Time

Organic flash memories that employ solution-processed polymer semiconductors preferentially require internal stability of their active channel layers. In this paper, a series of new donor-acceptor copolymers based on cyclopentadithiophene (CDT) and diketopyrrolopyrrole (DPP) are synthesized to obtain high performance and operational stability of nonvolatile floating-gate memory transistors with various additional donor units including thiophene, thiophene-vinylene-thiophene (CDT-DPP-TVT), selenophene, and selenophene-vinylene-selenophene. Detailed analyses on the photophysical, two-dimensional grazing incident X-ray diffraction, and bias stress stability are discussed, which reveal that the CDT-DPP-TVT exhibits excellent bias stress stability over 10⁵ s. To utilize the robust nature of CDT-DPP-TVT, floating-gate transistors are fabricated by embedding Au nanoparticles between Cytop layers as a charge storage site. The resulting memory devices reveal bistable current states with high on/off current ratio larger than 10⁴ and each state can be distinguished for more than 1 year, indicating a long retention time. Moreover, repetitive writing-reading-erasing-reading test clearly supports the reproducible memory operation with reversible and reliable electrical responses. All these results suggest that the internal stability of CDT-DPP-TVT makes this copolymer a promising material for application in reliable organic flash memory.

Hierarchical Hollow-Pore Nanostructure Bilayer Heterojunction Comprising Conjugated Polymers for High-Performance Flash Memory

We report the design and preparation of hierarchical hollow-pore nanostructure bilayer conjugated polymer films for high-performance resistive memory devices. By taking the merits of chemical and structural stabilities of a two-dimensional conjugated microporous polymer (2D CMP), a poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene] (MEH-PPV) film with a hollow surface was spin-coated onto 2D CMP nanofilm directly, constructing a bilayer heterojunction. A two-terminal diode with a configuration of indium tin oxide/2D CMP/hollow MEH-PPV/Al was fabricated by employing the prepared bilayer heterojunction. The device poses flash feature with a high on/off ratio (>10⁵) and a long retention time (>3.0 × 10⁴ s), which is higher than that of most of the reported conjugated polymers memories. Our work offers a general guideline to construct high on/off ratio polymer memories via hierarchical nanostructure engineering in memristive layer.

A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs)

Bose-Chaudhuri-Hocquenghem (BCH) codes are broadly used to correct errors in flash memory systems and digital communications. These codes are cyclic block codes and have their arithmetic fixed over the splitting field of their generator polynomial. There are many solutions proposed using CPUs, hardware, and Graphical Processing Units (GPUs) for the BCH decoders. The performance of these BCH decoders is of ultimate importance for systems involving flash memory. However, it is essential to have a flexible solution to correct multiple bit errors over the different finite fields (GF(2 m )). In this paper, we propose a pragmatic approach to decode BCH codes over the different finite fields using hardware circuits and GPUs in tandem. We propose to employ hardware design for a modified syndrome generator and GPUs for a key-equation solver and an error corrector. Using the above partition, we have shown the ability to support multiple bit errors across different BCH block codes without compromising on the performance. Furthermore, the proposed method to generate modified syndrome has zero latency for scenarios where there are no errors. When there is an error detected, the GPUs are deployed to correct the errors using the iBM and Chien search algorithm. The results have shown that using the modified syndrome approach, we can support different multiple finite fields with high throughput.

Investigation of Intra-Nitride Charge Migration Suppression in SONOS Flash Memory

In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N₂ plasma treated on the silicon nitride is proposed. Experimental results show that the charge loss decreased in the plasma treated device after baking at 300 °C for 2 h. To extract trap density according to the location in the trapping layer, capacitance-voltage analysis was used and N₂ plasma treatment was shown to be effective to restrain the interface trap formation between blocking oxide and silicon nitride. Moreover, from X-ray Photoelectron Spectroscopy, the reduction of Si-O-N bonding was observed.

Photonic Synapses Based on Inorganic Perovskite Quantum Dots for Neuromorphic Computing

Inspired by the biological neuromorphic system, which exhibits a high degree of connectivity to process huge amounts of information, photonic memory is expected to pave a way to overcome the von Neumann bottleneck for nonconventional computing. Here, a photonic flash memory based on all-inorganic CsPbBr₃ perovskite quantum dots (QDs) is demonstrated. The heterostructure formed between the CsPbBr₃ QDs and semiconductor layer serves as a basis for optically programmable and electrically erasable characteristics of the memory device. Furthermore, synapse functions including short-term plasticity, long-term plasticity, and spike-rate-dependent plasticity are emulated at the device level. The photonic potentiation and electrical habituation are implemented and the synaptic weight exhibits multiple wavelength response from 365, 450, 520 to 660 nm. These results may locate the stage for further thrilling novel advances in perovskite-based memories.

Sulfur (VI) Fluoride Exchange Polymerization for Large Conjugate Chromophores and Functional Main-Chain Polysulfates with Nonvolatile Memory Performance

Sulfur (VI) fluoride exchange (SuFEx) reactions can be applied not only in organic click synthesis, but also in the preparation of functional main-chain polymers. In this work, four functional main-chain polysulfates (PNT-PS, NPNT-PS, PHF-PS, and TPE-PS) are synthesized in high yield using the SuFEx reaction at room temperature. The polysulfates exhibit satisfactory thermal stability and solution processability. They are used as the active layer for memory devices (ITO/PNT-PS/Al, ITO/NPNT-PS/Al, ITO/PHF-PS/Al, and ITO/TPE-PS/Al). I-V measurements show that ITO/PNT-PS/Al and ITO/NPNT-PS/Al exhibit stable flash-memory (write-read-erase) behavior, while ITO/PHF-PS/Al and ITO/TPE-PS/Al exhibit WORM (write once read many) behavior. Our studies provide a feasible and efficient synthetic methodology for the preparation of new memory materials.

Redox-Active Molecular Nanowire Flash Memory for High-Endurance and High-Density Nonvolatile Memory Applications

In this work, high-performance top-gated nanowire molecular flash memory has been fabricated with redox-active molecules. Different molecules with one and two redox centers have been tested. The flash memory has clean solid/molecule and dielectric interfaces, due to the pristine molecular self-assembly and the nanowire device self-alignment fabrication process. The memory cells exhibit discrete charged states at small gate voltages. Such multi-bit memory in one cell is favorable for high-density storage. These memory devices exhibit fast speed, low power, long memory retention, and exceptionally good endurance (>10(9) cycles). The excellent characteristics are derived from the intrinsic charge-storage properties of the protected redox-active molecules. Such multi-bit molecular flash memory is very attractive for high-endurance and high-density on-chip memory applications in future portable electronics.

Surface engineering of reduced graphene oxide for controllable ambipolar flash memories

Tunable charge-trapping behaviors including unipolar charge trapping of one type of charge carrier and ambipolar trapping of both electrons and holes in a complementary manner is highly desirable for low power consumption multibit flash memory design. Here, we adopt a strategy of tuning the Fermi level of reduced graphene oxide (rGO) through self-assembled monolayer (SAM) functionalization and form p-type and n-type doped rGO with a wide range of manipulation on work function. The functionalized rGO can act as charge-trapping layer in ambipolar flash memories, and a dramatic transition of charging behavior from unipolar trapping of electrons to ambipolar trapping and eventually to unipolar trapping of holes was achieved. Adjustable hole/electron injection barriers induce controllable Vth shift in the memory transistor after programming operation. Finally, we transfer the ambipolar memory on flexible substrates and study their charge-trapping properties at various bending cycles. The SAM-functionalized rGO can be a promising candidate for next-generation nonvolatile memories.

Hierarchically built gold nanoparticle supercluster arrays as charge storage centers for enhancing the performance of flash memory devices

Flash memory devices with high-performance levels exhibiting high charge storage capacity, good charge retention, and high write/erase speeds with lower operating voltages are widely in demand. In this direction, we demonstrate hierarchical self-assembly of gold nanoparticles based on block copolymer templates as a promising route to engineer nanoparticle assemblies with high nanoparticle densities for application in nanocrystal flash memories. The hierarchical self-assembly process allows systematic multiplication of nanoparticle densities with minimal increase in footprint, thereby increasing the charge storage density without an increase in operating voltage. The protocol involves creation of a parent template composed of gold nanoclusters that guides the self-assembly of diblock copolymer reverse micelles which in turn directs electrostatic assembly of gold nanoparticles resulting in a three-level hierarchical system. Capacitance-voltage (C-V) measurements of the hierarchical nanopatterns with a metal-insulator-semiconductor capacitor configuration reveal promising enhancement in memory window as compared to nonhierarchical nanoparticle controls. Capacitance-time (C-t) measurements show that over half the stored charges were retained when extrapolated to 10 years. The fabrication route can be readily extended to programmed density multiplication of features made of other potential charge storage materials such as platinum, palladium, or hybrid metal/metal oxides for next generation, solution-processable flash memory devices.

Floating gate memory-based monolayer MoS2 transistor with metal nanocrystals embedded in the gate dielectrics

Charge trapping layers are formed from different metallic nanocrystals in MoS2 -based nanocrystal floating gate memory cells in a process compatible with existing fabrication technologies. The memory cells with Au nanocrystals exhibit impressive performance with a large memory window of 10 V, a high program/erase ratio of approximately 10(5) and a long retention time of 10 years.

Towards the development of flexible non-volatile memories

Flexible non-volatile memories have attracted tremendous attentions for data storage for future electronics application. From device perspective, the advantages of flexible memory devices include thin, lightweight, printable, foldable and stretchable. The flash memories, resistive random access memories (RRAM) and ferroelectric random access memory/ferroelectric field-effect transistor memories (FeRAM/FeFET) are considered as promising candidates for next generation non-volatile memory device. Here, we review the general background knowledge on device structure, working principle, materials, challenges and recent progress with the emphasis on the flexibility of above three categories of non-volatile memories.

A hot hole-programmed and low-temperature-formed SONOS flash memory

In this study, a high-performance TixZrySizO flash memory is demonstrated using a sol-gel spin-coating method and formed under a low annealing temperature. The high-efficiency charge storage layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride, followed by 60 s of annealing at 600°C. The flash memory exhibits a noteworthy hot hole trapping characteristic and excellent electrical properties regarding memory window, program/erase speeds, and charge retention. At only 6-V operation, the program/erase speeds can be as fast as 120:5.2 μs with a 2-V shift, and the memory window can be up to 8 V. The retention times are extrapolated to 106 s with only 5% (at 85°C) and 10% (at 125°C) charge loss. The barrier height of the TixZrySizO film is demonstrated to be 1.15 eV for hole trapping, through the extraction of the Poole-Frenkel current. The excellent performance of the memory is attributed to high trapping sites of the low-temperature-annealed, high-κ sol-gel film.

Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory

This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.