A Peripheral-Free True Random Number Generator Based on Integrated Circuits Enabled by Atomically Thin Two-Dimensional Materials

A true random number generator (TRNG) is essential to ensure information security for Internet of Things (IoT) edge devices. While pseudorandom number generators (PRNGs) have been instrumental, their deterministic nature limits their application in security-sensitive scenarios. In contrast, hardware-based TRNGs derived from physically unpredictable processes offer greater reliability. This study demonstrates a peripheral-free TRNG utilizing two cascaded three-stage inverters (TSIs) in conjunction with an XOR gate composed of monolayer molybdenum disulfide (MoS2) field-effect transistors (FETs) by exploiting the stochastic charge trapping and detrapping phenomena at and/or near the MoS2/dielectric interface. The entropy source passes the NIST SP800-90B tests with a minimum normalized entropy of 0.8780, while the generated bits pass the NIST SP800-22 randomness tests without any postprocessing. Moreover, the keys generated using these random bits are uncorrelated with near-ideal entropy, bit uniformity, and Hamming distances, exhibiting resilience against machine learning (ML) attacks, temperature variations, and supply bias fluctuations with a frugal energy expenditure of 30 pJ/bit. This approach offers an advantageous alternative to conventional silicon, memristive, and nanomaterial-based TRNGs as it obviates the need for extensive peripherals while harnessing the potential of atomically thin 2D materials in developing low-power TRNGs.

Radiation Resilient Two-Dimensional Electronics

Limitations in cloud-based computing have prompted a paradigm shift toward all-in-one "edge" devices capable of independent data sensing, computing, and storage. Advanced defense and space applications stand to benefit immensely from this due to their need for continual operation in areas where maintaining remote oversight is difficult. However, the extreme environments relevant to these applications necessitate rigorous testing of technologies, with a common requirement being hardness to ionizing radiation. Two-dimensional (2D) molybdenum disulfide (MoS₂) has been noted to enable the sensing, storage, and logic capabilities necessary for all-in-one edge devices. Despite this, the investigation of ionizing radiation effects in MoS₂-based devices remains incomplete. In particular, studies on gamma radiation effects in MoS₂ have been largely limited to standalone films, with few device investigations; to the best of our knowledge, no explorations have been made into gamma radiation effects on the sensing and memory capabilities of MoS₂-based devices. In this work, we have used a statistical approach to study high-dose (1 Mrad) gamma radiation effects on photosensitive and programmable memtransistors fabricated from large-area monolayer MoS₂. Memtransistors were divided into separate groups to ensure accurate extraction of device characteristics pertaining to baseline performance, sensing, and memory before and after irradiation. All-MoS₂ logic gates were also assessed to determine the gamma irradiation impact on logic implementation. Our findings show that the multiple functionalities of MoS₂ memtransistors are not severely impacted by gamma irradiation even without dedicated shielding/mitigation techniques. We believe that these results serve as a foundation for more application-oriented studies going forward.

A Graphene-Based Straintronic Physically Unclonable Function

Physically unclonable functions (PUFs) are an integral part of modern-day hardware security. Various types of PUFs already exist, including optical, electronic, and magnetic PUFs. Here, we introduce a novel straintronic PUF (SPUF) by exploiting strain-induced reversible cracking in the contact microstructures of graphene field-effect transistors (GFETs). We found that strain cycling in GFETs with a piezoelectric gate stack and high-tensile-strength metal contacts can lead to an abrupt transition in some GFET transfer characteristics, whereas other GFETs remain resilient to strain cycling. Strain sensitive GFETs show colossal ON/OFF current ratios >10⁷, whereas strain-resilient GFETs show ON/OFF current ratios <10. We fabricated a total of 25 SPUFs, each comprising 16 GFETs, and found near-ideal performance. SPUFs also demonstrated resilience to regression-based machine learning (ML) attacks in addition to supply voltage and temporal stability. Our findings highlight the opportunities for emerging straintronic devices in addressing some of the critical needs of the microelectronics industry.

Ultrascaled Contacts to Monolayer MoS2 Field Effect Transistors

Two-dimensional (2D) semiconductors possess promise for the development of field-effect transistors (FETs) at the ultimate scaling limit due to their strong gate electrostatics. However, proper FET scaling requires reduction of both channel length (L_CH) and contact length (L_C), the latter of which has remained a challenge due to increased current crowding at the nanoscale. Here, we investigate Au contacts to monolayer MoS₂ FETs with L_CH down to 100 nm and L_C down to 20 nm to evaluate the impact of contact scaling on FET performance. Au contacts are found to display a ∼2.5× reduction in the ON-current, from 519 to 206 μA/μm, when L_C is scaled from 300 to 20 nm. It is our belief that this study is warranted to ensure an accurate representation of contact effects at and beyond the technology nodes currently occupied by silicon.

A Monolithic Stochastic Computing Architecture for Energy Efficient Arithmetic

As the energy and hardware investments necessary for conventional high-precision digital computing continue to explode in the era of artificial intelligence (AI), a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since, unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting, etc., SC can implement the same using simple logic gates. While it is possible to accelerate SC using traditional silicon complementary metal-oxide-semiconductor (CMOS) technology, the need for extensive hardware investment to generate stochastic bits (s-bits), the fundamental computing primitive for SC, makes it less attractive. Memristor and spin-based devices offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here, the limitations of existing and emerging technologies are overcome, and a standalone SC architecture embedded in memory and based on 2D memtransistors is experimentally demonstrated. The monolithic and non-von-Neumann SC architecture occupies a small hardware footprint and consumes a miniscule amount of energy (<1 nJ) for both s-bit generation and arithmetic operations, highlighting the benefits of SC.

Insect-Inspired, Spike-Based, in-Sensor, and Night-Time Collision Detector Based on Atomically Thin and Light-Sensitive Memtransistors

Detecting a potential collision at night is a challenging task owing to the lack of discernible features that can be extracted from the available visual stimuli. To alert the driver or, alternatively, the maneuvering system of an autonomous vehicle, current technologies utilize resource draining and expensive solutions such as light detection and ranging (LiDAR) or image sensors coupled with extensive software running sophisticated algorithms. In contrast, insects perform the same task of collision detection with frugal neural resources. Even though the general architecture of separate sensing and processing modules is the same in insects and in image-sensor-based collision detectors, task-specific obstacle avoidance algorithms allow insects to reap substantial benefits in terms of size and energy. Here, we show that insect-inspired collision detection algorithms, when implemented in conjunction with in-sensor processing and enabled by innovative optoelectronic integrated circuits based on atomically thin and photosensitive memtransistor technology, can greatly simplify collision detection at night. The proposed collision detector eliminates the need for image capture and image processing yet demonstrates timely escape responses for cars on collision courses under various real-life scenarios at night. The collision detector also has a small footprint of ∼40 μm2 and consumes only a few hundred picojoules of energy. We strongly believe that the proposed collision detectors can augment existing sensors necessary for ensuring autonomous vehicular safety.

Graphene and Beyond: Recent Advances in Two-Dimensional Materials Synthesis, Properties, and Devices

Since the isolation of graphene in 2004, two-dimensional (2D) materials research has rapidly evolved into an entire subdiscipline in the physical sciences with a wide range of emergent applications. The unique 2D structure offers an open canvas to tailor and functionalize 2D materials through layer number, defects, morphology, moiré pattern, strain, and other control knobs. Through this review, we aim to highlight the most recent discoveries in the following topics: theory-guided synthesis for enhanced control of 2D morphologies, quality, yield, as well as insights toward novel 2D materials; defect engineering to control and understand the role of various defects, including in situ and ex situ methods; and properties and applications that are related to moiré engineering, strain engineering, and artificial intelligence. Finally, we also provide our perspective on the challenges and opportunities in this fascinating field.

A Sparse and Spike-Timing-Based Adaptive Photoencoder for Augmenting Machine Vision for Spiking Neural Networks

The representation of external stimuli in the form of action potentials or spikes constitutes the basis of energy efficient neural computation that emerging spiking neural networks (SNNs) aspire to imitate. With recent evidence suggesting that information in the brain is more often represented by explicit firing times of the neurons rather than mean firing rates, it is imperative to develop novel hardware that can accelerate sparse and spike-timing-based encoding. Here a medium-scale integrated circuit composed of two cascaded three-stage inverters and one XOR logic gate fabricated using a total of 21 memtransistors based on photosensitive 2D monolayer MoS₂  for spike-timing-based encoding of visual information, is introduced. It is shown that different illumination intensities can be encoded into sparse spiking with time-to-first-spike representing the illumination information, that is, higher intensities invoke earlier spikes and vice versa. In addition, non-volatile and analog programmability in the photoencoder is exploited for adaptive photoencoding that allows expedited spiking under scotopic (low-light) and deferred spiking under photopic (bright-light) conditions, respectively. Finally, low energy expenditure of less than 1 µJ by the 2D-memtransistor-based photoencoder highlights the benefits of in-sensor and bioinspired design that can be transformative for the acceleration of SNNs.

Hardware implementation of Bayesian network based on two-dimensional memtransistors

Bayesian networks (BNs) find widespread application in many real-world probabilistic problems including diagnostics, forecasting, computer vision, etc. The basic computing primitive for BNs is a stochastic bit (s-bit) generator that can control the probability of obtaining ‘1’ in a binary bit-stream. While silicon-based complementary metal-oxide-semiconductor (CMOS) technology can be used for hardware implementation of BNs, the lack of inherent stochasticity makes it area and energy inefficient. On the other hand, memristors and spintronic devices offer inherent stochasticity but lack computing ability beyond simple vector matrix multiplication due to their two-terminal nature and rely on extensive CMOS peripherals for BN implementation, which limits area and energy efficiency. Here, we circumvent these challenges by introducing a hardware platform based on 2D memtransistors. First, we experimentally demonstrate a low-power and compact s-bit generator circuit that exploits cycle-to-cycle fluctuation in the post-programmed conductance state of 2D memtransistors. Next, the s-bit generators are monolithically integrated with 2D memtransistor-based logic gates to implement BNs. Our findings highlight the potential for 2D memtransistor-based integrated circuits for non-von Neumann computing applications.

Bayesian networks are applied to resolve several types of probabilistic problems. Here, Das et al. develop a stochastic computing hardware platform using two-dimensional memtransistors for the implementation of Bayesian network with high accuracy.

Review and comparison of layer transfer methods for two-dimensional materials for emerging applications

Two-dimensional (2D) materials offer immense potential for scientific breakthroughs and technological innovations. While early demonstrations of 2D material-based electronics, optoelectronics, flextronics, straintronics, twistronics, and biomimetic devices exploited micromechanically-exfoliated single crystal flakes, recent years have witnessed steady progress in large-area growth techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and metal-organic CVD (MOCVD). However, use of high growth temperatures, chemically-active growth precursors and promoters, and the need for epitaxy often limit direct growth of 2D materials on the substrates of interest for commercial applications. This has led to the development of a large number of methods for the layer transfer of 2D materials from the growth substrate to the target application substrate with varying degrees of cleanliness, uniformity, and transfer-related damage. This review aims to catalog and discuss these layer transfer methods. In particular, the processes, advantages, and drawbacks of various transfer methods are discussed, as is their applicability to different technological platforms of interest for 2D material implementation.

Graphene memristive synapses for high precision neuromorphic computing

Memristive crossbar architectures are evolving as powerful in-memory computing engines for artificial neural networks. However, the limited number of non-volatile conductance states offered by state-of-the-art memristors is a concern for their hardware implementation since trained weights must be rounded to the nearest conductance states, introducing error which can significantly limit inference accuracy. Moreover, the incapability of precise weight updates can lead to convergence problems and slowdown of on-chip training. In this article, we circumvent these challenges by introducing graphene-based multi-level (>16) and non-volatile memristive synapses with arbitrarily programmable conductance states. We also show desirable retention and programming endurance. Finally, we demonstrate that graphene memristors enable weight assignment based on k-means clustering, which offers greater computing accuracy when compared with uniform weight quantization for vector matrix multiplication, an essential component for any artificial neural network.