Automated Age-Related Macular Degeneration Detector on Optical Coherence Tomography Images Using Slice-Sum Local Binary Patterns and Support Vector Machine

Artificial intelligence has revolutionised smart medicine, resulting in enhanced medical care. This study presents an automated detector chip for age-related macular degeneration (AMD) using a support vector machine (SVM) and three-dimensional (3D) optical coherence tomography (OCT) volume. The aim is to assist ophthalmologists by reducing the time-consuming AMD medical examination. Using the property of 3D OCT volume, a modified feature vector connected method called slice-sum is proposed, reducing computational complexity while maintaining high detection accuracy. Compared to previous methods, this method significantly reduces computational complexity by at least a hundredfold. Image adjustment and noise removal steps are excluded for classification accuracy, and the feature extraction algorithm of local binary patterns is determined based on hardware consumption considerations. Through optimisation of the feature vector connection method after feature extraction, the computational complexity of SVM detection is significantly reduced, making it applicable to similar 3D datasets. Additionally, the design supports model replacement, allowing users to train and update classification models as needed. Using TSMC 40 nm CMOS technology, the proposed detector achieves a core area of 0.12 mm2 while demonstrating a classification throughput of 8.87 decisions/s at a maximum operating frequency of 454.54 MHz. The detector achieves a final testing classification accuracy of 92.31%.

A Tiled Ultrasound Matrix Transducer for Volumetric Imaging of the Carotid Artery

High frame rate three-dimensional (3D) ultrasound imaging would offer excellent possibilities for the accurate assessment of carotid artery diseases. This calls for a matrix transducer with a large aperture and a vast number of elements. Such a matrix transducer should be interfaced with an application-specific integrated circuit (ASIC) for channel reduction. However, the fabrication of such a transducer integrated with one very large ASIC is very challenging and expensive. In this study, we develop a prototype matrix transducer mounted on top of multiple identical ASICs in a tiled configuration. The matrix was designed to have 7680 piezoelectric elements with a pitch of 300 μm × 150 μm integrated with an array of 8 × 1 tiled ASICs. The performance of the prototype is characterized by a series of measurements. The transducer exhibits a uniform behavior with the majority of the elements working within the -6 dB sensitivity range. In transmit, the individual elements show a center frequency of 7.5 MHz, a -6 dB bandwidth of 45%, and a transmit efficiency of 30 Pa/V at 200 mm. In receive, the dynamic range is 81 dB, and the minimum detectable pressure is 60 Pa per element. To demonstrate the imaging capabilities, we acquired 3D images using a commercial wire phantom.

Feasibility Study of a Time-of-Flight Brain Positron Emission Tomography Employing Individual Channel Readout Electronics

The purpose of this study was to investigate the feasibility of a time-of-flight (TOF) brain positron emission tomography (PET) providing high-quality images. It consisted of 30 detector blocks arranged in a ring with a diameter of 257 mm and an axial field of view of 52.2 mm. Each detector block was composed of two detector modules and two application-specific integrated circuit (ASIC) chips. The detector module was composed of an 8 × 8 array of 3 × 3 mm² multi-pixel photon counters and an 8 × 8 array of 3.11 × 3.11 × 15 mm³ lutetium yttrium oxyorthosilicate scintillators. The 64-channel individual readout ASIC was used to acquire the position, energy, and time information of a detected gamma ray. A coincidence timing resolution of 187 ps full width at half maximum (FWHM) was achieved using a pair of channels of two detector modules. The energy resolution and spatial resolution were 6.6 ± 0.6% FWHM (without energy nonlinearity correction) and 2.5 mm FWHM, respectively. The results of this study demonstrate that the developed TOF brain PET could provide excellent performance, allowing for a reduction in radiation dose or scanning time for brain imaging due to improved sensitivity and signal-to-noise ratio.

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

A Temperature-Compensated Single-Crystal Silicon-on-Insulator (SOI) MEMS Oscillator with a CMOS Amplifier Chip

Self-sustained feedback oscillators referenced to MEMS/NEMS resonators have the potential for a wide range of applications in timing and sensing systems. In this paper, we describe a real-time temperature compensation approach to improving the long-term stability of such MEMS-referenced oscillators. This approach is implemented on a ~26.8 kHz self-sustained MEMS oscillator that integrates the fundamental in-plane mode resonance of a single-crystal silicon-on-insulator (SOI) resonator with a programmable and reconfigurable single-chip CMOS sustaining amplifier. Temperature compensation using a linear equation fit and look-up table (LUT) is used to obtain the near-zero closed-loop temperature coefficient of frequency (TCf) at around room temperature (~25 °C). When subject to small temperature fluctuations in an indoor environment, the temperature-compensated oscillator shows a >2-fold improvement in Allan deviation over the uncompensated counterpart on relatively long time scales (averaging time τ > 10,000 s), as well as overall enhanced stability throughout the averaging time range from τ = 1 to 20,000 s. The proposed temperature compensation algorithm has low computational complexity and memory requirement, making it suitable for implementation on energy-constrained platforms such as Internet of Things (IoT) sensor nodes.