A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

Optimizing Time Resolution Electronics for DMAPs

Depleted Monolithic Active Pixel Sensors (DMAPSs) are foreseen as an interesting choice for future high-energy physics experiments, mainly because of the reduced fabrication costs. However, they generally offer limited time resolution due to the stringent requirements of area and power consumption imposed by the targeted spatial resolution. This work describes a methodology to optimize the design of time-to-digital converter (TDC)-based timing electronics that takes advantage of the asymmetrical shape of the pulse at the output of the analog front-end (AFE). Following that methodology, a power and area efficient implementation fully compatible with the RD50-MPW3 solution is proposed. Simulation results show that the proposed solution offers a time resolution of 2.08 ns for a range of energies from 1000 e^- to 20,000 e^-, with minimum area and zero quiescent in-pixel power consumption.

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-in-memory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal-ferroelectric-metal-insulator-semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal-oxide-semiconductor FET, leading to a large MW (∼11 V), fast operation speed (<20 ns), and high endurance (∼10¹¹ cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.