Memory devices and applications for in-memory computing

Neural Network Training With Asymmetric Crosspoint Elements

Analog crossbar arrays comprising programmable non-volatile resistors are under intense investigation for acceleration of deep neural network training. However, the ubiquitous asymmetric conductance modulation of practical resistive devices critically degrades the classification performance of networks trained with conventional algorithms. Here we first describe the fundamental reasons behind this incompatibility. Then, we explain the theoretical underpinnings of a novel fully-parallel training algorithm that is compatible with asymmetric crosspoint elements. By establishing a powerful analogy with classical mechanics, we explain how device asymmetry can be exploited as a useful feature for analog deep learning processors. Instead of conventionally tuning weights in the direction of the error function gradient, network parameters can be programmed to successfully minimize the total energy (Hamiltonian) of the system that incorporates the effects of device asymmetry. Our technique enables immediate realization of analog deep learning accelerators based on readily available device technologies.

Dynamic Model of the Short-Term Synaptic Behaviors of PEDOT-based Organic Electrochemical Transistors with Modified Shockley Equations

Neuromorphic computing is an emerging area with prospects to break the energy efficiency bottleneck of artificial intelligence (AI). A crucial challenge for neuromorphic computing is understanding the working principles of artificial synaptic devices. As an emerging class of synaptic devices, organic electrochemical transistors (OECTs) have attracted significant interest due to ultralow voltage operation, analog conductance tuning, mechanical flexibility, and biocompatibility. However, little work has been focused on the first-principal modeling of the synaptic behaviors of OECTs. The simulation of OECT synaptic behaviors is of great importance to understanding the OECT working principles as neuromorphic devices and optimizing ultralow power consumption neuromorphic computing devices. Here, we develop a two-dimensional transient drift-diffusion model based on modified Shockley equations for poly(3,4-ethylenedioxythiophene) (PEDOT)-based OECTs. We reproduced the typical transistor characteristics of these OECTs including the unique non-monotonic transconductance-gate bias curve and frequency dependency of transconductance. Furthermore, typical synaptic phenomena, such as excitatory/inhibitory postsynaptic current (EPSC/IPSC), paired-pulse facilitation/depression (PPF/PPD), and short-term plasticity (STP), are also demonstrated. This work is crucial in guiding the experimental exploration of neuromorphic computing devices and has the potential to serve as a platform for future OECT device simulation based on a wide range of semiconducting materials.

Ultrahigh-Speed In-Memory Electronics Enabled by Proximity-Oxidation-Evolved Metal Oxide Redox Transistors

The pursuit of a universal device that combines nonvolatile multilevel storage, ultrafast writing/erasing speed, nondestructive readout, and embedded processing with low power consumption demands the development of innovative architectures. Although thin-film transistors and redox-based resistive-switching devices have independently been proven to be ideal building blocks for data processing and storage, it is still difficult to achieve both well-controlled multilevel memory and high-precision ultrafast processing in a single unit, even though this is essential for the large-scale hardware implementation of in-memory computing. In this work, an ultrafast (≈42 ns) and programable redox thin-film transistor (ReTFT) memory made of a proximity-oxidation-grown TiO₂ layer is developed, which has on/off ratio of 10⁵ , nonvolatile multilevel analog storage with a long retention time, strong durability, and high reliability. Utilizing the proof-of-concept ReTFTs, circuits capable of performing fundamental NOT, AND, and OR operations with reconfigurable logic-in-memory processing are developed. Further, on-demand signal memory-processing operations, like multi-terminal addressable memory, learning, pattern recognition, and classification, are explored for prospective application in neuromorphic hardware. This device, which operates on a fundamentally different mechanism, presents an alternate solution to the problems associated with the creation of high-performing in-memory processing technology.

Reconfigurable and Efficient Implementation of 16 Boolean Logics and Full-Adder Functions with Memristor Crossbar for Beyond von Neumann In-Memory Computing

The rise of emerging technologies such as Big Data, the Internet of Things, and artificial intelligence, which requires efficient power schemes, is driving brainstorming in data computing and storage technologies. In this study, merely relying on the fundamental structure of two memristors and a resistor, arbitrary Boolean logic can be reconfigured and calculated in two steps, while no additional voltage sources are needed beyond "±V_P " and 0, and all state reversals are based on memristor set switching. Utilizing the proposed logic scheme in an elegant form of unity structure and minimum cost, the implementation of a 1-bit adder is demonstrated economically, and a promising circuit scheme for the N-bit adder is exhibited. Some critical issues including the crosstalk problem, energy consumption, and peripheral circuits are further simulated and discussed. Compared with existing works on memristive logic, such methods support building a memristor-based digital in-memory calculation system with high functional reconfigurability, simple voltage sources, and low power and area consumption.

Chalcogenide optomemristors for multi-factor neuromorphic computation

Neuromorphic hardware that emulates biological computations is a key driver of progress in AI. For example, memristive technologies, including chalcogenide-based in-memory computing concepts, have been employed to dramatically accelerate and increase the efficiency of basic neural operations. However, powerful mechanisms such as reinforcement learning and dendritic computation require more advanced device operations involving multiple interacting signals. Here we show that nano-scaled films of chalcogenide semiconductors can perform such multi-factor in-memory computation where their tunable electronic and optical properties are jointly exploited. We demonstrate that ultrathin photoactive cavities of Ge-doped Selenide can emulate synapses with three-factor neo-Hebbian plasticity and dendrites with shunting inhibition. We apply these properties to solve a maze game through on-device reinforcement learning, as well as to provide a single-neuron solution to linearly inseparable XOR implementation.

Some types of machine learning rely on the interaction between multiple signals, which requires new devices for efficient implementation. Here, Sarwat et al demonstrate a memristor that is both optically and electronically active, enabling computational models such as three factor learning.

Conductance-Aware Quantization Based on Minimum Error Substitution for Non-Linear-Conductance-State Tolerance in Neural Computing Systems

Emerging resistive random-access memory (ReRAM) has demonstrated great potential in the achievement of the in-memory computing paradigm to overcome the well-known “memory wall” in current von Neumann architecture. The ReRAM crossbar array (RCA) is a promising circuit structure to accelerate the vital multiplication-and-accumulation (MAC) operations in deep neural networks (DNN). However, due to the nonlinear distribution of conductance levels in ReRAM, a large deviation exists in the mapping process when the trained weights that are quantized by linear relationships are directly mapped to the nonlinear conductance values from the realistic ReRAM device. This deviation degrades the inference accuracy of the RCA-based DNN. In this paper, we propose a minimum error substitution based on a conductance-aware quantization method to eliminate the deviation in the mapping process from the weights to the actual conductance values. The method is suitable for multiple ReRAM devices with different non-linear conductance distribution and is also immune to the device variation. The simulation results on LeNet5, AlexNet and VGG16 demonstrate that this method can vastly rescue the accuracy degradation from the non-linear resistance distribution of ReRAM devices compared to the linear quantization method.

An Integrated Photorefractive Analog Matrix-Vector Multiplier for Machine Learning

AI is fueling explosive growth in compute demand that traditional digital chip architectures cannot keep up with. Analog crossbar arrays enable power efficient synaptic signal processing with linear scaling on neural network size. We present a photonic photorefractive crossbar array for neural network training and inference on local analog memory. We discuss the concept and present results based on the first prototype hardware.

Experimental validation of state equations and dynamic route maps for phase change memristive devices

Phase Change Memory (PCM) is an emerging technology exploiting the rapid and reversible phase transition of certain chalcogenides to realize nanoscale memory elements. PCM devices are being explored as non-volatile storage-class memory and as computing elements for in-memory and neuromorphic computing. It is well-known that PCM exhibits several characteristics of a memristive device. In this work, based on the essential physical attributes of PCM devices, we exploit the concept of Dynamic Route Map (DRM) to capture the complex physics underlying these devices to describe them as memristive devices defined by a state-dependent Ohm's law. The efficacy of the DRM has been proven by comparing numerical results with experimental data obtained on PCM devices.

Hardware-Software Co-Design of an In-Memory Transformer Network Accelerator

Transformer networks have outperformed recurrent and convolutional neural networks in terms of accuracy in various sequential tasks. However, memory and compute bottlenecks prevent transformer networks from scaling to long sequences due to their high execution time and energy consumption. Different neural attention mechanisms have been proposed to lower computational load but still suffer from the memory bandwidth bottleneck. In-memory processing can help alleviate memory bottlenecks by reducing the transfer overhead between the memory and compute units, thus allowing transformer networks to scale to longer sequences. We propose an in-memory transformer network accelerator (iMTransformer) that uses a combination of crossbars and content-addressable memories to accelerate transformer networks. We accelerate transformer networks by (1) computing in-memory, thus minimizing the memory transfer overhead, (2) caching reusable parameters to reduce the number of operations, and (3) exploiting the available parallelism in the attention mechanism computation. To reduce energy consumption, the following techniques are introduced: (1) a configurable attention selector is used to choose different sparse attention patterns, (2) a content-addressable memory aided locality sensitive hashing helps to filter the number of sequence elements by their importance, and (3) FeFET-based crossbars are used to store projection weights while CMOS-based crossbars are used as an attentional cache to store attention scores for later reuse. Using a CMOS-FeFET hybrid iMTransformer introduced a significant energy improvement compared to the CMOS-only iMTransformer. The CMOS-FeFET hybrid iMTransformer achieved an 8.96× delay improvement and 12.57× energy improvement for the Vanilla transformers compared to the GPU baseline at a sequence length of 512. Implementing BERT using CMOS-FeFET hybrid iMTransformer achieves 13.71× delay improvement and 8.95× delay improvement compared to the GPU baseline at sequence length of 512. The hybrid iMTransformer also achieves a throughput of 2.23 K samples/sec and 124.8 samples/s/W using the MLPerf benchmark using BERT-large and SQuAD 1.1 dataset, an 11× speedup and 7.92× energy improvement compared to the GPU baseline.

CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks

Convolutional neural networks (CNNs) have gained much attention because they can provide superior complex image recognition through convolution operations. Convolution processes require repeated multiplication and accumulation operations, which are difficult tasks for conventional computing systems. Compute-in-memory (CIM) that uses parallel data processing is an ideal device structure for convolution operations. CIM based on two-terminal synaptic devices with a crossbar structure has been developed, but unwanted leakage current paths and the high-power consumption remain as the challenges. Here, we demonstrate integrated ferroelectric thin-film transistor (FeTFT) synaptic arrays that can provide efficient parallel programming and data processing for CNNs by the selective and accurate control of polarization in the ferroelectric layer. In addition, three-terminal FeTFTs can act as both nonvolatile memory and access device, which tackle issues from two-terminal devices. An integrated FeTFT synaptic array with parallel programming capabilities can perform convolution operations to extract image features with a high-recognition accuracy.

Electrically Reconfigurable Organic Logic Gates: A Promising Perspective on a Dual-Gate Antiambipolar Transistor

Electrically reconfigurable organic logic circuits are promising candidates for realizing new computation architectures, such as artificial intelligence and neuromorphic devices. In this study, multiple logic gate operations are attained based on a dual-gate organic antiambipolar transistor (DG-OAAT). The transistor exhibits a Λ-shaped transfer curve, namely, a negative differential transconductance at room temperature. It is important to note that the peak voltage of the drain current is precisely tuned by three input signals: bottom-gate, top-gate, and drain voltages. This distinctive feature enables multiple logic gate operations with "only a single DG-OAAT," which are not obtainable in conventional transistors. Five logic gate operations, which correspond to AND, OR, NAND, NOR, and XOR, are demonstrated by adjusting the bottom-gate and top-gate voltages. Moreover, varying the drain voltage makes it possible to reversibly switch two logic gates, e.g., NAND/NOR and OR/XOR. In addition, the DG-OAATs show a high degree of stability and reliability. The logic gate operations are observed even months later. The hysteresis in the transfer curves is also negligible. Thus, the device concept is promising for realizing multifunctional logic circuits with a simple transistor configuration. Hence, these findings are expected to surpass the current limitations in complementary metal-oxide-semiconductor devices.

A Neuromorphic Brain Interface based on RRAM Crossbar Arrays for High Throughput Real-time Spike Sorting

Real-time spike sorting and processing are crucial for closed-loop brain-machine interfaces and neural prosthetics. Recent developments in high-density multi-electrode arrays with hundreds of electrodes have enabled simultaneous recordings of spikes from a large number of neurons. However, the high channel count imposes stringent demands on real-time spike sorting hardware regarding data transmission bandwidth and computation complexity. Thus, it is necessary to develop a specialized real-time hardware that can sort neural spikes on the fly with high throughputs while consuming minimal power. Here, we present a real-time, low latency spike sorting processor that utilizes high-density CuO_x resistive crossbars to implement in-memory spike sorting in a massively parallel manner. We developed a fabrication process which is compatible with CMOS BEOL integration. We extensively characterized switching characteristics and statistical variations of the CuO_x memory devices. In order to implement spike sorting with crossbar arrays, we developed a template matching-based spike sorting algorithm that can be directly mapped onto RRAM crossbars. By using synthetic and in vivo recordings of extracellular spikes, we experimentally demonstrated energy efficient spike sorting with high accuracy. Our neuromorphic interface offers substantial improvements in area (~1000× less area), power (~200× less power), and latency (4.8μs latency for sorting 100 channels) for real-time spike sorting compared to other hardware implementations based on FPGAs and microcontrollers.

An adaptive synaptic array using Fowler–Nordheim dynamic analog memory

In this paper we present an adaptive synaptic array that can be used to improve the energy-efficiency of training machine learning (ML) systems. The synaptic array comprises of an ensemble of analog memory elements, each of which is a micro-scale dynamical system in its own right, storing information in its temporal state trajectory. The state trajectories are then modulated by a system level learning algorithm such that the ensemble trajectory is guided towards the optimal solution. We show that the extrinsic energy required for state trajectory modulation can be matched to the dynamics of neural network learning which leads to a significant reduction in energy-dissipated for memory updates during ML training. Thus, the proposed synapse array could have significant implications in addressing the energy-efficiency imbalance between the training and the inference phases observed in artificial intelligence (AI) systems.

While great progress has been made in the applications of machine learning models, training them on conventional computing hardware is an energy intensive process. Here, Mehta et al present an adaptive synaptic array offering considerable improvements in the energy efficiency of training.

Neuromorphic behaviour in discontinuous metal films

Physical systems that exhibit brain-like behaviour are currently under intense investigation as platforms for neuromorphic computing. We show that discontinuous metal films, comprising irregular flat islands on a substrate and formed using simple evaporation processes, exhibit correlated avalanches of electrical signals that mimic those observed in the cortex. We further demonstrate that these signals meet established criteria for criticality. We perform a detailed experimental investigation of the atomic-scale switching processes that are responsible for these signals, and show that they mimic the integrate-and-fire mechanism of biological neurons. Using numerical simulations and a simple circuit model, we show that the characteristic features of the switching events are dependent on the network state and the local position of the switch within the complex network. We conclude that discontinuous films provide an interesting potential platform for brain-inspired computing.

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS₂. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

Improved Performance of NbOx Resistive Switching Memory by In-Situ N Doping

Valence change memory (VCM) attracts numerous attention in memory applications, due to its high stability and low energy consumption. However, owing to the low on/off ratio of VCM, increasing the difficulty of information identification hinders the development of memory applications. We prepared N-doped NbO_x:N films (thickness = approximately 15 nm) by pulsed laser deposition at 200 °C. N-doping significantly improved the on/off ratio, retention time, and stability of the Pt/NbO_x:N/Pt devices, thus improving the stability of data storage. The Pt/NbO_x:N/Pt devices also achieved lower and centralized switching voltage distribution. The improved performance was mainly attributed to the formation of oxygen vacancy (V_O) + 2N clusters, which greatly reduced the ionic conductivity and total energy of the system, thus increasing the on/off ratio and stability. Moreover, because of the presence of Vo + 2N clusters, the conductive filaments grew in more localized directions, which led to a concentrated distribution of SET and RESET voltages. Thus, in situ N-doping is a novel and effective approach to optimize device performances for better information storage and logic circuit applications.

Programmable black phosphorus image sensor for broadband optoelectronic edge computing

Image sensors with internal computing capability enable in-sensor computing that can significantly reduce the communication latency and power consumption for machine vision in distributed systems and robotics. Two-dimensional semiconductors have many advantages in realizing such intelligent vision sensors because of their tunable electrical and optical properties and amenability for heterogeneous integration. Here, we report a multifunctional infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT). By controlling the stored charges in the gate dielectric layers electrically and optically, the bP-PPT’s electrical conductance and photoresponsivity can be locally or remotely programmed with 5-bit precision to implement an in-sensor convolutional neural network (CNN). The sensor array can receive optical images transmitted over a broad spectral range in the infrared and perform inference computation to process and recognize the images with 92% accuracy. The demonstrated bP image sensor array can be scaled up to build a more complex vision-sensory neural network, which will find many promising applications for distributed and remote multispectral sensing.

2D materials represent a promising platform for machine vision and edge computing applications, although usually limited to ultraviolet and visible wavelengths. Here, the authors report the realization of a programmable image sensor based on black phosphorus, implementing multispectral imaging and analog in-memory computing functionalities in the near- to mid-infrared range.

Interface Formation during the Growth of Phase Change Material Heterostructures Based on Ge-Rich Ge-Sb-Te Alloys

In this study, we present a full characterization of the electronic properties of phase change material (PCM) double-layered heterostructures deposited on silicon substrates. Thin films of amorphous Ge-rich Ge-Sb-Te (GGST) alloys were grown by physical vapor deposition on Sb₂Te₃ and on Ge₂Sb₂Te₅ layers. The two heterostructures were characterized in situ by X-ray and ultraviolet photoemission spectroscopies (XPS and UPS) during the formation of the interface between the first and the second layer (top GGST film). The evolution of the composition across the heterostructure interface and information on interdiffusion were obtained. We found that, for both cases, the final composition of the GGST layer was close to Ge₂SbTe₂ (GST212), which is a thermodynamically favorable off-stoichiometry GeSbTe alloy in the Sb-GeTe pseudobinary of the ternary phase diagram. Density functional theory calculations allowed us to calculate the density of states for the valence band of the amorphous phase of GST212, which was in good agreement with the experimental valence bands measured in situ by UPS. The same heterostructures were characterized by X-ray diffraction as a function of the annealing temperature. Differences in the crystallization process are discussed on the basis of the photoemission results.

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowire feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

Unraveling Crystallization Mechanisms and Electronic Structure of Phase-Change Materials by Large-Scale Ab Initio Simulations

Ge-Sb-Te ("GST") alloys are leading phase-change materials for digital memories and neuro-inspired computing. Upon fast crystallization, these materials form rocksalt-like phases with large structural and vacancy disorder, leading to an insulating phase at low temperature. Here, a comprehensive description of crystallization, structural disorder, and electronic properties of GeSb₂ Te₄ based on realistic, quantum-mechanically based ("ab initio") computer simulations with system sizes of more than 1000 atoms is provided. It is shown how an analysis of the crystallization mechanism based on the smooth overlap of atomic positions kernel reveals the evolution of both geometrical and chemical order. The connection between structural and electronic properties of the disordered, as-crystallized models, which are relevant to the transport properties of GST, is then studied. Furthermore, it is shown how antisite defects and extended Sb-rich motifs can lead to Anderson localization in the conduction band. Beyond memory applications, these findings are therefore more generally relevant to disordered rocksalt-like chalcogenides that exhibit self-doping, since they can explain the origin of Anderson insulating behavior in both p- and n-doped chalcogenide materials.

Miniaturizing neural networks for charge state autotuning in quantum dots

A key challenge in scaling quantum computers is the calibration and control of multiple qubits. In solid-state quantum dots (QDs), the gate voltages required to stabilize quantized charges are unique for each individual qubit, resulting in a high-dimensional control parameter space that must be tuned automatically. Machine learning techniques are capable of processing high-dimensional data—provided that an appropriate training set is available—and have been successfully used for autotuning in the past. In this paper, we develop extremely small feed-forward neural networks that can be used to detect charge-state transitions in QD stability diagrams. We demonstrate that these neural networks can be trained on synthetic data produced by computer simulations, and robustly transferred to the task of tuning an experimental device into a desired charge state. The neural networks required for this task are sufficiently small as to enable an implementation in existing memristor crossbar arrays in the near future. This opens up the possibility of miniaturizing powerful control elements on low-power hardware, a significant step towards on-chip autotuning in future QD computers.

Designing Conductive-Bridge Phase-Change Memory to Enable Ultralow Programming Power

Phase-change material (PCM) devices are one of the most mature nonvolatile memories. However, their high power consumption remains a bottleneck problem limiting the data storage density. One may drastically reduce the programming power by patterning the PCM volume down to nanometer scale, but that route incurs a stiff penalty from the tremendous cost associated with the complex nanofabrication protocols required. Instead, here a materials solution to resolve this dilemma is offered. The authors work with memory cells of conventional dimensions, but design/exploit a PCM alloy that decomposes into a heterogeneous network of nanoscale crystalline domains intermixed with amorphous ones. The idea is to confine the subsequent phase-change switching in the interface region of the crystalline nanodomain with its amorphous surrounding, forming/breaking "nano-bridges" that link up the crystalline domains into a conductive path. This conductive-bridge switching mechanism thus only involves nanometer-scale volume in programming, despite of the large areas in contact with the electrodes. The pore-like devices based on spontaneously phase-separated Ge₁₃ Sb₇₁ O₁₆ alloy enable a record-low programming energy, down to a few tens of femtojoule. The new PCM/fabrication is fully compatible with the current 3D integration technology, adding no expenses or difficulty in processing.

Dual-Ferroelectric-Coupling-Engineered Two-Dimensional Transistors for Multifunctional In-Memory Computing

In-memory computing featuring a radical departure from the von Neumann architecture is promising to substantially reduce the energy and time consumption for data-intensive computation. With the increasing challenges facing silicon complementary metal-oxide-semiconductor (CMOS) technology, developing in-memory computing hardware would require a different platform to deliver significantly enhanced functionalities at the material and device level. Here, we explore a dual-gate two-dimensional ferroelectric field-effect transistor (2D FeFET) as a basic device to form both nonvolatile logic gates and artificial synapses, addressing in-memory computing simultaneously in digital and analog spaces. Through diversifying the electrostatic behaviors in 2D transistors with the dual-ferroelectric-coupling effect, rich logic functionalities including linear (AND, OR) and nonlinear (XNOR) gates were obtained in unipolar (MoS₂) and ambipolar (MoTe₂) FeFETs. Combining both types of 2D FeFETs in a heterogeneous platform, an important computation circuit, i.e., a half-adder, was successfully constructed with an area-efficient two-transistor structure. Furthermore, with the same device structure, several key synaptic functions are shown at the device level, and an artificial neural network is simulated at the system level, manifesting its potential for neuromorphic computing. These findings highlight the prospects of dual-gate 2D FeFETs for the development of multifunctional in-memory computing hardware capable of both digital and analog computation.

Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array

In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system’s operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 10⁵ s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications.

Retinomorphic optoelectronic devices for intelligent machine vision

Biological visual system can efficiently handle optical information within the retina and visual cortex of the brain, which suggests an alternative approach for the upgrading of the current low-intelligence, large energy consumption, and complex circuitry of the artificial vision system for high-performance edge computing applications. In recent years, retinomorphic machine vision based on the integration of optoelectronic image sensors and processors has been regarded as a promising candidate to improve this phenomenon. This novel intelligent machine vision technology can perform information preprocessing near or even within the sensor in the front end, thereby reducing the transmission of redundant raw data and improving the efficiency of the back-end processor for high-level computing tasks. In this contribution, we try to present a comprehensive review on the recent progress achieved in this emergent field.

A crossbar array of magnetoresistive memory devices for in-memory computing

Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-power alternatives to fully digital approaches^1-3. One notable example is in-memory computing based on crossbar arrays of non-volatile memories^4-7 that execute, in an analogue manner, multiply-accumulate operations prevalent in artificial neural networks. Various non-volatile memories-including resistive memory^8-13, phase-change memory^14,15 and flash memory^16-19-have been used for such approaches. However, it remains challenging to develop a crossbar array of spin-transfer-torque magnetoresistive random-access memory (MRAM)^20-22,  despite the technology's practical advantages such as endurance and large-scale commercialization⁵. The difficulty stems from the low resistance of MRAM, which would result in large power consumption in a conventional crossbar array that uses current summation for analogue multiply-accumulate operations. Here we report a 64 × 64 crossbar array based on MRAM cells that overcomes the low-resistance issue with an architecture that uses resistance summation for analogue multiply-accumulate operations. The array is integrated with readout electronics in 28-nanometre complementary metal-oxide-semiconductor technology. Using this array, a two-layer perceptron is implemented to classify 10,000 Modified National Institute of Standards and Technology digits with an accuracy of 93.23 per cent (software baseline: 95.24 per cent). In an emulation of a deeper, eight-layer Visual Geometry Group-8 neural network with measured errors, the classification accuracy improves to 98.86 per cent (software baseline: 99.28 per cent). We also use the array to implement a single layer in a ten-layer neural network to realize face detection with an accuracy of 93.4 per cent.

Applying Neuromorphic Computing Simulation in Band Gap Prediction and Chemical Reaction Classification

The rapidly developing artificial intelligence (AI) requires revolutionary computing architectures to break the energy efficiency bottleneck caused by the traditional von Neumann computing architecture. In addition, the emerging brain-machine interface also requires computational circuitry that can conduct large parallel computational tasks with low energy cost and good biocompatibility. Neuromorphic computing, a novel computational architecture emulating human brains, has drawn significant interest for the aforementioned applications due to its low energy cost, capability to parallelly process large-scale data, and biocompatibility. Most efforts in the domain of neuromorphic computing focus on addressing traditional AI problems, such as handwritten digit recognition and file classification. Here, we demonstrate for the first time that current neuromorphic computing techniques can be used to solve key machine learning questions in cheminformatics. We predict the band gaps of small-molecule organic semiconductors and classify chemical reaction types with a simulated neuromorphic circuitry. Our work can potentially guide the design and fabrication of elementary devices and circuitry for neuromorphic computing specialized for chemical purposes.

Evolution and modulation of Ag filament dynamics within memristive devices based on necklace-like Ag@TiO2nanowire networks

Random nanowire networks (NWNs) are regarded as promising memristive materials for applications in information storage, selectors, and neuromorphic computing. The further insight to understand their resistive switching properties and conduction mechanisms is crucial to realize the full potential of random NWNs. Here, a novel planar memristive device based on necklace-like structure Ag@TiO₂NWN is reported, in which a strategy only using water to tailor the TiO₂shell on Ag core for necklace-like core-shell structure is developed to achieve uniform topology connectivity. With analyzing the influence of compliance current on resistive switching characteristics and further tracing evolution trends of resistance state during the repetitive switching cycles, two distinctive evolution trends of low resistance state failure and high resistance state failure are revealed, which bear resemblance to memory loss and consolidation in biological systems. The underlying conduction mechanisms are related to the modulation of the Ag accumulation dynamics inside the filaments at cross-point junctions within conductive paths of NWNs. An optimizing principle is then proposed to design reproducible and reliable threshold switching devices by tuning the NWN density and electrical stimulation. The optimized threshold switching devices have a high ON/OFF ratio of ∼10⁷with threshold voltage as low as 0.35 V. This work will provide insights into engineering random NWNs for diverse functions by modulating external excitation and optimizing NWN parameters to satisfy specific applications, transforming from neuromorphic systems to threshold switching devices as selectors.

Engineering Spiking Neurons Using Threshold Switching Devices for High-Efficient Neuromorphic Computing

Inspired by the human brain, the spike-based neuromorphic system has attracted strong research enthusiasm because of the high energy efficiency and powerful computational capability, in which the spiking neurons and plastic synapses are two fundamental building blocks. Recently, two-terminal threshold switching (TS) devices have been regarded as promising candidates for building spiking neurons in hardware. However, how circuit parameters affect the spiking behavior of TS-based neurons is still an open question. Here, based on a leaky integrate-and-fire (LIF) neuron circuit, we systematically study the effect of both the extrinsic and intrinsic factors of NbO x -based TS neurons on their spiking behaviors. The extrinsic influence factors contain input intensities, connected synaptic weights, and parallel capacitances. To illustrate the effect of intrinsic factors, including the threshold voltage, holding voltage, and high/low resistance states of NbO x devices, we propose an empirical model of the fabricated NbO x devices, fitting well with the experimental results. The results indicate that with enhancing the input intensity, the spiking frequency increases first then decreases after reaching a peak value. Except for the connected synaptic weights, all other parameters can modulate the spiking peak frequency under high enough input intensity. Also, the relationship between energy consumption per spike and frequency of the neuron cell is further studied, leading guidance to design neuron circuits in a system to obtain the lowest energy consumption. At last, to demonstrate the practical applications of TS-based neurons, we construct a spiking neural network (SNN) to control the cart-pole using reinforcement learning, obtaining a reward score up to 450. This work provides valuable guidance on building compact LIF neurons based on TS devices and further bolsters the construction of high-efficiency neuromorphic systems.

Energy-adaptive resistive switching with controllable thresholds in insulator–metal transition

Adaptive energy-scaling resistive switching with active response and self-regulation via controllable insulator–metal transition shows promise in energy-efficient devices.

Global minimization via classical tunneling assisted by collective force field formation

Simple elements interacting in networks can give rise to intricate emergent behaviors. Examples such as synchronization and phase transitions often apply in many contexts, as many different systems may reduce to the same effective model. Here, we demonstrate such a behavior in a model inspired by memristors. When weakly driven, the system is described by movement in an effective potential, but when strongly driven, instabilities cause escapes from local minima, which can be interpreted as an unstable tunneling mechanism. We dub this collective and nonperturbative effect a “Lyapunov force,” which steers the system toward the global minimum of the potential function, even if the full system has a constellation of equilibrium points growing exponentially with the system size. This mechanism is appealing for its physical relevance in nanoscale physics and for its possible applications in optimization, Monte Carlo schemes, and machine learning.

Suppressed electronic contribution in thermal conductivity of Ge2Sb2Se4Te

Integrated nanophotonics is an emerging research direction that has attracted great interests for technologies ranging from classical to quantum computing. One of the key-components in the development of nanophotonic circuits is the phase-change unit that undergoes a solid-state phase transformation upon thermal excitation. The quaternary alloy, Ge2Sb2Se4Te, is one of the most promising material candidates for application in photonic circuits due to its broadband transparency and large optical contrast in the infrared spectrum. Here, we investigate the thermal properties of Ge2Sb2Se4Te and show that upon substituting tellurium with selenium, the thermal transport transitions from an electron dominated to a phonon dominated regime. By implementing an ultrafast mid-infrared pump-probe spectroscopy technique that allows for direct monitoring of electronic and vibrational energy carrier lifetimes in these materials, we find that this reduction in thermal conductivity is a result of a drastic change in electronic lifetimes of Ge2Sb2Se4Te, leading to a transition from an electron-dominated to a phonon-dominated thermal transport mechanism upon selenium substitution. In addition to thermal conductivity measurements, we provide an extensive study on the thermophysical properties of Ge2Sb2Se4Te thin films such as thermal boundary conductance, specific heat, and sound speed from room temperature to 400 °C across varying thicknesses.

Natural Acidic Polysaccharide-Based Memristors for Transient Electronics: Highly Controllable Quantized Conductance for Integrated Memory and Nonvolatile Logic Applications

As a leading candidate for further memory and computing applications, memristors are being developed in an important direction of transient electronics. Herein, wafer-scale acidic polysaccharide thin films are reported as promising materials for memristors with remarkable transient characteristics. The memristor shows freestanding and lightweight features, and can be fully dissolved in deionized water within 3.5 s. More importantly, the ion-confinement capability of acidic polysaccharides where the cations can interact with the ionizable acid groups enables atomic manipulation of conductive filament. As a result, (i) a single device can produce 16 highly controllable and independent quantized conductance (QC) states with quasi-nonvolatile and nonvolatile characteristics and (ii) QC switching can be performed with ultrafast speed (2-5 ns) and low energy consumption (0.6-16 pJ). These remarkable features make the memristor promising for fast, low-power, and high-density memory and computing applications. Based on QC switching, the encoding/decoding and nonvolatile basic Boolean logic are designed and implemented. More importantly, "stateful" material implication logic which is promising for future in-memory computing is demonstrated with QC switching. These results significantly advance acidic polysaccharides to develop nanodevices with quantum effects.

CMOS back-end compatible memristors for in situ digital and neuromorphic computing applications

In-memory logic calculations and brain-inspired artificial synaptic neuromorphic computing are expected to solve the limitations of the traditional von Neumann computing architecture. The data processing efficiency of the traditional von Neumann architecture is inherently limited by its physically separated processing and storage units, and thus data transmission besides calculation leads to a limited calculation speed and additional high-power consumption. In addition, traditional digital logic calculations and analog calculations have greater limitations in conversion. Herein, we report a flexible two-terminal memristor based on SiCO:H, which is a porous low-k back-end complementary metal-oxide-semiconductor (CMOS)-compatible material. Due to its low operating voltage (200 mV) and fast response speed (100 ns), it could perform digital memory calculation and neuromorphic calculation simultaneously. The memristor could realize a transition from short-term to long-term plasticity in the process of enhancement and inhibition during neuromorphic calculation, with high biological reality. In digital logic calculations, IMP-based and MAGIC-based logic calculations were verified. In neuromorphic computing, an Ag ion-based conductive filament was introduced. The relationship between the temporal dynamics of the conductance evolution and the diffusive dynamics of the Ag active metal could be modulated by the external programming electric field strength. The synapses and neuron dynamics in biology were faithfully simulated, realizing a transition from short-term to long-term plasticity in the process of enhancement and inhibition, which has high compatibility and scalability, proposing a novel solution for the next generation of computer architectures.

Design of In-Memory Parallel-Prefix Adders

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.

ReSe2-Based RRAM and Circuit-Level Model for Neuromorphic Computing

Resistive random-access memory (RRAM) devices have drawn increasing interest for the simplicity of its structure, low power consumption and applicability to neuromorphic computing. By combining analog computing and data storage at the device level, neuromorphic computing system has the potential to meet the demand of computing power in applications such as artificial intelligence (AI), machine learning (ML) and Internet of Things (IoT). Monolayer rhenium diselenide (ReSe2), as a two-dimensional (2D) material, has been reported to exhibit non-volatile resistive switching (NVRS) behavior in RRAM devices with sub-nanometer active layer thickness. In this paper, we demonstrate stable multiple-step RESET in ReSe2 RRAM devices by applying different levels of DC electrical bias. Pulse measurement has been conducted to study the neuromorphic characteristics. Under different height of stimuli, the ReSe2 RRAM devices have been found to switch to different resistance states, which shows the potentiation of synaptic applications. Long-term potentiation (LTP) and depression (LTD) have been demonstrated with the gradual resistance switching behaviors observed in long-term plasticity programming. A Verilog-A model is proposed based on the multiple-step resistive switching behavior. By implementing the LTP/LTD parameters, an artificial neural network (ANN) is constructed for the demonstration of handwriting classification using Modified National Institute of Standards and Technology (MNIST) dataset.

Tailoring the Structural and Optical Properties of Germanium Telluride Phase-Change Materials by Indium Incorporation

Chalcogenide phase-change materials (PCMs) based random access memory (PCRAM) enter the global memory market as storage-class memory (SCM), holding great promise for future neuro-inspired computing and non-volatile photonic applications. The thermal stability of the amorphous phase of PCMs is a demanding property requiring further improvement. In this work, we focus on indium, an alloying ingredient extensively exploited in PCMs. Starting from the prototype GeTe alloy, we incorporated indium to form three typical compositions along the InTe-GeTe tie line: InGe3Te4, InGeTe2 and In3GeTe4. The evolution of structural details, and the optical properties of the three In-Ge-Te alloys in amorphous and crystalline form, was thoroughly analyzed via ab initio calculations. This study proposes a chemical composition possessing both improved thermal stability and sizable optical contrast for PCM-based non-volatile photonic applications.

Stochastic Spiking Behavior in Neuromorphic Networks Enables True Random Number Generation

There is currently a great deal of interest in the use of nanoscale devices to emulate the behaviors of neurons and synapses and to facilitate brain-inspired computation. Here, it is shown that percolating networks of nanoparticles exhibit stochastic spiking behavior that is strikingly similar to that observed in biological neurons. The spiking rate can be controlled by the input stimulus, similar to "rate coding" in biology, and the distributions of times between events are log-normal, providing insights into the atomic-scale spiking mechanism. The stochasticity of the spiking behavior is then used for true random number generation, and the high quality of the generated random bit-streams is demonstrated, opening up promising routes toward integration of neuromorphic computing with secure information processing.

Atomic-Layer-Deposition-Based 2D Transition Metal Chalcogenides: Synthesis, Modulation, and Applications

Transition metal chalcogenides (TMCs) are a large family of 2D materials with different properties, and are promising candidates for a wide range of applications such as nanoelectronics, sensors, energy conversion, and energy storage. In the research of new materials, the development and investigation of industry-compatible synthesis techniques is of key importance. In this respect, it is important to study 2D TMC materials synthesized by the atomic layer deposition (ALD) technique, which is widely applied in industries. In addition to the synthesis of 2D TMCs, ALD is used to modulate the characteristic of 2D TMCs such as their carrier density and morphology. So far, the improvement of thin film uniformity without oxidation and the synthesis of low-dimensional nanomaterials on 2D TMCs have been the research focus. Herein, the synthesis and modulation of 2D TMCs by ALD is described, and the characteristics of ALD-based TMCs used in nanoelectronics, sensors, and energy applications are discussed.

Stimuli-Responsive Memristive Materials for Artificial Synapses and Neuromorphic Computing

Neuromorphic computing holds promise for building next-generation intelligent systems in a more energy-efficient way than the conventional von Neumann computing architecture. Memristive hardware, which mimics biological neurons and synapses, offers high-speed operation and low power consumption, enabling energy- and area-efficient, brain-inspired computing. Here, recent advances in memristive materials and strategies that emulate synaptic functions for neuromorphic computing are highlighted. The working principles and characteristics of biological neurons and synapses, which can be mimicked by memristive devices, are presented. Besides device structures and operation with different external stimuli such as electric, magnetic, and optical fields, how memristive materials with a rich variety of underlying physical mechanisms can allow fast, reliable, and low-power neuromorphic applications is also discussed. Finally, device requirements are examined and a perspective on challenges in developing memristive materials for device engineering and computing science is given.

Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors

Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS₂ transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR/XOR computations and the skewed SRAM cell can achieve in-memory NAND/NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

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We demonstrate the symmetrical 4T2R and skewed 3T3R computing-in-memory SRAM

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Both computing-in-memory SRAM cells consume six components, exhibiting higher area efficiency

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The designed computing-in-memory SRAM cells support multiple Boolean logic operations

Statistical Analysis of Uniform Switching Characteristics of Ta2O5-Based Memristors by Embedding In-Situ Grown 2D-MoS2 Buffer Layers

A memristor based on emerging resistive random-access memory (RRAM) is a promising candidate for use as a next-generation neuromorphic computing device which overcomes the von Neumann bottleneck. Meanwhile, due to their unique properties, including atomically thin layers and surface smoothness, two-dimensional (2D) materials are being widely studied for implementation in the development of new information-processing electronic devices. However, inherent drawbacks concerning operational uniformities, such as device-to-device variability, device yield, and reliability, are huge challenges in the realization of concrete memristor hardware devices. In this study, we fabricated Ta₂O₅-based memristor devices, where a 2D-MoS₂ buffer layer was directly inserted between the Ta₂O₅ switching layer and the Ag metal electrode to improve uniform switching characteristics in terms of switching voltage, the distribution of resistance states, endurance, and retention. A 2D-MoS₂ layered buffer film with a 5 nm thickness was directly grown on the Ta₂O₅ switching layer by the atomic-pressure plasma-enhanced chemical vapor deposition (AP-PECVD) method, which is highly uniform and provided a superior yield of 2D-MoS₂ film. It was observed that the switching operation was dramatically stabilized via the introduction of the 2D-MoS₂ buffer layer compared to a pristine device without the buffer layer. It was assumed that the difference in mobility and reduction rates between Ta₂O₅ and MoS₂ caused the narrow localization of ion migration, inducing the formation of more stable conduction filament. In addition, an excellent yield of 98% was confirmed while showing cell-to-cell operation uniformity, and the extrinsic and intrinsic variabilities in operating the device were highly uniform. Thus, the introduction of a MoS₂ buffer layer could improve highly reliable memristor device switching operation.

Dopant-Tunable Ultrathin Transparent Conductive Oxides for Efficient Energy Conversion Devices

Ultrathin film-based transparent conductive oxides (TCOs) with a broad work function (WF) tunability are highly demanded for efficient energy conversion devices. However, reducing the film thickness below 50 nm is limited due to rapidly increasing resistance; furthermore, introducing dopants into TCOs such as indium tin oxide (ITO) to reduce the resistance decreases the transparency due to a trade-off between the two quantities. Herein, we demonstrate dopant-tunable ultrathin (≤ 50 nm) TCOs fabricated via electric field-driven metal implantation (m-TCOs; m = Ni, Ag, and Cu) without compromising their innate electrical and optical properties. The m-TCOs exhibit a broad WF variation (0.97 eV), high transmittance in the UV to visible range (89-93% at 365 nm), and low sheet resistance (30-60 Ω cm^-2). Experimental and theoretical analyses show that interstitial metal atoms mainly affect the change in the WF without substantial losses in optical transparency. The m-ITOs are employed as anode or cathode electrodes for organic light-emitting diodes (LEDs), inorganic UV LEDs, and organic photovoltaics for their universal use, leading to outstanding performances, even without hole injection layer for OLED through the WF-tailored Ni-ITO. These results verify the proposed m-TCOs enable effective carrier transport and light extraction beyond the limits of traditional TCOs.

Scalable massively parallel computing using continuous-time data representation in nanoscale crossbar array

The growth of connected intelligent devices in the Internet of Things has created a pressing need for real-time processing and understanding of large volumes of analogue data. The difficulty in boosting the computing speed renders digital computing unable to meet the demand for processing analogue information that is intrinsically continuous in magnitude and time. By utilizing a continuous data representation in a nanoscale crossbar array, parallel computing can be implemented for the direct processing of analogue information in real time. Here, we propose a scalable massively parallel computing scheme by exploiting a continuous-time data representation and frequency multiplexing in a nanoscale crossbar array. This computing scheme enables the parallel reading of stored data and the one-shot operation of matrix-matrix multiplications in the crossbar array. Furthermore, we achieve the one-shot recognition of 16 letter images based on two physically interconnected crossbar arrays and demonstrate that the processing and modulation of analogue information can be simultaneously performed in a memristive crossbar array.

Ultrafast machine vision with artificial neural network devices based on a GaN-based micro-LED array

GaN-based micro-LED is an emerging display and communication device, which can work as well as a photodetector, enabling possible applications in machine vision. In this work, we measured the characteristics of micro-LED based photodetector experimentally and proposed a feasible simulation of a novel artificial neural network (ANN) device for the first time based on a micro-LED based photodetector array, providing ultrafast imaging (∼133 million bins per second) and a high image recognition rate. The array itself constitutes a neural network, in which the synaptic weights are tunable by the bias voltage. It has the potentials to be integrated with novel machine vision and reconfigurable computing applications, acting as a role of acceleration and similar functionality expansion. Also, the multi-functionality of micro-LED broadens its application potentials of combining ANN with display and communication.

2D materials-based homogeneous transistor-memory architecture for neuromorphic hardware

[Figure: see text].