New Opportunities for High-Performance Source-Gated Transistors Using Unconventional Materials

Ternary Logic Circuit and Neural Network Integration via Small Molecule-Based Antiambipolar Vertical Electrochemical Transistor

Circuits based on organic electrochemical transistors (OECTs) have great potential in the fields of biosensors and artificial neural computation due to their biocompatibility and neural similarity. However, the integration of OECT-based circuits lags far behind other emerging electronics. Here, ternary inverters based on antiambipolar vertical OECTs (vOECTs) and their integration with the establishment of neural networks are demonstrated. Specifically, by adopting a small molecule (t-gdiPDI) as the channel of vOECT, high antiambipolar performance, with current density of 33.9 ± 2.1 A cm-2 under drain voltage of 0.1 V, peak voltage ≈0 V, low driving voltage < ± 0.6 V, and current on/off ratio > 106, are realized. Consequently, vertically stacked ternary circuits based solely on OECTs are constructed for the first time, showing three distinct logical states and high integration density. By further developing inverter array as the internal fundamental units of ternary weight network hardware circuits for ternary processing and computation, it demonstrates excellent data classification and recognition capabilities. This work demonstrates the possibility of constructing multi-valued logic circuits by OECTs and promotes a new strategy for high-density integration and multivalued computing systems based on organic circuits.

Ultrahigh-gain organic transistors based on van der Waals metal-barrier interlayer-semiconductor junction

Intrinsic gain is a vital figure of merit in transistors, closely related to signal amplification, operation voltage, power consumption, and circuit simplification. However, organic thin-film transistors (OTFTs) targeted at high gain have suffered from challenges such as narrow subthreshold operating voltage, low-quality interface, and uncontrollable barrier. Here, we report a van der Waals metal-barrier interlayer-semiconductor junction-based OTFT, which shows ultrahigh performance including ultrahigh gain of ~104, low saturation voltage, negligible hysteresis, and good stability. The high-quality van der Waals-contacted junctions are mainly attributed to patterning EGaIn liquid metal electrodes by low-energy microfluidic processes. The wide-bandgap semiconductor Ga2O3 as barrier interlayer is achieved by in situ surface oxidation of EGaIn electrodes, allowing for an adjustable barrier height and expected thermionic emission properties. The organic inverters with a high gain of 5130 and a simplified current stabilizer are further demonstrated, paving a way for high-gain and low-power organic electronics.

The Schottky barrier transistor in emerging electronic devices

This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable field-effect transistors (FETs) for sensors, neuromorphic hardware and security applications. Similarly, judicious use of an SB can be an asset for applications involving Josephson junction FETs.

High-Performance Organic Source-Gated Transistors Enabled by the Indium-Tin Oxide-Diketopyrrolopyrrole Polymer Interface

Source-gated transistors are a new driver of low-power high-gain thin-film electronics. However, source-gated transistors based on organic semiconductors are not widely investigated yet despite their potential for future display and sensor technologies. We report on the fabrication and modeling of high-performance organic source-gated transistors utilizing a critical junction formed between indium-tin oxide and diketopyrrolopyrrole polymer. This partially blocked hole-injection interface is shown to offer both a sufficient level of drain currents and a strong depletion effect necessary for source pinch-off. As a result, our transistors exhibit a set of outstanding metrics, including an intrinsic gain of 160 V/V, an output resistance of 4.6 GΩ, and a saturation coefficient of 0.2 at an operating voltage of 5 V. Drift-diffusion simulation is employed to reproduce and rationalize the experimental data. The modeling reveals that the effective contact length is significantly reduced in an interdigitated electrode geometry, eventually contributing to the realization of low-voltage saturation.

High-performance and low-power source-gated transistors enabled by a solution-processed metal oxide homojunction

Cost-effective fabrication of mechanically flexible low-power electronics is important for emerging applications including wearable electronics, artificial intelligence, and the Internet of Things. Here, solution-processed source-gated transistors (SGTs) with an unprecedented intrinsic gain of ~2,000, low saturation voltage of +0.8 ± 0.1 V, and a ~25.6 μW power consumption are realized using an indium oxide In₂O₃/In₂O₃:polyethylenimine (PEI) blend homojunction with Au contacts on Si/SiO₂. Kelvin probe force microscopy confirms source-controlled operation of the SGT and reveals that PEI doping leads to more effective depletion of the reverse-biased Schottky contact source region. Furthermore, using a fluoride-doped AlO_x gate dielectric, rigid (on a Si substrate) and flexible (on a polyimide substrate) SGTs were fabricated. These devices exhibit a low driving voltage of +2 V and power consumption of ~11.5 μW, yielding inverters with an outstanding voltage gain of >5,000. Furthermore, electrooculographic (EOG) signal monitoring can now be demonstrated using an SGT inverter, where a ~1.0 mV EOG signal is amplified to over 300 mV, indicating significant potential for applications in wearable medical sensing and human-computer interfacing.

New Approach to Low-Power-Consumption, High-Performance Photodetectors Enabled by Nanowire Source-Gated Transistors

Power consumption makes next-generation large-scale photodetection challenging. In this work, the source-gated transistor (SGT) is adopted first as a photodetector, demonstrating the expected low power consumption and high photodetection performance. The SGT is constructed by the functional sulfur-rich shelled GeS nanowire (NW) and low-function metal, displaying a low saturated voltage of 0.61 V ± 0.29 V and an extremely low power consumption of 7.06 pW. When the as-constructed NW SGT is used as a photodetector, the maximum value of the power consumption is as low as 11.96 nW, which is far below that of the reported phototransistors working in the saturated region. Furthermore, benefiting from the adopted SGT device, the photodetector shows a high photovoltage of 6.6 × 10^-1 V, a responsivity of 7.86 × 10¹² V W^-1, and a detectivity of 5.87 × 10¹³ Jones. Obviously, the low power consumption and excellent responsivity and detectivity enabled by NW SGT promise a new approach to next-generation, high-performance photodetection technology.

Azide-functionalized ligand enabling organic-inorganic hybrid dielectric for high-performance solution-processed oxide transistors

We propose a highly efficient crosslinking strategy for organic-inorganic hybrid dielectric layers using azide-functionalized acetylacetonate, which covalently connect inorganic particles to polymers, enabling highly efficient inter- and intra-crosslinking of organic and inorganic inclusions, resulting in a dense and defect-free thin-film morphology. From the optimized processing conditions, we obtained an excellent dielectric strength of over 4.0 MV cm-1, a high dielectric constant of ~14, and a low surface energy of 38 mN m-1. We demonstrated the fabrication of exceptionally high-performance, hysteresis-free n-type solution-processed oxide transistors comprising an In2O3/ZnO double layer as an active channel with an electron mobility of over 50 cm2 V-1 s-1, on/off ratio of ~107, subthreshold swing of 108 mV dec-1, and high bias-stress stability. From temperature-dependent I-V analyses combined with charge transport mechanism analyses, we demonstrated that the proposed hybrid dielectric layer provides percolation-limited charge transport for the In2O3/ZnO double layer under field-effect conditions.