Machine Learning Driven Channel Thickness Optimization in Dual-Layer Oxide Thin-Film Transistors for Advanced Electrical Performance

Machine learning (ML) provides temporal advantage and performance improvement in practical electronic device design by adaptive learning. Herein, Bayesian optimization (BO) is successfully applied to the design of optimal dual-layer oxide semiconductor thin film transistors (OS TFTs). This approach effectively manages the complex correlation and interdependency between two oxide semiconductor layers, resulting in the efficient design of experiment (DoE) and reducing the trial-and-error. Considering field effect mobility (𝜇) and threshold voltage (Vth ) simultaneously, the dual-layer structure designed by the BO model allows to produce OS TFTs with remarkable electrical performance while significantly saving an amount of experimental trial (only 15 data sets are required). The optimized dual-layer OS TFTs achieve the enhanced field effect mobility of 36.1 cm2  V-1  s-1 and show good stability under bias stress with negligible difference in its threshold voltage compared to conventional IGZO TFTs. Moreover, the BO algorithm is successfully customized to the individual preferences by applying the weight factors assigned to both field effect mobility (𝜇) and threshold voltage (Vth ).

Low-Voltage Solution-Processed Zinc-Doped CuI Thin Film Transistors with NOR Logic and Artificial Synaptic Function

Low-voltage Zn-doped CuI thin film transistors (TFTs) gated by chitosan dielectric were fabricated at a low temperature. The Zn-doped CuI TFT exhibited a more superior on/off current ratio than CuI TFT due to the substitution or supplementation of copper vacancies by Zn ions. The Zn-doped CuI films were characterized by scanning electron microscope, X-ray diffraction, and X-ray photoelectron spectroscopy. The Zn-doped CuI TFTs exhibited an on/off current ratio of 1.58 × 104, a subthreshold swing of 70 mV/decade, and a field effect mobility of 0.40 cm2V-1s-1, demonstrating good operational stability. Due to the electric-double-layer (EDL) effect and high specific capacitance (17.3 μF/cm2) of chitosan gate dielectric, Zn-doped CuI TFT operates at a voltage below -2 V. The threshold voltage is -0.2 V. In particular, we have prepared Zn-doped CuI TFTs with two in-plane gates and NOR logic operation is implemented on such TFTs. In addition, using the ion relaxation effect and EDL effect of chitosan film, a simple pain neuron simulation is realized on such a p-type TFTs for the first time through the bottom gate to regulate the carrier transport of the channel. This p-type device has promising applications in low-cost electronic devices, complementary electronic circuit, and biosensors.

The Schottky barrier transistor in emerging electronic devices

This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable field-effect transistors (FETs) for sensors, neuromorphic hardware and security applications. Similarly, judicious use of an SB can be an asset for applications involving Josephson junction FETs.

Improvement in Switching Characteristics and Bias Stability of Solution-Processed Zinc-Tin Oxide Thin Film Transistors via Simple Low-Pressure Thermal Annealing Treatment

In this study, we used a low-pressure thermal annealing (LPTA) treatment to improve the switching characteristics and bias stability of zinc-tin oxide (ZTO) thin film transistors (TFTs). For this, we first fabricated the TFT and then applied the LPTA treatment at temperatures of 80 °C and 140 °C. The LPTA treatment reduced the number of defects in the bulk and interface of the ZTO TFTs. In addition, the changes in the water contact angle on the ZTO TFT surface indicated that the LPTA treatment reduced the surface defects. Hydrophobicity suppressed the off-current and instability under negative bias stress because of the limited absorption of moisture on the oxide surface. Moreover, the ratio of metal-oxygen bonds increased, while the ratio of oxygen-hydrogen bonds decreased. The reduced action of hydrogen as a shallow donor induced improvements in the on/off ratio (from 5.5 × 103 to 1.1 × 107) and subthreshold swing (8.63 to V·dec-1 and 0.73 V·dec-1), producing ZTO TFTs with excellent switching characteristics. In addition, device-to-device uniformity was significantly improved because of the reduced defects in the LPTA-treated ZTO TFTs.

Performance Enhancement of Lead-Free 2D Tin Halide Perovskite Transistors by Surface Passivation and Its Impact on Non-Volatile Photomemory Characteristics

Two-dimensional (2D) tin (Sn)-based perovskites have recently received increasing research attention for perovskite transistor application. Although some progress is made, Sn-based perovskites have long suffered from easy oxidation from Sn²⁺ to Sn⁴⁺ , leading to undesirable p-doping and instability. In this study, it is demonstrated that surface passivation by phenethylammonium iodide (PEAI) and 4-fluorophenethylammonium iodide (FPEAI) effectively passivates surface defects in 2D phenethylammonium tin iodide (PEA₂ SnI₄ ) films, increases the grain size by surface recrystallization, and p-dopes the PEA₂ SnI₄ film to form a better energy-level alignment with the electrodes and promote charge transport properties. As a result, the passivated devices exhibit better ambient and gate bias stability, improved photo-response, and higher mobility, for example, 2.96 cm² V^-1 s^-1 for the FPEAI-passivated films-four times higher than the control film (0.76 cm² V^-1 s^-1 ). In addition, these perovskite transistors display non-volatile photomemory characteristics and are used as perovskite-transistor-based memories. Although the reduction of surface defects in perovskite films results in reduced charge retention time due to lower trap density, these passivated devices with better photoresponse and air stability show promise for future photomemory applications.

An Integrated Analog Front-End System on Flexible Substrate for the Acquisition of Bio-Potential Signals

The application of a versatile, low-temperature thin-film transistor (TFT) technology is presently described as the implementation on a flexible substrate of an analog front-end (AFE) system for the acquisition of bio-potential signals. The technology is based on semiconducting amorphous indium-gallium-zinc oxide (IGZO). The AFE system consists of three monolithically integrated constituent components: a bias-filter circuit with a bio-compatible low cut-off frequency of ≈1 Hz, a 4-stage differential amplifier offering a large gain-bandwidth product of ≈955 kHz, and an additional notch filter exhibiting over 30 dB suppression of the power-line noise. Respectively built using conductive IGZO electrodes with thermally induced donor agents and enhancement-mode fluorinated IGZO TFTs with exceptionally low leakage current, both capacitors and resistors with significantly reduced footprints are realized. Defined as the ratio of the gain-bandwidth product of an AFE system to its area, a record-setting figure-of-merit of ≈86 kHz mm^-2 is achieved. This is about an order of magnitude larger than the < 10 kHz mm^-2 of the nearest benchmark. Requiring no supplementary off-substrate signal-conditioning components and occupying an area of ≈11 mm² , the stand-alone AFE system is successfully applied to both electromyography and electrocardiography (ECG).

Towards Digital Twin Implementation in Roll-To-Roll Gravure Printed Electronics: Overlay Printing Registration Error Prediction Based on Printing Process Parameters

Roll-to-roll gravure (R2Rg) has become highly affiliated with printed electronics in the past few years due to its high yield of printed thin-film transistor (TFT) in active matrix devices, and to its low cost. For printing TFTs with multilayer structures, achieving a high-precision in overlay printing registration accuracy (OPRA) is a key challenge to attain the high degree of TFT integration through R2Rg. To address this challenge efficiently, a digital twin paradigm was first introduced in the R2Rg system with an aim to optimize the OPRA by developing a predictive model based on typical input variables such as web tension, nip force, and printing speed in the R2Rg system. In our introductory-level digital twin, errors in the OPRA were collected with the variable parameters of web tensions, nip forces, and printing speeds from several R2Rg printing processes. Subsequently, statistical features were extracted from the input data followed by the training of a deep learning long-short term memory (LSTM) model for predicting machine directional error (MD) in the OPRA. As a result of training the LSTM model in our digital twin, its attained accuracy of prediction was 77%. Based on this result, we studied the relationship between the nip forces and printing speeds to predict the MD error in the OPRA. The results indicated a correlation between the MD error in the OPRA and the printing speed, as the MD error amplitude in the OPRA tended to decline at the higher printing speed.

Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter

In this work, the authors demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p-channel polycrystalline silicon (poly-Si) and n-channel amorphous indium tungsten oxide (a-IWO), with a low footprint than planar structure. The a-IWO TFT with channel thickness of approximately 3-4 atomic layers exhibits high mobility of 24 cm² V^-1 s^-1 , near ideally subthreshold swing of 63 mV dec^-1 , low leakage current below 10^-13 A, high on/off current ratio of larger than 10⁹ , extremely small hysteresis of 0 mV, low contact resistance of 0.44 kΩ-µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n-channel a-IWO TFT are well-matched with p-channel poly-Si TFT for superior complementary metal-oxide-semiconductor technology applications. The inverter can exhibit a high voltage gain of 152 V V^-1 at low supply voltage of 1.5 V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico-watt static power consumption inverter is achieved by the wide energy bandgap of a-IWO channel and atomically-thin channel. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.

High-Performance Solution-Processed 2D P-Type WSe2 Transistors and Circuits through Molecular Doping

Semiconducting ink based on 2D single-crystal flakes with dangling-bond-free surfaces enables the implementation of high-performance devices on form-free substrates by cost-effective and scalable printing processes. However, the lack of solution-processed p-type 2D semiconducting inks with high mobility is an obstacle to the development of complementary integrated circuits. Here, a versatile strategy of doping with Br₂ is reported to enhance the hole mobility by orders of magnitude for p-type transistors with 2D layered materials. Br₂ -doped WSe₂ transistors show a field-effect hole mobility of more than 27 cm²  V^-1  s^-1 , and a high on/off current ratio of ≈10⁷ , and exhibits excellent operational stability during the on-off switching, cycling, and bias stressing testing. Moreover, complementary inverters composed of patterned p-type WSe₂ and n-type MoS₂ layered films are demonstrated with an ultra-high gain of 1280 under a driving voltage (V_DD ) of 7 V. This work unveils the high potential of solution-processed 2D semiconductors with low-temperature processability for flexible devices and monolithic circuitry.

Interfacial Ultraviolet Cross-Linking of Green Bilayer Dielectrics

Electronic waste is a growing challenge which needs to be addressed through the integration of high-performance sustainable materials. Green dielectric polymers such as poly(vinyl alcohol) (PVA) have favorable electrical properties but are challenging to integrate into thin film electronics due to their physical properties. For example, PVA suffers from poor film formation and is hygroscopic. Bilayer dielectrics with interfacial cross-linking can enable the use of high-performance PVA with favorable surface chemistry by using a hydrophobic poly(caprolactone) (PCL) layer. In this study, we developed a benzodioxinone-terminated PCL layer, which can be UV cross-linked to the hydroxy groups of the PVA dielectric. This air-stable UV-cross-linking PCL dielectric was able to effectively cross-link with PVA, leading to high-performance capacitors and single-walled carbon nanotube-based thin film transistors. This UV cross-linking PCL dielectric led to significant improvements in shelf-life, ease of processing, and similar device performance compared to our previously reported thermally cross-linking PCL layer. The UV cross-linking at the interface between these bilayers can allow for the integration of high-speed roll-to-roll processing, which enables low-cost, sustainable, and high-performance electronics.

A Delay-Cell-Controlled VCO Design for Unipolar Single-Gate Enhancement-Mode TFT Technologies

This work outperforms the previous literatures by proposing a delay-cell-controlled voltage control oscillator (VCO) design for common unipolar, single-gate, and enhancement-mode thin-film transistor (TFT) technologies. A design example with InZnO TFTs is simulated to verify the proposed design. The design example has a 500 μW power consumption, 0.7 mm² area, 3.8 kHz-8 kHz output frequency range, 600 Hz/V tuning sensitivity, and 4% maximum linear error. This design may have the potential to be used for flexible, low cost, and moderate speed sensor readout interfaces.

Progress in the Development of Active-Matrix Quantum-Dot Light-Emitting Diodes Driven by Non-Si Thin-Film Transistors

This paper aims to discuss the key accomplishments and further prospects of active-matrix (AM) quantum-dot (QD) light-emitting diodes (QLEDs) display. We present an overview and state-of-the-art of QLEDs as a frontplane and non-Si-based thin-film transistors (TFTs) as a backplane to meet the requirements for the next-generation displays, such as flexibility, transparency, low power consumption, fast response, high efficiency, and operational reliability. After a brief introduction, we first review the research on non-Si-based TFTs using metal oxides, transition metal dichalcogenides, and semiconducting carbon nanotubes as the driving unit of display devices. Next, QLED technologies are analyzed in terms of the device structure, device engineering, and QD patterning technique to realize high-performance, full-color AM-QLEDs. Lastly, recent research on the monolithic integration of TFT-QLED is examined, which proposes a new perspective on the integrated device. We anticipate that this review will help the readership understand the fundamentals, current state, and issues on TFTs and QLEDs for future AM-QLED displays.

Effect of oxygen partial pressure on the performance of homojunction amorphous In-Ga-Zn-O thin-film transistors

In this study, the homojunction thin-film transistors (TFTs) with amorphous indium gallium zinc oxide (a-IGZO) as active channel layers and source/drain electrodes were fabricated by RF magnetron sputtering. The effect of oxygen partial pressure on the phase, microstructure, optical and electrical properties of IGZO thin films was investigated. The results showed that amorphous IGZO thin films always exhibit a high transmittance above 90% and wide band gaps of around 3.9 eV. The resistivity increases as the IGZO thin films are deposited at a higher oxygen partial pressure due to the depletion of oxygen vacancies. In addition, the electrical behaviors in homojunction IGZO TFTs were analyzed. When the active channel layers were deposited with an oxygen partial pressure of 1.96%, the homojunction IGZO TFTs exhibited optimal transfer and output characteristics with a field-effect mobility of 13.68 cm²V^-1s^-1. Its sub-threshold swing, threshold voltage and on/off ratio are 0.6 V/decade, 0.61 V and 10⁷, respectively.

High Operation Frequency and Strain Tolerance of Fully Printed Oxide Thin Film Transistors and Circuits on PET Substrates

The major limitations of solution-processed oxide electronics include high process temperatures and the absence of necessary strain tolerance that would be essential for flexible electronic applications. Here, a combination of low temperature (<100 °C) curable indium oxide nanoparticle ink and a conductive silver nanoink, which are used to fabricate fully-printed narrow-channel thin film transistors (TFTs) on polyethylene terephthalate (PET) substrates, is proposed. The metal ink is printed onto the In₂ O₃ nanoparticulate channel to narrow the effective channel lengths down to the thickness of the In₂ O₃ layer and thereby obtain near-vertical transport across the semiconductor layer. The TFTs thus prepared show On/Off ratio ≈10⁶ and simultaneous maximum current density of 172 µA µm^-1 . Next, the depletion-load inverters fabricated on PET substrates demonstrate signal gain >200 and operation frequency >300 kHz at low operation voltage of V_DD = 2 V. In addition, the near-vertical transport across the semiconductor layer is found to be largely strain tolerant with insignificant change in the TFT and inverter performance observed under bending fatigue tests performed down to a bending radius of 1.5 mm, which translates to a strain value of 5%. The devices are also found to be robust against atmospheric exposure when remeasured after a month.

Layer-by-layer epitaxy of multi-layer MoS2 wafers

The 2D semiconductor of MoS₂ has great potential for advanced electronics technologies beyond silicon. So far, high-quality monolayer MoS₂ wafers have been available and various demonstrations from individual transistors to integrated circuits have also been shown. In addition to the monolayer, multilayers have narrower band gaps but improved carrier mobilities and current capacities over the monolayer. However, achieving high-quality multi-layer MoS₂ wafers remains a challenge. Here we report the growth of high-quality multi-layer MoS₂ 4-inch wafers via the layer-by-layer epitaxy process. The epitaxy leads to well-defined stacking orders between adjacent epitaxial layers and offers a delicate control of layer numbers up to six. Systematic evaluations on the atomic structures and electronic properties were carried out for achieved wafers with different layer numbers. Significant improvements in device performances were found in thicker-layer field-effect transistors (FETs), as expected. For example, the average field-effect mobility (μ_FE) at room temperature (RT) can increase from ∼80 cm²·V^–1·s^–1 for monolayers to ∼110/145 cm²·V^–1·s^–1 for bilayer/trilayer devices. The highest RT μ_FE of 234.7 cm²·V^–1·s^–1 and record-high on-current densities of 1.70 mA·μm^–1 at V_ds = 2 V were also achieved in trilayer MoS₂ FETs with a high on/off ratio of >10⁷. Our work hence moves a step closer to practical applications of 2D MoS₂ in electronics.

High-Performance P-Channel Tin Halide Perovskite Thin Film Transistor Utilizing a 2D-3D Core-Shell Structure

Metal halide perovskites (MHPs) are plausible candidates for practical p-type semiconductors. However, in thin film transistor (TFT) applications, both 2D PEA₂ SnI₄ and 3D FASnI₃ MHPs have different drawbacks. In 2D MHP, the TFT mobility is seriously reduced by grain-boundary issues, whereas 3D MHP has an uncontrollably high hole density, which results in quite a large threshold voltage (V_th ). To overcome these problems, a new concept based on a 2D-3D core-shell structure is herein proposed. In the proposed structure, a 3D MHP core is fully isolated by a 2D MHP, providing two desirable effects as follows. (i) V_th can be independently controlled by the 2D component, and (ii) the grain-boundary resistance is significantly improved by the 2D/3D interface. Moreover, SnF₂ additives are used, and they facilitate the formation of the 2D/3D core-shell structure. Consequently, a high-performance p-type Sn-based MHP TFT with a field-effect mobility of ≈25 cm² V^-1 s^-1 is obtained. The voltage gain of a complementary metal oxide semiconductor (CMOS) inverter comprising an n-channel InGaZnO_x TFT and a p-channel Sn-MHP TFT is ≈200 V/V at V_DD = 20 V. Overall, the proposed 2D/3D core-shell structure is expected to provide a new route for obtaining high-performance MHP TFTs.

Investigation on Transparent, Conductive ZnO:Al Films Deposited by Atomic Layer Deposition Process

Transparent electrodes are a core component for transparent electron devices, photoelectric devices, and advanced displays. In this work, we fabricate fully-transparent, highly-conductive Al-doped ZnO (AZO) films using an atomic layer deposition (ALD) system method of repeatedly stacking ZnO and Al₂O₃ layers. The influences of Al cycle ratio (0, 2, 3, and 4%) on optical property, conductivity, crystallinity, surface morphology, and material components of the AZO films are examined, and current conduction mechanisms of the AZO films are analyzed. We found that Al doping increases electron concentration and optical bandgap width, allowing the AZO films to excellently combine low resistivity with high transmittance. Besides, Al doping induces preferred-growth-orientation transition from (002) to (100), which improves surface property and enhances current conduction across the AZO films. Interestingly, the AZO films with an Al cycle ratio of 3% show preferable film properties. Transparent ZnO thin film transistors (TFTs) with AZO electrodes are fabricated, and the ZnO TFTs exhibit superior transparency and high performance. This work accelerates the practical application of the ALD process in fabricating transparent electrodes.

Transparent Flexible IGZO Thin Film Transistors Fabricated at Room Temperature

Flexible and fully transparent thin film transistors (TFT) were fabricated via room temperature processes. The fabricated TFT on the PEN exhibited excellent performance, including a saturation mobility (μ_sat) of 7.9 cm²/V·s, an I_on/I_off ratio of 4.58 × 10⁶, a subthreshold swing (SS) of 0.248 V/dec, a transparency of 87.8% at 550 nm, as well as relatively good stability under negative bias stress (NBS) and bending stress, which shows great potential in smart, portable flexible display, and wearable device applications.

An Analytical Model for Dual Gate Piezoelectrically Sensitive ZnO Thin Film Transistors

We report the experimental realization of piezoelectric ZnO dual-gate thin film transistors (TFTs) as highly sensitive force sensors and discuss the physical origins of its electrically tunable piezoelectric response using a simple analytical model. A dual gate TFT is fabricated on a polyimide substrate using radio-frequency (RF) magnetron sputtering of piezoelectric ZnO thin film as a channel. The ZnO TFTs exhibited a field effect mobility of ~ 5 cm2/Vs, I max to I min ratio of 107, and a subthreshold slope of 700 mV/dec. Notably, the TFT exhibited static and transient current changes under external force stimuli, with varying amplitude and polarity for different gate bias regimes. To understand the current modulation of the dual-gate TFT with independently biased top and bottom gates, an analytical model is developed. The model includes accumulation channels at both surfaces and a bulk channel within the film and accounts for the force-induced piezoelectric charge density. The microscopic piezoelectric response that modulates the energy-band edges and correspondent current-voltage characteristics are accurately portrayed by our model. Finally, the field-tunable force response in single TFT is demonstrated as a function of independent bias for the top and bottom gates with a force response range from -0.29 nA/mN to 22.7 nA/mN. This work utilizes intuitive analytical models to shed light on the correlation between the material properties with the force response in piezoelectric TFTs.

Dimensional structure regulation of organic-inorganic hybrid perovskite and its application in thin film transistors

The effects of dimensional structure on the properties of lead iodide perovskite (C₈H₉NH₃)₂(CH₃NH₃)_n-1Pb_nI_3n+1were investigated. Furthermore, perovskite thin films with different dimensionalities were applied as the channel layer of thin film transistors (TFT). The electrical performance and stability of TFT devices were significantly improved through the regulation of dimensional microstructure of the perovskites. As a result, the quasi-2D (n = 6) perovskite TFTs achieved a field-effect mobility (μ_FE) of 3.90 cm²V^-1s^-1, with 10⁴on-off current ratio and -1.85 V threshold voltage, which can be maintained well after 4 days without degradation at 30% ambient humidity. Moreover, the electrical performance of the TFTs based on Pure-2D and Quasi-2D perovskite also exhibited a good bias stability.

A Study about Schottky Barrier Height and Ideality Factor in Thin Film Transistors with Metal/Zinc Oxide Nanoparticles Structures Aiming Flexible Electronics Application

Zinc oxide nanoparticles (ZnO NP) used for the channel region in inverted coplanar setup in Thin Film Transistors (TFT) were the focus of this study. The regions between the source electrode and the ZnO NP and the drain electrode were under investigation as they produce a Schottky barrier in metal-semiconductor interfaces. A more general Thermionic emission theory must be evaluated: one that considers both metal/semiconductor interfaces (MSM structures). Aluminum, gold, and nickel were used as metallization layers for source and drain electrodes. An organic-inorganic nanocomposite was used as a gate dielectric. The TFTs transfer and output characteristics curves were extracted, and a numerical computational program was used for fitting the data; hence information about Schottky Barrier Height (SBH) and ideality factors for each TFT could be estimated. The nickel metallization appears with the lowest SBH among the metals investigated. For this metal and for higher drain-to-source voltages, the SBH tended to converge to some value around 0.3 eV. The developed fitting method showed good fitting accuracy even when the metallization produced different SBH in each metal-semiconductor interface, as was the case for gold metallization. The Schottky effect is also present and was studied when the drain-to-source voltages and/or the gate voltage were increased.

Amorphous NdIZO Thin Film Transistors with Contact-Resistance-Adjustable Cu S/D Electrodes

High-performance amorphous oxide semiconductor thin film transistors (AOS-TFT) with copper (Cu) electrodes are of great significance for next-generation large-size, high-refresh rate and high-resolution panel display technology. In this work, using rare earth dopant, neodymium-doped indium-zinc-oxide (NdIZO) film was optimized as the active layer of TFT with Cu source and drain (S/D) electrodes. Under the guidance of the Taguchi orthogonal design method from Minitab software, the semiconductor characteristics were evaluated by microwave photoconductivity decay (μ-PCD) measurement. The results show that moderate oxygen concentration (~5%), low sputtering pressure (≤5 mTorr) and annealing temperature (≤300 °C) are conducive to reducing the shallow localized states of NdIZO film. The optimized annealing temperature of this device configuration is as low as 250 °C, and the contact resistance (R_C) is modulated by gate voltage (V_G) instead of a constant value when annealed at 300 °C. It is believed that the adjustable R_C with V_G is the key to keeping both high mobility and compensation of the threshold voltage (V_th). The optimal device performance was obtained at 250 °C with an I_on/I_off ratio of 2.89 × 10⁷, a saturation mobility (μ_sat) of 24.48 cm²/(V·s) and V_th of 2.32 V.

Role of ALD Al2O3 Surface Passivation on the Performance of p-Type Cu2O Thin Film Transistors

High-performance p-type oxide thin film transistors (TFTs) have great potential for many semiconductor applications. However, these devices typically suffer from low hole mobility and high off-state currents. We fabricated p-type TFTs with a phase-pure polycrystalline Cu₂O semiconductor channel grown by atomic layer deposition (ALD). The TFT switching characteristics were improved by applying a thin ALD Al₂O₃ passivation layer on the Cu₂O channel, followed by vacuum annealing at 300 °C. Detailed characterization by transmission electron microscopy-energy dispersive X-ray analysis and X-ray photoelectron spectroscopy shows that the surface of Cu₂O is reduced following Al₂O₃ deposition and indicates the formation of a 1-2 nm thick CuAlO₂ interfacial layer. This, together with field-effect passivation caused by the high negative fixed charge of the ALD Al₂O₃, leads to an improvement in the TFT performance by reducing the density of deep trap states as well as by reducing the accumulation of electrons in the semiconducting layer in the device off-state.

Flexible Quasi-van der Waals Ferroelectric Hafnium-Based Oxide for Integrated High-Performance Nonvolatile Memory

Ferroelectric memories with ultralow-power-consumption are attracting a great deal of interest with the ever-increasing demand for information storage in wearable electronics. However, sufficient scalability, semiconducting compatibility, and robust flexibility of the ferroelectric memories remain great challenges, e.g., owing to Pb-containing materials, oxide electrode, and limited thermal stability. Here, high-performance flexible nonvolatile memories based on ferroelectric Hf0.5Zr0.5O2 (HZO) via quasi-van der Waals heteroepitaxy are reported. The flexible ferroelectric HZO exhibits not only high remanent polarization up to 32.6 µC cm-2 without a wake-up effect during cycling, but also remarkably robust mechanical properties, degradation-free retention, and endurance performance under a series of bent deformations and cycling tests. Intriguingly, using HZO as a gate, flexible ferroelectric thin-film transistors with a low operating voltage of ±3 V, high on/off ratio of 6.5  ×  105, and a small subthreshold slope of about 100 mV dec-1, which outperform reported flexible ferroelectric transistors, are demonstrated. The results make ferroelectric HZO a promising candidate for the next-generation of wearable, low-power, and nonvolatile memories with manufacturability and scalability.

TFT Channel Materials for Display Applications: From Amorphous Silicon to Transition Metal Dichalcogenides

As the need for super-high-resolution displays with various form factors has increased, it has become necessary to produce high-performance thin-film transistors (TFTs) that enable faster switching and higher current driving of each pixel in the display. Over the past few decades, hydrogenated amorphous silicon (a-Si:H) has been widely utilized as a TFT channel material. More recently, to meet the requirement of new types of displays such as organic light-emitting diode displays, and also to overcome the performance and reliability issues of a-Si:H, low-temperature polycrystalline silicon and amorphous oxide semiconductors have partly replaced a-Si:H channel materials. Basic material properties and device structures of TFTs in commercial displays are explored, and then the potential of atomically thin layered transition metal dichalcogenides as next-generation channel materials is discussed.

Fabrication of Carbon Nanotube Thin Films for Flexible Transistors by Using a Cross-Linked Amine Polymer

Owing to their remarkable properties, single-walled carbon nanotube thin-film transistors (SWCNT-TFTs) are expected to be used in various flexible electronics applications. To fabricate SWCNT channel layers for TFTs, solution-based film formation on a self-assembled monolayer (SAM) covered with amino groups is commonly used. However, this method uses highly oxidized surfaces, which is not suitable for flexible polymeric substrates. In this work, a solution-based SWCNT film fabrication using methoxycarbonyl polyallylamine (Moc-PAA) is reported. The NH₂ -terminated surface of the cross-linked Moc-PAA layer enables the formation of highly dense and uniform SWCNT networks on both rigid and flexible substrates. TFTs that use the fabricated SWCNT thin film exhibited excellent performance with small variations. The presented simple method to access SWCNT thin film accelerates the realization of flexible nanoelectronics.

Wafer-Scale, Conformal, and Low-Temperature Synthesis of Layered Tin Disulfides for Emerging Nonplanar and Flexible Electronics

Two-dimensional (2D) metal dichalcogenides have drawn considerable interest because they offer possibilities for the implementation of emerging electronics. The emerging electronics are moving toward two major directions: vertical expansion of device space and flexibility. However, the development of a synthesis method for 2D metal dichalcogenides that meets all the requirements remains a significant challenge. Here, we propose a promising method for wafer-scale, conformal, and low-temperature (≤240 °C) synthesis of single-phase SnS₂ via the atomic layer deposition technique. There is a trade-off relationship between the crystallinity and orientation preference of SnS₂, which is efficiently eliminated by the two-step growth occurring at different temperatures. Consequently, the van der Waals layers of the highly crystalline SnS₂ are parallel to the substrate. Thin-film transistors (TFTs) comprising the SnS₂ layer show reasonable electrical performances (field-effect mobility: ∼0.8 cm² V^-1 s^-1 and on/off ratio: ∼10⁶), which are comparable to that of a single-crystal SnS₂ flake. Moreover, we demonstrate nonplanar and flexible TFTs to identify the feasibility of the implementation of future electronics. Both the diagonal-structured TFT and flexible TFT fabricated without a transfer process show electrical performances comparable to those of rigid and planar TFTs. Particularly, the flexible TFT does not exhibit substantial degradation even after 2000 bending cycles. Our work would provide decisive opportunities for the implementation of future electronic devices utilizing 2D metal chalcogenides.

Temperature Dependence Of AOS Thin Film Nano Transistors For Medical Applications

Background

A novel temperature dependent amorphous nano oxide semiconductor (AOS) thin-film transistor (TFT) is reported here for the first time, which is vastly different from conventional behavior. In the literature, the threshold voltage of TFTs decreases with increasing temperature. Here, the threshold voltage increased at higher temperatures, which is different from previously reported results and was repeated on different samples.

Methods

Electrical experiments (such as I-V measurements and photoelectron spectrometer experiments) were performed in order to explain such behavior. Double sweeping gate voltage measurements were performed to investigate the mechanism for the temperature dependent behavior.

Results

It was found that there was a change of trap charge under thermal stress, which was released after the stress.

Conclusion

Non-Arrhenius behaviors (including a linear behavior) were obtained for the amorphous nano oxide thin-film transistors within 303~425 K, suggesting their potential to be adjusted by measurement processes and be applied as temperature sensors for numerous medical applications.

Transparent ZnO Thin-Film Deposition by Spray Pyrolysis for High-Performance Metal-Oxide Field-Effect Transistors

Solution-based metal oxide semiconductors (MOSs) have emerged, with their potential for low-cost and low-temperature processability preserving their intrinsic properties of high optical transparency and high carrier mobility. In particular, MOS field-effect transistors (FETs) using the spray pyrolysis technique have drawn huge attention with the electrical performances compatible with those of vacuum-based FETs. However, further intensive investigations are still desirable, associated with the processing optimization and operational instabilities when compared to other methodologies for depositing thin-film semiconductors. Here, we demonstrate high-performing transparent ZnO FETs using the spray pyrolysis technique, exhibiting a field-effect mobility of ~14.7 cm² V⁻¹ s⁻¹, an on/off ratio of ~10⁹, and an SS of ~0.49 V/decade. We examine the optical and electrical characteristics of the prepared ZnO films formed by spray pyrolysis via various analysis techniques. The influence of spray process conditions was also studied for realizing high quality ZnO films. Furthermore, we measure and analyze time dependence of the threshold voltage (V_th) shifts and their recovery behaviors under prolonged positive and negative gate bias, which were expected to be attributed to defect creation and charge trapping at or near the interface between channel and insulator, respectively.

Integration of Electrochemical Microsupercapacitors with Thin Film Electronics for On-Chip Energy Storage

The development of self-powered electronic systems requires integration of on-chip energy-storage units to interface with various types of energy harvesters, which are intermittent by nature. Most studies have involved on-chip electrochemical microsupercapacitors that have been interfaced with energy harvesters through bulky Si-based rectifiers that are difficult to integrate. This study demonstrates transistor-level integration of electrochemical microsupercapacitors and thin film transistor rectifiers. In this approach, the thin film transistors, thin film rectifiers, and electrochemical microsupercapacitors share the same electrode material for all, which allows for a highly integrated electrochemical on-chip storage solution. The thin film rectifiers are shown to be capable of rectifying AC signal input from either triboelectric nanogenerators or standard function generators. In addition, electrochemical microsupercapacitors exhibit exceptionally slow self-discharge rate (≈18.75 mV h^-1 ) and sufficient power to drive various electronic devices. This study opens a new avenue for developing compact on-chip electrochemical micropower units integrated with thin film electronics.

Perovskite and Conjugated Polymer Wrapped Semiconducting Carbon Nanotube Hybrid Films for High-Performance Transistors and Phototransistors

Although organic-inorganic halide perovskites continue to generate considerable interest due to great potentials for various optoelectronic devices, there are some critical obstacles to practical applications, including lead toxicity, relatively low field-effect mobility, and strong hysteresis during operation. This paper proposes a universal approach to significantly improve mobility and operational stability with reduced dual-sweep hysteresis for perovskite-based thin film transistors (TFTs) by coupling low-dimensional lead-free perovskite material (C₆H₅C₂H₄NH₃)₂SnI₄ (hereafter abbreviated as (PEA)₂SnI₄) with embedded conjugated polymer wrapped semiconducting carbon nanotubes (semi-CNTs). In (PEA)₂SnI₄/semi-CNT hybrid TFTs, semi-CNTs can provide highway-like transport paths, enabling smoother carrier transport with less trapping and scattering. We also demonstrate the performance of (PEA)₂SnI₄/semi-CNT hybrid phototransistors with ultrahigh photoresponsivity ( R) of 6.3 × 10⁴ A/W and detectivity ( D*) of 1.12 × 10¹⁷ Jones, which is about 2 or 3 orders of magnitude higher than that of the best devices available to date. The results indicate promising potentials for solution-processed perovskite/semi-CNT hybrid platforms, and the developed strategy can be applied for high-performance perovskite nanomaterial optoelectronics.

Thermopower Modulation Clarification of the Operating Mechanism in Wide Bandgap BaSnO3 -SrSnO3 Solid-Solution Based Thin Film Transistors

The transparent oxide semiconductor (TOS) with large bandgap (E_g ≈ 4 eV) based thin-film transistors (TFTs) showing both high carrier mobility and UV-visible transparency has attracted increasing attention as a promising component for next generation optoelectronics. Among TOSs, BaSnO₃ -SrSnO₃ solid-solutions (E_g = 3.5-4.2 eV) are good candidates because the single crystal shows very high mobility. However, the TFT performance has not been optimized due to the lack of fundamental knowledge especially the effective thickness (t_eff ) and the carrier effective mass (m*). Here, it is demonstrated that the electric field thermopower (S) modulation method addresses this problem by combining with the standard volume carrier concentration (n_3D ) dependence of S measurements. By comparing the electric field accumulated sheet carrier concentration (n_2D ) and n_3D at same S, it is clarified that the t_eff (n_2D /n_3D ) of the conducting channel becomes thicker with increasing Sr concentration, whereas the m* becomes lighter. The former would be due to the increase of E_g and latter would be due to the enhancement of overlap population of neighboring Sn 5s orbitals. The present analyses technique is useful to experimentally clarify the t_eff and m*, and essentially important to realize advanced TOS-based TFTs showing both high optical transparency and high mobility.

Aqueous Solution Processing of Combustible Precursor Compounds into Amorphous Indium Gallium Zinc Oxide (IGZO) Semiconductors for Thin Film Transistor Applications

Combustion synthesis of semiconducting amorphous indium gallium zinc oxide IGZO (In:Ga:Zn, 7:1:1.5) thin films was carried out using urea nitrate precursor compounds of indium(III), gallium(III) and zinc(II). This approach provides further understanding towards the oxide formation process under a moderate temperature regime by employment of well-defined coordination compounds. All precursor compounds were fully characterized by spectroscopic techniques as well as by single crystal structure analysis. Their intrinsic thermal decomposition was studied by a combination of differential scanning calorimetry (DSC) and thermogravimetry coupled with mass spectrometry and infrared spectroscopy (TG-MS/IR). For all precursors a multistep decomposition involving a complex redox-reaction pathway under in situ formation of nitrogen containing molecular species was observed. Controlled thermal conversion of a mixture of the indium, gallium and zinc urea nitrate complexes into ternary amorphous IGZO films could thus be achieved. Thin film transistors (TFTs) were fabricated from a defined compositional mixture of the molecular precursors. The TFT devices exhibited decent charge carrier mobilities of 0.4 and 3.1 cm² /(Vs) after annealing of the deposited films at temperatures as low as 250 and 350 °C, respectively. This approach represents a significant step further towards a low temperature solution processing of semiconducting thin films.

Transparent Electronics Using One Binary Oxide for All Transistor Layers

A novel process is developed in which thin film transistors (TFTs) comprising one binary oxide for all transistor layers (gate, source/drain, semiconductor channel, and dielectric) are fabricated in a single deposition system at low temperature. By simply changing the flow ratio of two chemical precursors, C₈ H₂₄ HfN₄ and (C₂ H₅ )₂ Zn, in an atomic layer deposition system, the electronic properties of the binary oxide (Hf _x Zn_{1- x} O_{2- δ} or HZO) are tuned from conducting, to semiconducting, to insulating. Furthermore, by carefully optimizing the properties of the various transistor HZO layers, all-HZO thin film transistors are achieved with excellent performance on both glass and plastic substrates. Specifically, the optimized all-HZO TFTs show a saturation mobility of ≈17.9 cm² V^-1 s^-1 , low subthreshold swing of ≈480 mV dec^-1 , high I_on /I_off ratio of >10⁹ , and excellent gate bias stability at elevated temperatures. In addition, all-HZO inverters with high DC voltage gain (≈470), and all-HZO ring oscillators with low stage delay (≈408 ns) and high oscillation frequency of 245 kHz are demonstrated. This approach presents a novel, simple, high performance, and cost-effective process for the fabrication of indium-free transparent electronics.

Room-Temperature Fabricated Thin-Film Transistors Based on Compounds with Lanthanum and Main Family Element Boron

For the first time, compounds with lanthanum from the main family element Boron (LaB_x) were investigated as an active layer for thin-film transistors (TFTs). Detailed studies showed that the room-temperature fabricated LaB_x thin film was in the crystalline state with a relatively narrow optical band gap of 2.28 eV. The atom ration of La/B was related to the working pressure during the sputtering process and the atom ration of La/B increased with the increase of the working pressure, which will result in the freer electrons in the LaB_x thin film. LaB_x-TFT without any intentionally annealing steps exhibited a saturation mobility of 0.44 cm²·V⁻¹·s⁻¹, which is a subthreshold swing (SS) of 0.26 V/decade and a I_on/I_off ratio larger than 10⁴. The room-temperature process is attractive for its compatibility with almost all kinds of flexible substrates and the LaB_x semiconductor may be a new choice for the channel materials in TFTs.

Effect of Source/Drain Electrodes on the Electrical Properties of Silicon⁻Tin Oxide Thin-Film Transistors

Ultra-high definition displays have become a trend for the current flat plane displays. In this study, the contact properties of amorphous silicon⁻tin oxide thin-film transistors (a-STO TFTs) employed with source/drain (S/D) electrodes were analyzed. Ohmic contact with a good device performance was achieved when a-STO was matched with indium-tin-oxide (ITO) or Mo electrodes. The acceptor-like densities of trap states (DOS) of a-STO TFTs were further investigated by using low-frequency capacitance⁻voltage (C⁻V) characteristics to understand the impact of the electrode on the device performance. The reason of the distinct electrical performances of the devices with ITO and Mo contacts was attributed to different DOS caused by the generation of local defect states near the electrodes, which distorted the electric field distribution and formed an electrical potential barrier hindering the flow of electrons. It is of significant importance for circuit designers to design reliable integrated circuits with SnO₂-based devices applied in flat panel displays.

Mobility Enhancement in Amorphous In-Ga-Zn-O Thin-Film Transistor by Induced Metallic in Nanoparticles and Cu Electrodes

In this work, we fabricated a high-mobility amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) based on alumina oxide (Al2O3) passivation layer (PVL) and copper (Cu) source/drain electrodes (S/D). The mechanism of the high mobility for a-IGZO TFT was proposed and experimentally demonstrated. The conductivity of the channel layer was significantly improved due to the formation of metallic In nanoparticles on the back channel during Al2O3 PVL sputtering. In addition, Ar atmosphere annealing induced the Schottky contact formation between the Cu S/D and the channel layer caused by Cu diffusion. In conjunction with high conductivity channel and Schottky contact, the a-IGZO TFT based on Cu S/D and Al2O3 PVL exhibited remarkable mobility of 33.5–220.1 cm2/Vs when channel length varies from 60 to 560 μm. This work presents a feasible way to implement high mobility and Cu electrodes in a-IGZO TFT, simultaneously.

Flexible Zinc-Tin Oxide Thin Film Transistors Operating at 1 kV for Integrated Switching of Dielectric Elastomer Actuators Arrays

Flexible high-voltage thin-film transistors (HVTFTs) operating at more than 1 kV are integrated with compliant dielectric elastomer actuators (DEA) to create a flexible array of 16 independent actuators. To allow for high-voltage operation, the HVTFT implements a zinc-tin oxide channel, a thick dielectric stack, and an offset gate. At a source-drain bias of 1 kV, the HVTFT has a 20 µA on-current at a gate voltage bias of 30 V. Their electrical characteristics enable the switching of DEAs which require drive voltages of over 1 kV, making control of an array simpler in comparison to the use of external high-voltage switching. These HVTFTs are integrated in a flexible haptic display consisting of a 4 × 4 matrix of DEAs and HVTFTs. Using a single 1.4 kV supply, each DEA is independently switched by its associated HVTFT, requiring only a 30 V gate voltage for full DEA deflection. The 4 × 4 display operates well even when bent to a 5 mm radius of curvature. By enabling DEA switching at low voltages, flexible metal-oxide HVTFTs enable complex flexible systems with dozens to hundreds of independent DEAs for applications in haptics, Braille displays, and soft robotics.

Modulation-Doped In2 O3 /ZnO Heterojunction Transistors Processed from Solution

This paper reports the controlled growth of atomically sharp In₂ O₃ /ZnO and In₂ O₃ /Li-doped ZnO (In₂ O₃ /Li-ZnO) heterojunctions via spin-coating at 200 °C and assesses their application in n-channel thin-film transistors (TFTs). It is shown that addition of Li in ZnO leads to n-type doping and allows for the accurate tuning of its Fermi energy. In the case of In₂ O₃ /ZnO heterojunctions, presence of the n-doped ZnO layer results in an increased amount of electrons being transferred from its conduction band minimum to that of In₂ O₃ over the interface, in a process similar to modulation doping. Electrical characterization reveals the profound impact of the presence of the n-doped ZnO layer on the charge transport properties of the isotype In₂ O₃ /Li-ZnO heterojunctions as well as on the operating characteristics of the resulting TFTs. By judicious optimization of the In₂ O₃ /Li-ZnO interface microstructure, and Li concentration, significant enhancement in both the electron mobility and TFT bias stability is demonstrated.

A Mixed-Extractor Strategy for Efficient Sorting of Semiconducting Single-Walled Carbon Nanotubes

A general strategy for sorting semiconducting single-walled carbon nanotubes (s-SWNTs) with high efficiency using a mixed-extractor is reported. When the two extractors have a sufficient difference in binding energy with s-SWNTs, and skeleton flexibility, the mixture shows enhanced yield for sorting s-SWNTs. The strategy could be effective when applied to increase the sorting yield of other selective dispersion systems.

Structural and Electrical Characterization of SiO2 Gate Dielectrics Deposited from Solutions at Moderate Temperatures in Air

Silicon dioxide (SiO₂) is the most widely used dielectric for electronic applications. It is usually produced by thermal oxidation of silicon or by using a wide range of vacuum-based techniques. By default, the growth of SiO₂ by thermal oxidation of silicon requires the use of Si substrates whereas the other deposition techniques either produce low quality or poor interface material and mostly require high deposition or annealing temperatures. Recent investigations therefore have focused on the development of alternative deposition paradigms based on solutions. Here, we report the deposition of SiO₂ thin film dielectrics deposited by spray pyrolysis in air at moderate temperatures of ≈350 °C from pentane-2,4-dione solutions of SiCl₄. SiO₂ dielectrics were investigated by means of UV-vis absorption spectroscopy, spectroscopic ellipsometry, XPS, XRD, UFM/AFM, admittance spectroscopy, and field-effect measurements. Data analysis reveals smooth (R_RMS < 1 nm) amorphous films with a dielectric constant of about 3.8, an optical band gap of ≈8.1 eV, leakage current densities in the order of ≈10^-7 A/cm² at 1 MV/cm, and high dielectric strength in excess of 5 MV/cm. XPS measurements confirm the SiO₂ stoichiometry and FTIR spectra reveal features related to SiO₂ only. Thin film transistors implementing spray-coated SiO₂ gate dielectrics and C₆₀ and pentacene semiconducting channels exhibit excellent transport characteristics, i.e., negligible hysteresis, low leakage currents, high on/off current modulation ratio on the order of 10⁶, and high carrier mobility.

Direct Inkjet Printing of Silver Source/Drain Electrodes on an Amorphous InGaZnO Layer for Thin-Film Transistors

Printing technologies for thin-film transistors (TFTs) have recently attracted much interest owing to their eco-friendliness, direct patterning, low cost, and roll-to-roll manufacturing processes. Lower production costs could result if electrodes fabricated by vacuum processes could be replaced by inkjet printing. However, poor interfacial contacts and/or serious diffusion between the active layer and the silver electrodes are still problematic for achieving amorphous indium–gallium–zinc–oxide (a-IGZO) TFTs with good electrical performance. In this paper, silver (Ag) source/drain electrodes were directly inkjet-printed on an amorphous a-IGZO layer to fabricate TFTs that exhibited a mobility of 0.29 cm²·V⁻¹·s⁻¹ and an on/off current ratio of over 10⁵. To the best of our knowledge, this is a major improvement for bottom-gate top-contact a-IGZO TFTs with directly printed silver electrodes on a substrate with no pretreatment. This study presents a promising alternative method of fabricating electrodes of a-IGZO TFTs with desirable device performance.

Significantly Increasing the Ductility of High Performance Polymer Semiconductors through Polymer Blending

Polymer semiconductors based on donor-acceptor monomers have recently resulted in significant gains in field effect mobility in organic thin film transistors (OTFTs). These polymers incorporate fused aromatic rings and have been designed to have stiff planar backbones, resulting in strong intermolecular interactions, which subsequently result in stiff and brittle films. The complex synthesis typically required for these materials may also result in increased production costs. Thus, the development of methods to improve mechanical plasticity while lowering material consumption during fabrication will significantly improve opportunities for adoption in flexible and stretchable electronics. To achieve these goals, we consider blending a brittle donor-acceptor polymer, poly[4-(4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b']dithiophen-2-yl)-alt-[1,2,5]thiadiazolo[3,4-c]pyridine] (PCDTPT), with ductile poly(3-hexylthiophene). We found that the ductility of the blend films is significantly improved compared to that of neat PCDTPT films, and when the blend film is employed in an OTFT, the performance is largely maintained. The ability to maintain charge transport character is due to vertical segregation within the blend, while the improved ductility is due to intermixing of the polymers throughout the film thickness. Importantly, the application of large strains to the ductile films is shown to orient both polymers, which further increases charge carrier mobility. These results highlight a processing approach to achieve high performance polymer OTFTs that are electrically and mechanically optimized.

Rational Hydrogenation for Enhanced Mobility and High Reliability on ZnO-based Thin Film Transistors: From Simulation to Experiment

Hydrogenation is one of the effective methods for improving the performance of ZnO thin film transistors (TFTs), which originate from the fact that hydrogen (H) acts as a defect passivator and a shallow n-type dopant in ZnO materials. However, passivation accompanied by an excessive H doping of the channel region of a ZnO TFT is undesirable because high carrier density leads to negative threshold voltages. Herein, we report that Mg/H codoping could overcome the trade-off between performance and reliability in the ZnO TFTs. The theoretical calculation suggests that the incorporation of Mg in hydrogenated ZnO decrease the formation energy of interstitial H and increase formation energy of O-vacancy (VO). The experimental results demonstrate that the existence of the diluted Mg in hydrogenated ZnO TFTs could be sufficient to boost up mobility from 10 to 32.2 cm(2)/(V s) at a low carrier density (∼2.0 × 10(18) cm(-3)), which can be attributed to the decreased electron effective mass by surface band bending. The all results verified that the Mg/H codoping can significantly passivate the VO to improve device reliability and enhance mobility. Thus, this finding clearly points the way to realize high-performance metal oxide TFTs for low-cost, large-volume, flexible electronics.

Modulating Cationic Ratios for High-Performance Transparent Solution-Processed Electronics

Amorphous oxide semiconductors such as indium zinc tin oxide (IZTO) are considered favorites to serve as channel materials for thin film transistors (TFTs) because they combine high charge carrier mobility with high optical transmittance, allowing for the development of transparent electronics. Although the influence of relative cationic concentrations in determining the electronic properties have been studied in sputtered and PLD films, the development of printed transparent electronics hinges on such dependencies being explored for solution-processed systems. Here, we study solution-processed indium zinc tin oxide thin film transistors (TFTs) to investigate variation in their electrical properties with change in cationic composition. Charge transport mobility ranging from 0.3 to 20.3 cm(2)/(V s), subthreshold swing ranging from 1.2 to 8.4 V/dec, threshold voltage ranging from -50 to 5 V, and drain current on-off ratio ranging from 3 to 6 orders of magnitude were obtained by examining different compositions of the semiconductor films. Mobility was found to increase with the incorporation of large cations such as In(3+) and Sn(4+) due to the vast s-orbital overlap they can achieve when compared to the intercationic distance. Subthreshold swing decreased with an increase in Zn(2+) concentration due to reduced interfacial state formation between the semiconductor and dielectric. The optimized transistor obtained at a compositional ratio of In/Zn/Sn = 1:1:1, exhibited a high field-effect mobility of 8.62 cm(2)/(V s), subthreshold swing of 1.75 V/dec, and current on-off ratio of 10(6). Such impressive performances reaffirm the promise of amorphous metal oxide semiconductors for printed electronics.

Toward the Limits of Uniformity of Mixed Metallicity SWCNT TFT Arrays with Spark-Synthesized and Surface-Density-Controlled Nanotube Networks

We report the fabrication of thin film transistors (TFTs) from networks of nonbundled single-walled carbon nanotubes with controlled surface densities. Individual nanotubes were synthesized by using a spark generator-based floating catalyst CVD process. High uniformity and the control of SWCNT surface density were realized by mixing of the SWCNT aerosol in a turbulent flow mixer and monitoring the online number concentration with a condensation particle counter at the reactor outlet in real time. The networks consist of predominantly nonbundled SWCNTs with diameters of 1.0-1.3 nm, mean length of 3.97 μm, and metallic to semiconducting tube ratio of 1:2. The ON/OFF ratio and charge carrier mobility of SWCNT TFTs were simultaneously optimized through fabrication of devices with SWCNT surface densities ranging from 0.36 to 1.8 μm(-2) and channel lengths and widths from 5 to 100 μm and from 100 to 500 μm, respectively. The density optimized TFTs exhibited excellent performance figures with charge carrier mobilities up to 100 cm(2) V(-1) s(-1) and ON/OFF current ratios exceeding 1 × 10(6), combined with high uniformity and more than 99% of devices working as theoretically expected.

Performance Enhancement of ZITO Thin-Film Transistors via Graphene Bridge Layer by Sol-Gel Combustion Process

In this article, we reported the stacked structure zinc-indium-tin oxide (ZITO) thin-film transistors (TFTs) with graphene nanosheets (GNSs) prepared by solution process. GNSs were used as bridge layer between dual-ZITO layers. The transmission of stacked ZITO/GNSs/ZITO films are more than 80% in the visible region and the resistivity of ZITO films with GNSs bridge layer decreased from 502.9 to 13.4 Ω cm. The solution-processed TFT devices with GNSs bridge layer exhibited a desirable characteristic with a subthreshold slope of 0.25 V/dec and current on-off ratio of 1 × 10(7), and the saturation filed effect mobility is improved to 45.9 cm(2)V(-1)s(-1), which exceeds the mobility values of the pristine ZITO TFTs by one order. These results demonstrate the solution-processed ZITO/GNSs/ZITO TFTs maybe make a further step to achieve high-performance TFTs and show the potential for next-generation applications.

Stable and High-Performance Flexible ZnO Thin-Film Transistors by Atomic Layer Deposition

Passivation is a challenging issue for the oxide thin-film transistor (TFT) technologies because it requires prolonged high-temperature annealing treatments to remedy defects produced in the process, which greatly limits its manufacturability as well as its compatibility with temperature-sensitive materials such as flexible plastic substrates. This study investigates the defect-formation mechanisms incurred by atomic layer deposition (ALD) passivation processes on ZnO TFTs, based on which we demonstrate for the first time degradation-free passivation of ZnO TFTs by a TiO2/Al2O3 nanolaminated (TAO) film deposited by a low-temperature (110 °C) ALD process. By combining the TAO passivation film with ALD dielectric and channel layers into an integrated low-temperature ALD process, we successfully fabricate flexible ZnO TFTs on plastics. Thanks to the exceptional gas-barrier property of the TAO film (water vapor transmission rate (WVTR)<10(-6) g m(-2) day(-1)) as well as the defect-free nature of the ALD dielectric and ZnO channel layers, the TFTs exhibit excellent device performance with high stability and flexibility: field-effect mobility>20 cm2 V(-1) s(-1), subthreshold swing<0.4 V decade(-1) after extended bias-stressing (>10,000 s), air-storage (>1200 h), and bending (1.3 cm radius for 1000 times).

ZnO-based thin film transistors employing aluminum titanate gate dielectrics deposited by spray pyrolysis at ambient air

The replacement of SiO2 gate dielectrics with metal oxides of higher dielectric constant has led to the investigation of a wide range of materials with superior properties compared with SiO2. Despite their attractive properties, these high-k dielectrics are usually manufactured using costly vacuum-based techniques. To overcome this bottleneck, research has focused on the development of alternative deposition methods based on solution-processable metal oxides. Here we report the application of spray pyrolysis for the deposition and investigation of Al2x-1·TixOy dielectrics as a function of the [Ti(4+)]/[Ti(4+)+2·Al(3+)] ratio and their implementation in thin film transistors (TFTs) employing spray-coated ZnO as the active semiconducting channels. The films are studied by UV-visible absorption spectroscopy, spectroscopic ellipsometry, impedance spectroscopy, atomic force microscopy, X-ray diffraction and field-effect measurements. Analyses reveal amorphous Al2x-1·TixOy dielectrics that exhibit a wide band gap (∼4.5 eV), low roughness (∼0.9 nm), high dielectric constant (k ∼ 13), Schottky pinning factor S of ∼0.44 and very low leakage currents (<5 nA/cm(2)). TFTs employing stoichiometric Al2O3·TiO2 gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with low operating voltages (∼10 V), negligible hysteresis, high on/off current modulation ratio of ∼10(6), subthreshold swing (SS) of ∼550 mV/dec and electron mobility of ∼10 cm(2) V(-1) s(-1).

Spatial atmospheric atomic layer deposition of InxGayZnzO for thin film transistors

We have investigated the nucleation and growth of InGaZnO thin films by spatial atmospheric atomic layer deposition. Diethyl zinc (DEZ), trimethyl indium (TMIn), triethyl gallium (TEGa), and water were used as Zn, In, Ga and oxygen precursors, respectively. The vaporized metal precursors have been coinjected in the reactor. The metal composition of InGaZnO has been controlled by varying the TMIn or TEGa flow to the reactor, for a given DEZ flow and exposure time. The morphology of the films changes from polycrystalline, for ZnO and In-doped ZnO, to amorphous for In-rich IZO and InGaZnO. The use of these films as the active channel in TFTs has been demonstrated and the influence of In and Ga cations on the electrical characteristics of the TFTs has been studied.