Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

The Nonvolatile Memory and Neuromorphic Simulation of ReS2 /h-BN/Graphene Floating Gate Devices Under Photoelectrical Hybrid Modulations

The floating gate devices, as a kind of nonvolatile memory, obtain great application potential in logic-in-memory chips. The 2D materials have been greatly studied due to atomically flat surfaces, higher carrier mobility, and excellent photoelectrical response. The 2D ReS2 flake is an excellent candidate for channel materials due to thickness-independent direct bandgap and outstanding optoelectronic response. In this paper, the floating gate devices are prepared with the ReS2 /h-BN/Gr heterojunction. It obtains superior nonvolatile electrical memory characteristics, including a higher memory window ratio (81.82%), tiny writing/erasing voltage (±8 V/2 ms), long retention (>1000 s), and stable endurance (>1000 times) as well as multiple memory states. Meanwhile, electrical writing and optical erasing are achieved by applying electrical and optical pulses, and multilevel storage can easily be achieved by regulating light pulse parameters. Finally, due to the ideal long-time potentiation/depression synaptic weights regulated by light pulses and electrical pulses, the convolutional neural network (CNN) constructed by ReS2 /h-BN/Gr floating gate devices can achieve image recognition with an accuracy of up to 98.15% for MNIST dataset and 91.24% for Fashion-MNIST dataset. The research work adds a powerful option for 2D materials floating gate devices to apply to logic-in-memory chips and neuromorphic computing.

2D Dual Gate Field-Effect Transistor Enabled Versatile Functions

Advanced computing technologies such as distributed computing and the Internet of Things require highly integrated and multifunctional electronic devices. Beyond the Si technology, 2D-materials-based dual-gate transistors are expected to meet these demands due to the ultra-thin body and the dangling-bond-free surface. In this work, a molybdenum disulfide (MoS2 ) asymmetric-dual-gate field-effect transistor (ADGFET) with an In2 Se3 top gate and a global bottom gate is designed. The independently controlled double gates enable the device to achieve an on/off ratio of 106 with a low subthreshold swing of 94.3 mV dec-1 while presenting a logic function. The coupling effect between the double gates allows the top gate to work as a charge-trapping layer, realizing nonvolatile memory (105 on/off ratio with retention time over 104 s) and six-level memory states. Additionally, ADGFET displays a tunable photodetection with the responsivity reaching the highest value of 857 A W-1 , benefiting from the interface coupling between the double gates. Meanwhile, the photo-memory property of ADGFET is also verified by using the varying exposure dosages-dependent illumination. The multifunctional applications demonstrate that the ADGFET provides an alternative way to integrate logic, memory, and sensing into one device architecture.

Ultrafast Operation of 2D Heterostructured Nonvolatile Memory Devices Provided by the Strong Short-Time Dielectric Breakdown Strength of h-BN

Recently, the ultrafast operation (∼20 ns) of a two-dimensional (2D) heterostructured nonvolatile memory (NVM) device was demonstrated, attracting considerable attention. However, there is no consensus on its physical origin. In this study, various 2D NVM device structures are compared. First, we reveal that the hole injection at the metal/MoS₂ interface is the speed-limiting path in the NVM device with the access region. Therefore, MoS₂ NVM devices with a direct tunneling path between source/drain electrodes and the floating gate are fabricated by removing the access region. Indeed, a 50 ns program/erase operation is successfully achieved for devices with metal source/drain electrodes as well as graphite source/drain electrodes. This controlled experiment proves that an atomically sharp interface is not necessary for ultrafast operation, which is contrary to the previous literature. Finally, the dielectric breakdown strength (E_BD) of h-BN under short voltage pulses is examined. Since a high dielectric breakdown strength allows a large tunneling current, ultrafast operations can be achieved. Surprisingly, an E_BD = 26.1 MV/cm for h-BN is realized under short voltage pulses, largely exceeding the E_BD = ∼12 MV/cm from the direct current (DC) measurement. This suggests that the high E_BD of h-BN can be the physical origin of the ultrafast operation.

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS₂. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage Trajectory

Two-dimensional heterostructures have been extensively investigated as next-generation nonvolatile memory (NVM) devices. In the past decade, drastic performance improvements and further advanced functionalities have been demonstrated. However, this progress is not sufficiently supported by the understanding of their operations, obscuring the material and device structure design policy. Here, detailed operation mechanisms are elucidated by exploiting the floating gate (FG) voltage measurements. Systematic comparisons of MoTe₂, WSe₂, and MoS₂ channel devices revealed that the tunneling behavior between the channel and FG is controlled by three kinds of current-limiting paths, i.e., tunneling barrier, 2D/metal contact, and p-n junction in the channel. Furthermore, the control experiment indicated that the access region in the device structure is required to achieve 2D channel/FG tunneling by preventing electrode/FG tunneling. The present understanding suggests that the ambipolar 2D-based FG-type NVM device with the access region is suitable for further realizing potentially high electrical reliability.