Controlling Native Oxidation of HfS2 for 2D Materials Based Flash Memory and Artificial Synapse

Advancing Nanoelectronics Applications: Progress in Non-van der Waals 2D Materials

Extending the inventory of two-dimensional (2D) materials remains highly desirable, given their excellent properties and wide applications. Current studies on 2D materials mainly focus on the van der Waals (vdW) materials since the discovery of graphene, where properties of atomically thin layers have been found to be distinct from their bulk counterparts. Beyond vdW materials, there are abundant non-vdW materials that can also be thinned down to 2D forms, which are still in their early stage of exploration. In this review, we focus on the downscaling of non-vdW materials into 2D forms to enrich the 2D materials family. This underexplored group of 2D materials could show potential promise in many areas such as electronics, optics, and magnetics, as has happened in the vdW 2D materials. Hereby, we will focus our discussion on their electronic properties and applications of them. We aim to motivate and inspire fellow researchers in the 2D materials community to contribute to the development of 2D materials beyond the widely studied vdW layered materials for electronic device applications. We also give our insights into the challenges and opportunities to guide researchers who are desirous of working in this promising research area.

Polarized Tunneling Transistor for Ultralow-Energy-Consumption Artificial Synapse toward Neuromorphic Computing

Neural networks based on low-power artificial synapses can significantly reduce energy consumption, which is of great importance in today's era of artificial intelligence. Two-dimensional (2D) material-based floating-gate transistors (FGTs) have emerged as compelling candidates for simulating artificial synapses owing to their multilevel and nonvolatile data storage capabilities. However, the low erasing/programming speed of FGTs renders them unsuitable for low-energy-consumption artificial synapses, thereby limiting their potential in high-energy-efficient neuromorphic computing. Here, we introduce a FGT-inspired MoS2/Trap/PZT heterostructure-based polarized tunneling transistor (PTT) with a simple fabrication process and significantly enhanced erasing/programming speed. Distinct from the FGT, the PTT lacks a tunnel layer, leading to a marked improvement in its erasing/programming speed. The PTT's highest erasing/programming (operation) speed can reach ∼20 ns, which outperforms the performance of most FGTs based on 2D heterostructures. Furthermore, the PTT has been utilized as an artificial synapse, and its weight-update energy consumption can be as low as 0.0002 femtojoule (fJ), which benefits from the PTT's ultrahigh operation speed. Additionally, PTT-based artificial synapses have been employed in constructing artificial neural network simulations, achieving facial-recognition accuracy (95%). This groundbreaking work makes it possible for fabricating future high-energy-efficient neuromorphic transistors utilizing 2D materials.

Plasma Processing and Treatment of 2D Transition Metal Dichalcogenides: Tuning Properties and Defect Engineering

Two-dimensional transition metal dichalcogenides (TMDs) offer fascinating opportunities for fundamental nanoscale science and various technological applications. They are a promising platform for next generation optoelectronics and energy harvesting devices due to their exceptional characteristics at the nanoscale, such as tunable bandgap and strong light-matter interactions. The performance of TMD-based devices is mainly governed by the structure, composition, size, defects, and the state of their interfaces. Many properties of TMDs are influenced by the method of synthesis so numerous studies have focused on processing high-quality TMDs with controlled physicochemical properties. Plasma-based methods are cost-effective, well controllable, and scalable techniques that have recently attracted researchers' interest in the synthesis and modification of 2D TMDs. TMDs' reactivity toward plasma offers numerous opportunities to modify the surface of TMDs, including functionalization, defect engineering, doping, oxidation, phase engineering, etching, healing, morphological changes, and altering the surface energy. Here we comprehensively review all roles of plasma in the realm of TMDs. The fundamental science behind plasma processing and modification of TMDs and their applications in different fields are presented and discussed. Future perspectives and challenges are highlighted to demonstrate the prominence of TMDs and the importance of surface engineering in next-generation optoelectronic applications.

PZT-Enabled MoS2 Floating Gate Transistors: Overcoming Boltzmann Tyranny and Achieving Ultralow Energy Consumption for High-Accuracy Neuromorphic Computing

Low-power electronic devices play a pivotal role in the burgeoning artificial intelligence era. The study of such devices encompasses low-subthreshold swing (SS) transistors and neuromorphic devices. However, conventional field-effect transistors (FETs) face the inherent limitation of the "Boltzmann tyranny", which restricts SS to 60 mV decade-1 at room temperature. Additionally, FET-based neuromorphic devices lack sufficient conductance states for highly accurate neuromorphic computing due to a narrow memory window. In this study, we propose a pioneering PZT-enabled MoS2 floating gate transistor (PFGT) configuration, demonstrating a low SS of 46 mV decade-1 and a wide memory window of 7.2 V in the dual-sweeping gate voltage range from -7 to 7 V. The wide memory window provides 112 distinct conductance states for PFGT. Moreover, the PFGT-based artificial neural network achieves an outstanding facial-recognition accuracy of 97.3%. This study lays the groundwork for the development of low-SS transistors and highly energy efficient artificial synapses utilizing two-dimensional materials.

Reconfigurable Artificial Synapse Based on Ambipolar Floating Gate Memory

Artificial synapse networks capable of massively parallel computing and mimicking biological neural networks can potentially improve the processing efficiency of existing information technologies. Semiconductor devices functioning as excitatory and inhibitory synapses are crucial for developing intelligence systems, such as traffic control systems. However, achieving reconfigurability between two working modes (inhibitory and excitatory) and bilingual synaptic behavior in a single transistor remains challenging. This study successfully mimics a bilingual synaptic response using an artificial synapse based on an ambipolar floating gate memory comprising tungsten selenide (WSe₂)/hexagonal boron nitride (h-BN)/ molybdenum telluride (MoTe₂). In this WSe₂/h-BN/MoTe₂ structure, ambipolar semiconductors WSe₂ and MoTe₂ are inserted as channel and floating gates, respectively, and h-BN serves as the tunneling barrier layer. Using either positive or negative pulse amplitude modulations at the control gate, this device with bipolar channel conduction produced eight distinct resistance states. Based on this, we experimentally projected that we could achieve 490 memory states (210 hole-resistance states + 280 electron-resistance states). Using the bipolar charge transport and multistorage states of WSe₂/h-BN/MoTe₂ floating gate memory, we mimicked reconfigurable excitatory and inhibitory synaptic plasticity in a single device. Furthermore, the convolution neural network formed by these synaptic devices can recognize handwritten digits with an accuracy of >92%. This study identifies the unique properties of heterostructure devices based on two-dimensional materials as well as predicts their applicability in advanced recognition of neuromorphic computing.

Double-Floating-Gate van der Waals Transistor for High-Precision Synaptic Operations

Two-dimensional materials and their heterostructures have thus far been identified as leading candidates for nanoelectronics owing to the near-atom thickness, superior electrostatic control, and adjustable device architecture. These characteristics are indeed advantageous for neuro-inspired computing hardware where precise programming is strongly required. However, its successful demonstration fully utilizing all of the given benefits remains to be further developed. Herein, we present van der Waals (vdW) integrated synaptic transistors with multistacked floating gates, which are reconfigured upon surface oxidation. When compared with a conventional device structure with a single floating gate, our double-floating-gate (DFG) device exhibits better nonvolatile memory performance, including a large memory window (>100 V), high on-off current ratio (∼10⁷), relatively long retention time (>5000 s), and satisfactory cyclic endurance (>500 cycles), all of which can be attributed to its increased charge-storage capacity and spatial redistribution. This facilitates highly effective modulation of trapped charge density with a large dynamic range. Consequently, the DFG transistor exhibits an improved weight update profile in long-term potentiation/depression synaptic behavior for nearly ideal classification accuracies of up to 96.12% (MNIST) and 81.68% (Fashion-MNIST). Our work adds a powerful option to vdW-bonded device structures for highly efficient neuromorphic computing.

Filamentary and Interface-Type Memristors Based on Tantalum Oxide for Energy-Efficient Neuromorphic Hardware

To implement artificial neural networks (ANNs) based on memristor devices, it is essential to secure the linearity and symmetry in weight update characteristics of the memristor, and reliability in the cycle-to-cycle and device-to-device variations. This study experimentally demonstrated and compared the filamentary and interface-type resistive switching (RS) behaviors of tantalum oxide (Ta₂O₅ and TaO₂)-based devices grown by atomic layer deposition (ALD) to propose a suitable RS type in terms of reliability and weight update characteristics. Although Ta₂O₅ is a strong candidate for memristor, the filament-type RS behavior of Ta₂O₅ does not fit well with ANNs demanding analog memory characteristics. Therefore, this study newly designed an interface-type TaO₂ memristor and compared it to a filament type of Ta₂O₅ memristor to secure the weight update characteristics and reliability. The TaO₂-based interface-type memristor exhibited gradual RS characteristics and area dependency in both high- and low-resistance states. In addition, compared to the filamentary memristor, the RS behaviors of the TaO₂-based interface-type device exhibited higher suitability for the neuromorphic, symmetric, and linear long-term potentiation (LTP) and long-term depression (LTD). These findings suggest better types of memristors for implementing ionic memristor-based ANNs among the two types of RS mechanisms.

Morphotaxy of Layered van der Waals Materials

Layered van der Waals (vdW) materials have attracted significant attention due to their materials properties that can enhance diverse applications including next-generation computing, biomedical devices, and energy conversion and storage technologies. This class of materials is typically studied in the two-dimensional (2D) limit by growing them directly on bulk substrates or exfoliating them from parent layered crystals to obtain single or few layers that preserve the original bonding. However, these vdW materials can also function as a platform for obtaining additional phases of matter at the nanoscale. Here, we introduce and review a synthesis paradigm, morphotaxy, where low-dimensional materials are realized by using the shape of an initial nanoscale precursor to template growth or chemical conversion. Using morphotaxy, diverse non-vdW materials such as HfO₂ or InF₃ can be synthesized in ultrathin form by changing the composition but preserving the shape of the original 2D layered material. Morphotaxy can also enable diverse atomically precise heterojunctions and other exotic structures such as Janus materials. Using this morphotaxial approach, the family of low-dimensional materials can be substantially expanded, thus creating vast possibilities for future fundamental studies and applied technologies.