Increasing the Room-Temperature Electric Double Layer Retention Time in Two-Dimensional Crystal FETs

A critical review of fabrication challenges and reliability issues in top/bottom gated MoS2field-effect transistors

The voyage of semiconductor industry to decrease the size of transistors to achieve superior device performance seems to near its physical dimensional limitations. The quest is on to explore emerging material systems that offer dimensional scaling to match the silicon- based technologies. The discovery of atomic flat two-dimensional materials has opened up a completely new avenue to fabricate transistors at sub-10 nanometer level which has the potential to compete with modern silicon-based semiconductor devices. Molybdenum disulfide (MoS₂) is a two-dimensional layered material with novel semiconducting properties at atomic level seems like a promising candidate that can possibly meet the expectation of Moore's law. This review discusses the various 'fabrication challenges' in making MoS₂based electronic devices from start to finish. The review outlines the intricate challenges of substrate selection and various synthesis methods of mono layer and few-layer MoS₂. The review focuses on the various techniques and methods to minimize interface defect density at substrate/MoS₂interface for optimum MoS₂-based device performance. The tunable band-gap of MoS₂with varying thickness presents a unique opportunity for contact engineering to mitigate the contact resistance issue using different elemental metals. In this work, we present a comprehensive overview of different types of contact materials with myriad geometries that show a profound impact on device performance. The choice of different insulating/dielectric gate oxides on MoS₂in co-planar and vertical geometry is critically reviewed and the physical feasibility of the same is discussed. The experimental constraints of different encapsulation techniques on MoS₂and its effect on structural and electronic properties are extensively discussed.

Electric-double-layer p-i-n junctions in WSe2

While p-n homojunctions in two-dimensional transition metal dichalcogenide materials have been widely reported, few show an ideality factor that is constant over more than a decade in current. In this paper, electric double layer p-i-n junctions in WSe2 are shown with substantially constant ideality factors (2-3) over more than 3 orders of magnitude in current. These lateral junctions use the solid polymer, polyethylene oxide: cesium perchlorate (PEO:CsClO4), to induce degenerate electron and hole carrier densities at the device contacts to form the junction. These high carrier densities aid in reducing the contact resistance and enable the exponential current dependence on voltage to be measured at higher currents than prior reports. Transport measurements of these WSe2 p-i-n homojunctions in combination with COMSOL multiphysics simulations are used to quantify the ion distributions, the semiconductor charge distributions, and the simulated band diagram of these junctions, to allow applications to be more clearly considered.

Low Voltage Graphene-Based Amplitude Modulator for High Efficiency Terahertz Modulation

In this paper, a high-efficiency terahertz amplitude modulation device based on a field-effect transistor has been proposed. The polarization insensitive modulator is designed to achieve a maximum experimental modulation depth of about 53% within 5 V of gate voltages using monolayer graphene. Moreover, the manufacturing processes are inexpensive. Two methods are adopted to improve modulation performance. For one thing, the metal metamaterial designed can effectively enhance the electromagnetic field near single-layer graphene and therefore greatly promote the graphene’s modulation ability in terahertz. For another, polyethylene oxide-based electrolytes (PEO:LiClO₄) acts as a high-capacity donor, which makes it possible to dope single-layer graphene at a relatively low voltage.

Ion-Locking in Solid Polymer Electrolytes for Reconfigurable Gateless Lateral Graphene p-n Junctions

A gateless lateral p-n junction with reconfigurability is demonstrated on graphene by ion-locking using solid polymer electrolytes. Ions in the electrolytes are used to configure electric-double-layers (EDLs) that induce p- and n-type regions in graphene. These EDLs are locked in place by two different electrolytes with distinct mechanisms: (1) a polyethylene oxide (PEO)-based electrolyte, PEO:CsClO₄, is locked by thermal quenching (i.e., operating temperature < T_g (glass transition temperature)), and (2) a custom-synthesized, doubly-polymerizable ionic liquid (DPIL) is locked by thermally triggered polymerization that enables room temperature operation. Both approaches are gateless because only the source/drain terminals are required to create the junction, and both show two current minima in the backgated transfer measurements, which is a signature of a graphene p-n junction. The PEO:CsClO₄ gated p-n junction is reconfigured to n-p by resetting the device at room temperature, reprogramming, and cooling to T < T_g. These results show an alternate approach to locking EDLs on 2D devices and suggest a path forward to reconfigurable, gateless lateral p-n junctions with potential applications in polymorphic logic circuits.

Electric Double-Layer Gating of Two-Dimensional Field-Effect Transistors Using a Single-Ion Conductor

Electric double-layer (EDL) gating using a custom-synthesized polyester single-ion conductor (PE400-Li) is demonstrated on two-dimensional (2D) crystals for the first time. The electronic properties of graphene and MoTe₂ field-effect transistors (FETs) gated with the single-ion conductor are directly compared to a poly(ethylene oxide) dual-ion conductor (PEO:CsClO₄). The anions in the single-ion conductor are covalently bound to the backbone of the polymer, leaving only the cations free to form an EDL at the negative electrode and a corresponding cationic depletion layer at the positive electrode. Because the cations are mobile in both the single- and dual-ion conductors, a similar enhancement of the n-branch is observed in both graphene and MoTe₂. Specifically, the single-ion conductor decreases the subthreshold swing in the n-branch of the bare MoTe₂ FET from 5000 to 250 mV/dec and increases the current density and on/off ratio by two orders of magnitude. However, the single-ion conductor suppressed the p-branch in both the graphene and the MoTe₂ FETs, and finite element modeling of ion transport shows that this result is unique to single-ion conductor gating in combination with an asymmetric gate/channel geometry. Both the experiments and modeling suggest that single-ion conductor-gated FETs can achieve sheet densities up to 10¹⁴ cm^-2, which corresponds to a charge density that would theoretically be sufficient to induce several percent strain in monolayer 2D crystals and potentially induce a semiconductor-to-metal phase transition in MoTe₂.

Pulse Dynamics of Electric Double Layer Formation on All-Solid-State Graphene Field-Effect Transistors

Electric double layer (EDL) dynamics in graphene field-effect transistors (FETs) gated with polyethylene oxide (PEO)-based electrolytes are studied by molecular dynamics (MD) simulations from picoseconds to nanoseconds and experimentally from microseconds to milliseconds. Under an applied field of approximately mV/nm, EDL formation on graphene FETs gated with PEO:CsClO₄ occurs on the timescale of microseconds at room temperature and strengthens within 1 ms to a sheet carrier density of n_S ≈ 10¹³ cm^-2. Stronger EDLs (i.e., larger n_S) are induced experimentally by pulsing with applied voltages exceeding the electrochemical window of the electrolyte; electrochemistry is avoided using short pulses of a few milliseconds. Dynamics on picosecond to nanosecond timescales are accessed using MD simulations of PEO:LiClO₄ between graphene electrodes with field strengths of hundreds of mV/nm which is 100× larger than experiment. At 100 mV/nm, EDL formation initiates in sub-nanoseconds achieving charge densities up to 6 × 10¹³ cm^-2 within 3 nanoseconds. The modeling shows that under sufficiently high electric fields, EDLs with densities ∼10¹³ cm^-2 can form within a nanosecond, which is a timescale relevant for high-performance electronics such as EDL transistors (EDLTs). Moreover, the combination of experiment and modeling shows that the timescale for EDL formation ( n_S = 10¹³ to 10¹⁴ cm^-2) can be tuned by 9 orders of magnitude by adjusting the field strength by only 3 orders of magnitude.