Ambipolar Deep-Subthreshold Printed-Carbon-Nanotube Transistors for Ultralow-Voltage and Ultralow-Power Electronics

Flexible Solid-Electrolyte-Gated-Dielectric Carbon Nanotube Thin Film Transistors and Integrated Circuits with the Recorded Radiation Tolerance and Reparability

Radiation-tolerance and repairable flexible transistors and integrated circuits (ICs) with low power consumption have become hot topics due to their wide applications in outer space, nuclear power plants, and X-ray imaging. Here, we designed and developed novel flexible semiconducting single-walled carbon nanotube (sc-SWCNT) thin-film transistors (TFTs) and ICs. Sc-SWCNT solid-electrolyte-gate dielectric (SEGD) TFTs showcase symmetric ambipolar characteristics with flat-band voltages (VFB) of ∼0 V, high ION/IOFF ratios (>105), and the recorded irradiation resistance (up to 22 Mrad). Moreover, flexible sc-SWCNT ICs, including CMOS-like inverters and NAND and NOR logic gates, have excellent operating characteristics with low power consumption (≤8.4 pW) and excellent irradiation resistance. Significantly, sc-SWCNT SEGD TFTs and ICs after radiation with a total irradiation dose (TID) ≥ 11 Mrad can be repaired after thermal heating at 100 °C. These outstanding characteristics are attributed to the designed device structures and key core materials including SEGD and sc-SWCNT.

Enhancement-Mode Carbon Nanotube Optoelectronic Synaptic Transistors with Large and Controllable Threshold Voltage Modulation Window for Broadband Flexible Vision Systems

The development of large-scale integration of optoelectronic neuromorphic devices with ultralow power consumption and broadband responses is essential for high-performance bionics vision systems. In this work, we developed a strategy to construct large-scale (40 × 30) enhancement-mode carbon nanotube optoelectronic synaptic transistors with ultralow power consumption (33.9 aJ per pulse) and broadband responses (from 365 to 620 nm) using low-work function yttrium (Y)-gate electrodes and the mixture of eco-friendly photosensitive Ag2S quantum dots (QDs) and ionic liquids (ILs)-cross-linking-poly(4-vinylphenol) (PVP) (ILs-c-PVP) as the dielectric layers. Solution-processable carbon nanotube thin-film transistors (TFTs) showed enhancement-mode characteristics with the wide and controllable threshold voltage window (-1 V∼0 V) owing to use of the low-work-function Y-gate electrodes. It is noted that carbon nanotube optoelectronic synaptic transistors exhibited high on/off ratios (>106), small hysteresis and low operating voltage (≤2 V), and enhancement mode even under the illumination of ultraviolet (UV, 365 nm), blue (450 nm), and green (550 nm) to red (620 nm) pulse lights when introducing eco-friendly Ag2S QDs in dielectric layers, demonstrating that they have the strong fault-tolerant ability for the threshold voltage drifts caused by various manufacturing scenarios. Furthermore, some important bionic functions including a high paired pulse facilitation index (PPF index, up to 290%), learning and memory function with the long duration (200 s), and rapid recovery (2 s). Pavlov's dog experiment (retention time up to 20 min) and visual memory forgetting experiments (the duration of high current for 180 s) are also demonstrated. Significantly, the optoelectronic synaptic transistors can be used to simulate the adaptive process of vision in varying light conditions, and we demonstrated the dynamic transition of light adaptation to dark adaptation based on light-induced conditional behavior. This work undoubtedly provides valuable insights for the future development of artificial vision systems.

Light-Triggerable and Gate-Tunable Negative Differential Resistance in Small Molecules Heterojunction

Negative differential resistance (NDR), a phenomenon in which the current decreases when the applied voltage is increased, is attracting attention as a unique electrical property. Here, we propose a broad spectral photo/gate cotunable channel switching NDR (CS-NDR) device. The proposed CS-NDR device has superior linear gate-tunable NDR behavior and highly reproducible properties compared to the previously reported NDR devices, as the fundamental mechanism of the CS-NDR device is directly related to a charge transport channel switching by the linear increase of the applied drain voltage. We also experimentally demonstrate that the photoinduced NDR behavior of the CS-NDR device was derived from the grain boundaries of dinaphtho[2;3-b:2',3'-f]-thieno[3,2-b]thiophene. Furthermore, this work produces a 9 × 9 CS-NDR device array composed of 81 devices, providing the reproducibility and uniformity of the CS-NDR device. Finally, we successfully demonstrate the detection of text images with 81 CS-NDR devices using the proposed photo/gate cotunable NDR behavior.

The Schottky barrier transistor in emerging electronic devices

This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable field-effect transistors (FETs) for sensors, neuromorphic hardware and security applications. Similarly, judicious use of an SB can be an asset for applications involving Josephson junction FETs.

Fully-Solution-Processed Enhancement-Mode Complementary Metal-Oxide-Semiconductor Carbon Nanotube Thin Film Transistors Based on BiI3 -Doped Crosslinked Poly(4-Vinylphenol) Dielectrics for Ultralow-Power Flexible Electronics

The threshold voltage (V_th ) adjustment of complementary metal-oxide-semiconductor (CMOS) thin film transistors (TFTs) is one of the research hotspots due to its key role in energy consumption control of CMOS circuits. Here, ultralow-power flexible CMOS circuits based on well-matched enhancement-mode (E-mode) CMOS single-walled carbon nanotube (SWCNT) TFTs are successfully achieved through tuning the work function of gate electrodes, electron doping, and printing techniques. E-mode P-type CMOS SWCNT TFTs with the full-solution procedure are first obtained through decreasing the work function of Ag gate electrodes directly caused by the deposition of bismuth iodide (BiI₃ )-doped solid-state electrolyte dielectrics. After synthetic optimization of dielectric compositions and semiconductor printing process, the flexible printed E-mode SWCNT TFTs show the high I_on /I_off ratios of ≈10⁶ , small subthreshold swing (SS) of 70-85 mV dec^-1 , low operating voltages of ≈0.5 to -1.5 V, good stability and excellent mechanical flexibility during 10 000 bending cycles. E-mode N-type SWCNT TFTs are then selectively achieved via printing the polarity conversion ink (2-Amino-2-methyl-1-propanol (AMP)  as electron  doping agent) in P- type TFT channels. Last, printed SWCNT CMOS inverters are successfully constructed with full rail-to-rail output characteristics and the record unit static power consumption of 6.75 fW µm^-1 at V_DD of 0.2 V.

Subthreshold Schottky-contacted carbon nanotube network film field-effect transistors for ultralow-power electronic applications

Ultralow-power electronics is critical to wearable, portable, and implantable applications where the systems could only have access to very limited electrical power supply or even be self-powered. Here, we report on a type of Schottky barrier (SB) contacted single-walled carbon nanotube (SWCNT) network film field-effect-transistors (FETs) that are operated in the subthreshold region to achieve ultralow-power applications. The thin high-k gate dielectric and the overlap between the gate and the source electrodes offer highly efficient gate electrostatic control over the SWCNT channel and the SB at the source contact, resulting in steep subthreshold switching characteristics with a small subthreshold swing (∼67 mV dec^-1), a large current on/off ratio (∼10⁶), and a low off-state current (∼0.5 pA). Ap-channel metal-oxide-semiconductor inverter built with the subthreshold SB-SWCNT-FETs exhibits a well-defined logic functionality and small-signal amplification capability under a low supply voltage (∼0.5 V) and an ultralow power (∼0.05 pWμm^-1). The low-voltage and deep subthreshold operations reported here could lay an essential foundation for high-performance and ultralow-power SWCNTs-based electronics.

Ultralow-Power and Radiation-Tolerant Complementary Metal-Oxide-Semiconductor Electronics Utilizing Enhancement-Mode Carbon Nanotube Transistors on Paper Substrates

The development of eco-friendly, ultralow-power and easy-to-process electronics is facing dominant challenges in emerging off-the-grid applications, such as the Internet of Things (IoTs) and extreme environment explorations at the south/north pole, in the deep sea, and in outer space. Eco-friendly, biodegradable, lightweight, and flexible paper-based electronics can provide many new possibilities for next-generation devices and circuits. Here, enhancement-mode (E-mode, remaining off state at zero gate voltages) carbon nanotube (CNT) complementary metal-oxide-semiconductor (CMOS) thin-film transistors (TFTs) are built on paper substrates through a printing-based process. Benefitting from the CMOS circuit style and E-mode transistors, the fabricated CMOS inverters exhibit high voltage gains (more than 11) and noise margins (up to 75% 1/2 V_DD at V_DD of 0.4 V), and rail-to-rail operation down to a V_DD as low as 0.2 V and record low power dissipation as low as 0.0124 pW μm^-1 . Furthermore, the transistors and integrated circuits (ICs) show an excellent radiation tolerance of a total ionizing dose (TID) exceeding 2 Mrad with a high dose rate of 365 rad s^-1 . The record power consumption and outstanding radiation tolerance behavior achieved in paper-based and easy-to-process CNT electronics are attractive for emerging energy-saving and environmentally friendly ICs in harsh environment (such as outer-space) applications.

Optimisation of geometric aspect ratio of thin film transistors for low-cost flexible CMOS inverters and its practical implementation

A low-cost, flexible processor is essential to realise affordable flexible electronic systems and transform everyday objects into smart-objects. Thin film transistors (TFTs) based on metal-oxides (or organics) are ideal candidates as they can be manufactured at low processing temperatures and low-cost per unit area, unlike traditional silicon devices. The development of complementary metal–oxide–semiconductor (CMOS) technology based on these materials remains challenging due to differences in performance between n- and p-type TFTs. Existing geometric rules typically compensate the lower mobility of the metal-oxide p-type TFT by scaling up the width-to-length (W/L) ratio but fail to take into account the significant off-state leakage current. Here we propose the concept of an optimal geometric aspect ratio which maximises the inverter efficiency represented by the average switching current divided by the static currents. This universal method is especially useful for the design of low-power CMOS inverters based on metal-oxides, where the large off-current of the p-type TFT dominates the static power consumption of the inverter. We model the inverter efficiency and noise margins of metal-oxide CMOS inverters with different geometric aspect ratios and compare the performance to different inverter configurations. The modelling results are verified experimentally by fabricating CMOS inverter configurations consisting of n-type indium-silicon-oxide (ISO) TFTs and p-type tin monoxide (SnO) TFTs. Notably, our results show that reducing W/L of metal-oxide p-type TFTs increases the inverter efficiency while reducing the area compared to simply scaling up W/L inversely with mobility. We anticipate this work provides a straightforward method to geometrically optimise flexible CMOS inverters, which will remain relevant even as the performance of TFTs continues to evolve.

Advances and Frontiers in Single-Walled Carbon Nanotube Electronics

Single-walled carbon nanotubes (SWCNTs) have been considered as one of the most promising electronic materials for the next-generation electronics in the more Moore era. Sub-10 nm SWCNT-field effect transistors (FETs) have been realized with several performances exceeding those of Si-based FETs at the same feature size. Several industrial initiatives have attempted to implement SWCNT electronics in integrated circuit (IC) chips. Here, the recent advances in SWCNT electronics are reviewed from in-depth understanding of the fundamental electronic structures, the carrier transport mechanisms, and the metal/SWCNT contact properties. In particular, the subthreshold switching properties are highlighted for low-power, energy-efficient device operations. State-of-the-art low-power SWCNT-based electronics and the key strategies to realize low-voltage and low-power operations are outlined. Finally, the essential challenges and prospects from the material preparation, device fabrication, and large-scale ICs integration for future SWCNT-based electronics are foregrounded.

A Review on Printed Electronics: Fabrication Methods, Inks, Substrates, Applications and Environmental Impacts

Innovations in industrial automation, information and communication technology (ICT), renewable energy as well as monitoring and sensing fields have been paving the way for smart devices, which can acquire and convey information to the Internet. Since there is an ever-increasing demand for large yet affordable production volumes for such devices, printed electronics has been attracting attention of both industry and academia. In order to understand the potential and future prospects of the printed electronics, the present paper summarizes the basic principles and conventional approaches while providing the recent progresses in the fabrication and material technologies, applications and environmental impacts.

Heterogeneous Wafer Bonding Technology and Thin-Film Transfer Technology-Enabling Platform for the Next Generation Applications beyond 5G

Wafer bonding technology is one of the most effective methods for high-quality thin-film transfer onto different substrates combined with ion implantation processes, laser irradiation, and the removal of the sacrificial layers. In this review, we systematically summarize and introduce applications of the thin films obtained by wafer bonding technology in the fields of electronics, optical devices, on-chip integrated mid-infrared sensors, and wearable sensors. The fabrication of silicon-on-insulator (SOI) wafers based on the Smart CutTM process, heterogeneous integrations of wide-bandgap semiconductors, infrared materials, and electro-optical crystals via wafer bonding technology for thin-film transfer are orderly presented. Furthermore, device design and fabrication progress based on the platforms mentioned above is highlighted in this work. They demonstrate that the transferred films can satisfy high-performance power electronics, molecular sensors, and high-speed modulators for the next generation applications beyond 5G. Moreover, flexible composite structures prepared by the wafer bonding and de-bonding methods towards wearable electronics are reported. Finally, the outlooks and conclusions about the further development of heterogeneous structures that need to be achieved by the wafer bonding technology are discussed.