All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration

A memristive-photoconductive transduction methodology for accurately nondestructive memory readout

Crossbar resistive memory architectures enable high-capacity storage and neuromorphic computing, accurate retrieval of the stored information is a prerequisite during read operation. However, conventional electrical readout normally suffer from complicated process, inaccurate and destructive reading due to crosstalk effect from sneak path current. Here we report a memristive-photoconductive transduction (MPT) methodology for precise and nondestructive readout in a memristive crossbar array. The individual devices present dynamic filament form/fuse for resistance modulation under electric stimulation, which leads to photogenerated carrier transport for tunable photoconductive response under subsequently light pulse stimuli. This coherent signal transduction can be used to directly detect the memorized on/off states stored in each cell, and a prototype 4 * 4 crossbar memories has been constructed and validated for the fidelity of crosstalk-free readout in recall process.

Thermally Oxidized Memristor and 1T1R Integration for Selector Function and Low-Power Memory

Resistive switching memories have garnered significant attention due to their high-density integration and rapid in-memory computing beyond von Neumann's architecture. However, significant challenges are posed in practical applications with respect to their manufacturing process complexity, a leakage current of high resistance state (HRS), and the sneak-path current problem that limits their scalability. Here, a mild-temperature thermal oxidation technique for the fabrication of low-power and ultra-steep memristor based on Ag/TiOx/SnOx/SnSe2/Au architecture is developed. Benefiting from a self-assembled oxidation layer and the formation/rupture of oxygen vacancy conductive filaments, the device exhibits an exceptional threshold switching behavior with high switch ratio exceeding 106, low threshold voltage of ≈1 V, long-term retention of >104 s, an ultra-small subthreshold swing of 2.5 mV decade-1 and high air-stability surpassing 4 months. By decreasing temperature, the device undergoes a transition from unipolar volatile to bipolar nonvolatile characteristics, elucidating the role of oxygen vacancies migration on the resistive switching process. Further, the 1T1R structure is established between a memristor and a 2H-MoTe2 transistor by the van der Waals (vdW) stacking approach, achieving the functionality of selector and multi-value memory with lower power consumption. This work provides a mild-thermal oxidation technology for the low-cost production of high-performance memristors toward future in-memory computing applications.

Programmable Retention Characteristics in MoS2-Based Atomristors for Neuromorphic and Reservoir Computing Systems

In this study, we investigate the coexistence of short- and long-term memory effects owing to the programmable retention characteristics of a two-dimensional Au/MoS2/Au atomristor device and determine the impact of these effects on synaptic properties. This device is constructed using bilayer MoS2 in a crossbar structure. The presence of both short- and long-term memory characteristics is proposed by using a filament model within the bilayer transition-metal dichalcogenide. Short- and long-term properties are validated based on programmable multilevel retention tests. Moreover, we confirm various synaptic characteristics of the device, demonstrating its potential use as a synaptic device in a neuromorphic system. Excitatory postsynaptic current, paired-pulse facilitation, spike-rate-dependent plasticity, and spike-number-dependent plasticity synaptic applications are implemented by operating the device at a low-conductance level. Furthermore, long-term potentiation and depression exhibit symmetrical properties at high-conductance levels. Synaptic learning and forgetting characteristics are emulated using programmable retention properties and composite synaptic plasticity. The learning process of artificial neural networks is used to achieve high pattern recognition accuracy, thereby demonstrating the suitability of the use of the device in a neuromorphic system. Finally, the device is used as a physical reservoir with time-dependent inputs to realize reservoir computing by using short-term memory properties. Our study reveals that the proposed device can be applied in artificial intelligence-based computing applications by utilizing its programmable retention properties.

High-performance one-dimensional halide perovskite crossbar memristors and synapses for neuromorphic computing

Despite impressive demonstrations of memristive behavior with halide perovskites, no clear pathway for material and device design exists for their applications in neuromorphic computing. Present approaches are limited to single element structures, fall behind in terms of switching reliability and scalability, and fail to map out the analog programming window of such devices. Here, we systematically design and evaluate robust pyridinium-templated one-dimensional halide perovskites as crossbar memristive materials for artificial neural networks. We compare two halide perovskite 1D inorganic lattices, namely (propyl)pyridinium and (benzyl)pyridinium lead iodide. The absence of conjugated, electron-rich substituents in PrPyr+ prevents edge-to-face type π-stacking, leading to enhanced electronic isolation of the 1D iodoplumbate chains in (PrPyr)[PbI3], and hence, superior resistive switching performance compared to (BnzPyr)[PbI3]. We report outstanding resistive switching behaviours in (PrPyr)[PbI3] on the largest flexible crossbar implementation (16 × 16) to date - on/off ratio (>105), long term retention (105 s) and high endurance (2000 cycles). Finally, we put forth a universal approach to comprehensively map the analog programming window of halide perovskite memristive devices - a critical prerequisite for weighted synaptic connections in artificial neural networks. This consequently facilitates the demonstration of accurate handwritten digit recognition from the MNIST database based on spike-timing-dependent plasticity of halide perovskite memristive synapses.

Van der Waals polarity-engineered 3D integration of 2D complementary logic

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1-3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6-8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9-17) and MoS2 (refs. 11,18-28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V-1 s-1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

2D Memory Selectors with Giant Nonlinearity Enabled by Van der Waals Heterostructures

The integration of one-selector-one-resistor crossbar arrays requires the selectors featured with high nonlinearity and bipolarity to prevent leakage currents and any crosstalk among distinct cells. However, a selector with sufficient nonlinearity especially in the frame of device miniaturization remains scarce, restricting the advance of high-density storage devices. Herein, a high-performance memory selector is reported by constructing a graphene/hBN/WSe2 heterostructure. Within the temperature range of 300-80 K, the nonlinearity of this selector varies from ≈103 - ≈104 under forward bias, and increases from ≈300 - ≈105 under reverse bias, the highest reported nonlinearity among 2D selectors. This improvement is ascribed to direct tunneling at low bias and Fowler-Nordheim tunneling at high bias. The tunneling current versus voltage curves exhibit excellent bipolarity behavior because of the comparable hole and electron tunneling barriers, and the charge transport polarity can be effectively tuned from N-type or P-type to bipolar by simply changing source-drain bias. In addition, the conceptual memory selector exhibits no sign of deterioration after 70 000 switching cycles, paving the way for assembling 2D selectors into modern memory devices.

Solution-Processable and Printable Two-Dimensional Transition Metal Dichalcogenide Inks

Two-dimensional (2D) transition metal dichalcogenides (TMDs) with layered crystal structures have been attracting enormous research interest for their atomic thickness, mechanical flexibility, and excellent electronic/optoelectronic properties for applications in diverse technological areas. Solution-processable 2D TMD inks are promising for large-scale production of functional thin films at an affordable cost, using high-throughput solution-based processing techniques such as printing and roll-to-roll fabrications. This paper provides a comprehensive review of the chemical synthesis of solution-processable and printable 2D TMD ink materials and the subsequent assembly into thin films for diverse applications. We start with the chemical principles and protocols of various synthesis methods for 2D TMD nanosheet crystals in the solution phase. The solution-based techniques for depositing ink materials into solid-state thin films are discussed. Then, we review the applications of these solution-processable thin films in diverse technological areas including electronics, optoelectronics, and others. To conclude, a summary of the key scientific/technical challenges and future research opportunities of solution-processable TMD inks is provided.

Low Power Volatile and Nonvolatile Memristive Devices from 1D MoO2-MoS2 Core-Shell Heterostructures for Future Bio-Inspired Computing

Memristors-based integrated circuits for emerging bio-inspired computing paradigms require an integrated approach utilizing both volatile and nonvolatile memristive devices. Here, an innovative architecture comprising of 1D CVD-grown core-shell heterostructures (CSHSs) of MoO2-MoS2 is employed as memristors manifesting both volatile switching (with high selectivity of 107 and steep slope of 0.6 mV decade-1) and nonvolatile switching phenomena (with Ion/Ioff ≈103 and switching speed of 60 ns). In these CSHSs, the metallic core MoO2 with high current carrying capacity provides a conformal and immaculate interface with semiconducting MoS2 shells and therefore it acts as a bottom electrode for the memristors. The power consumption in volatile devices is as low as 50 pW per set transition and 0.1 fW in standby mode. Voltage-driven current spikes are observed for volatile devices while with nonvolatile memristors, key features of a biological synapse such as short/long-term plasticity and paired pulse facilitation are emulated suggesting their potential for the development of neuromorphic circuits. These CSHSs offer an unprecedented solution for the interfacial issues between metallic electrodes and the layered materials-based switching element with the prospects of developing smaller footprint memristive devices for future integrated circuits.

Ag-doped non-imperfection-enabled uniform memristive neuromorphic device based on van der Waals indium phosphorus sulfide

Memristors are considered promising energy-efficient artificial intelligence hardware, which can eliminate the von Neumann bottleneck by parallel in-memory computing. The common imperfection-enabled memristors are plagued with critical variability issues impeding their commercialization. Reported approaches to reduce the variability usually sacrifice other performances, e.g., small on/off ratios and high operation currents. Here, we demonstrate an unconventional Ag-doped nonimperfection diffusion channel-enabled memristor in van der Waals indium phosphorus sulfide, which can combine ultralow variabilities with desirable metrics. We achieve operation voltage, resistance, and on/off ratio variations down to 3.8, 2.3, and 6.9% at their extreme values of 0.2 V, 1011 ohms, and 108, respectively. Meanwhile, the operation current can be pushed from 1 nA to 1 pA at the scalability limit of 6 nm after Ag doping. Fourteen Boolean logic functions and convolutional image processing are successfully implemented by the memristors, manifesting the potential for logic-in-memory devices and efficient non-von Neumann accelerators.

Technology and Integration Roadmap for Optoelectronic Memristor

Optoelectronic memristors (OMs) have emerged as a promising optoelectronic Neuromorphic computing paradigm, opening up new opportunities for neurosynaptic devices and optoelectronic systems. These OMs possess a range of desirable features including minimal crosstalk, high bandwidth, low power consumption, zero latency, and the ability to replicate crucial neurological functions such as vision and optical memory. By incorporating large-scale parallel synaptic structures, OMs are anticipated to greatly enhance high-performance and low-power in-memory computing, effectively overcoming the limitations of the von Neumann bottleneck. However, progress in this field necessitates a comprehensive understanding of suitable structures and techniques for integrating low-dimensional materials into optoelectronic integrated circuit platforms. This review aims to offer a comprehensive overview of the fundamental performance, mechanisms, design of structures, applications, and integration roadmap of optoelectronic synaptic memristors. By establishing connections between materials, multilayer optoelectronic memristor units, and monolithic optoelectronic integrated circuits, this review seeks to provide insights into emerging technologies and future prospects that are expected to drive innovation and widespread adoption in the near future.

Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials

The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.

p-Type Two-Dimensional Semiconductors: From Materials Preparation to Electronic Applications

Two-dimensional (2D) materials are regarded as promising candidates in many applications, including electronics and optoelectronics, because of their superior properties, including atomic-level thickness, tunable bandgaps, large specific surface area, and high carrier mobility. In order to bring 2D materials from the laboratory to industrialized applications, materials preparation is the first prerequisite. Compared to the n-type analogs, the family of p-type 2D semiconductors is relatively small, which limits the broad integration of 2D semiconductors in practical applications such as complementary logic circuits. So far, many efforts have been made in the preparation of p-type 2D semiconductors. In this review, we overview recent progresses achieved in the preparation of p-type 2D semiconductors and highlight some promising methods to realize their controllable preparation by following both the top-down and bottom-up strategies. Then, we summarize some significant application of p-type 2D semiconductors in electronic and optoelectronic devices and their superiorities. In end, we conclude the challenges existed in this field and propose the potential opportunities in aspects from the discovery of novel p-type 2D semiconductors, their controlled mass preparation, compatible engineering with silicon production line, high-κ dielectric materials, to integration and applications of p-type 2D semiconductors and their heterostructures in electronic and optoelectronic devices. Overall, we believe that this review will guide the design of preparation systems to fulfill the controllable growth of p-type 2D semiconductors with high quality and thus lay the foundations for their potential application in electronics and optoelectronics.

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10's of MHz.

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T-4R structure for high-density memory

Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems.

Multiple-State Nonvolatile Memory Based on Ultrathin Indium Oxide Film via Liquid Metal Printing

In this work, the ultrathin two-dimensional (2D) indium oxide (InO_x) with a large area of more than 100 μm² and a high degree of uniformity was automatically peeled off from indium by the liquid-metal printing technique. Raman and optical measurements revealed that 2D-InO_x has a polycrystalline cubic structure. By altering the printing temperature which affects the crystallinity of 2D-InO_x, the mechanism of the existence and disappearance of memristive characteristics was established. The tunable characteristics of the 2D-InO_x memristor with reproducible one-order switching was manifest from the electrical measurements. Further adjustable multistate characteristics of the 2D-InO_x memristor and its resistance switching mechanism were evaluated. A detailed examination of the memristive process demonstrated the Ca²⁺ mimic dynamic in 2D-InO_x memristors as well as the fundamental principles underlying biological and artificial synapses. These surveys allow us to comprehend a 2D-InO_x memristor using the liquid-metal printing technique and could be applied to future neuromorphic applications and in the field of revolutionary 2D material exploration.

Hardware and Information Security Primitives Based on 2D Materials and Devices

Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon-based complementary metal-oxide-semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon-based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D-materials-based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large-scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

Se-Vacancy Healing with Substitutional Oxygen in WSe2 for High-Mobility p-Type Field-Effect Transistors

Transition-metal dichalcogenides possess high carrier mobility and can be scaled to sub-nanometer dimensions, making them viable alternative to Si electronics. WSe₂ is capable of hole and electron carrier transport, making it a key component in CMOS logic circuits. However, since the p-type electrical performance of the WSe₂-field effect transistor (FET) is still limited, various approaches are being investigated to circumvent this issue. Here, we formed a heterostructural multilayer WSe₂ channel and solution-processed aluminum-doped zinc oxide (AZO) for compositional modification of WSe₂ to obtain a device with excellent electrical properties. Supplying oxygen anions from AZO to the WSe₂ channel eliminated subgap states through Se-deficiency healing, resulting in improved transport capacity. Se vacancies are known to cause mobility degradation due to scattering, which is mitigated through ionic compensation. Consequently, the hole mobility can reach high values, with a maximum of approximately 100 cm²/V s. Further, the transport behavior of the oxygen-doped WSe₂-FET is systematically analyzed using density functional theory simulations and photoexcited charge collection spectroscopy measurements.

Controllable digital and analog resistive switching behavior of 2D layered WSe2 nanosheets for neuromorphic computing

Memristors with controllable resistive switching (RS) behavior have been considered as promising candidates for synaptic devices in next-generation neuromorphic computing. In this work, two-terminal memristors with controllable digital and analog RS behavior are fabricated based on two-dimensional (2D) WSe₂ nanosheets. Under a relatively high operating voltage of 4 V, the memristor demonstrates stable and reliable non-volatile bipolar digital RS with a high switching ratio of 6.3 × 10⁴. On the other hand, under a relatively low operation voltage, the memristor exhibits analog RS with a series of tunable resistance states. The fabricated memristors can work as an artificial synapse with fundamental synaptic functions, such as long-term potentiation (LTP) and depression (LTD) as well as paired-pulse facilitation (PPF). More importantly, the memristor demonstrates high conductance modulation linearity with the calculated nonlinear parameter for conductance as -0.82 in the LTP process, which is beneficial to improving the accuracy of neuromorphic computing. Furthermore, the neuromorphic computing of file types and image recognition can be emulated based on a constructed three-layer artificial neural network (ANN) with a recognition accuracy that can reach up to 95.9% for small digits. In addition, memristors can be used to emulate the learning-forgetting experience of the human brain. Consequently, the memristor based on 2D WSe₂ nanosheets not only exhibits controllable RS behavior but also simulates synaptic functions and is expected to be a potential candidate for future neuromorphic computing applications.

Resistive random access memory: introduction to device mechanism, materials and application to neuromorphic computing

The modern-day computing technologies are continuously undergoing a rapid changing landscape; thus, the demands of new memory types are growing that will be fast, energy efficient and durable. The limited scaling capabilities of the conventional memory technologies are pushing the limits of data-intense applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Resistive random access memory (RRAM) is one of the most suitable emerging memory technologies candidates that have demonstrated potential to replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. RRAM has grown in prominence in the recent years due to its simple structure, long retention, high operating speed, ultra-low-power operation capabilities, ability to scale to lower dimensions without affecting the device performance and the possibility of three-dimensional integration for high-density applications. Over the past few years, research has shown RRAM as one of the most suitable candidates for designing efficient, intelligent and secure computing system in the post-CMOS era. In this manuscript, the journey and the device engineering of RRAM with a special focus on the resistive switching mechanism are detailed. This review also focuses on the RRAM based on two-dimensional (2D) materials, as 2D materials offer unique electrical, chemical, mechanical and physical properties owing to their ultrathin, flexible and multilayer structure. Finally, the applications of RRAM in the field of neuromorphic computing are presented.

Resistive Switching Crossbar Arrays Based on Layered Materials

Resistive switching (RS) devices are metal/insulator/metal cells that can change their electrical resistance when electrical stimuli are applied between the electrodes, and they can be used to store and compute data. Planar crossbar arrays of RS devices can offer a high integration density (>10⁸  devices mm^{- 2} ) and this can be further enhanced by stacking them three-dimensionally. The advantage of using layered materials (LMs) in RS devices compared to traditional phase-change materials and metal oxides is that their electrical properties can be adjusted with a higher precision. Here, the key figures-of-merit and procedures to implement LM-based RS devices are defined. LM-based RS devices fabricated using methods compatible with industry are identified and discussed. The focus is on small devices (size < 9 µm² ) arranged in crossbar structures, since larger devices may be affected by artifacts, such as grain boundaries and flake junctions. How to enhance device performance, so to accelerate the development of this technology, is also discussed.

Fully Optical in Operando Investigation of Ambient Condition Electrical Switching in MoS2 Nanodevices

MoS₂ nanoswitches have shown superb ultralow switching energies without excessive leakage currents. However, the debate about the origin and volatility of electrical switching is unresolved due to the lack of adequate nanoimaging of devices in operando. Here, three optical techniques are combined to perform the first noninvasive in situ characterization of nanosized MoS₂ devices. This study reveals volatile threshold resistive switching due to the intercalation of metallic atoms from electrodes directly between Mo and S atoms, without the assistance of sulfur vacancies. A "semi-memristive" effect driven by an organic adlayer adjacent to MoS₂ is observed, which suggests that nonvolatility can be achieved by careful interface engineering. These findings provide a crucial understanding of nanoprocess in vertically biased MoS₂ nanosheets, which opens new routes to conscious engineering and optimization of 2D electronics.

Self-Assembled TaOX/2H-TaS2 as a van der Waals Platform of a Multilevel Memristor Circuit Integrated with a β-Ga2O3 Transistor

Two-dimensional (2D)-layered material tantalum disulfide (2H-TaS₂) is known to be a van der Waals conductor at room temperature. Here, 2D-layered TaS₂ has been partially oxidized by utraviolet-ozone (UV-O₃) annealing to form a 12-nm-thin TaO_X on conducting TaS₂, so that the TaO_X/2H-TaS₂ structure might be self-assembled. Utilizing the TaO_X/2H-TaS₂ structure as a platform, each device of a β-Ga₂O₃ channel MOSFET and a TaO_X memristor has been successfully fabricated. An insulator structure of Pt/TaO_X/2H-TaS₂ shows good a dielectric constant (k ∼ 21) and strength (∼3 MV/cm) of achieved TaO_X, which is enough to support a β-Ga₂O₃ transistor channel. Based on the quality of TaO_X and low trap density of the TaO_X/β-Ga₂O₃ interface, which is achieved via another UV-O₃ annealing, excellent device properties such as little hysteresis (<∼0.04 V), band-like transport, and a steep subthreshold swing of ∼85 mV/dec are achieved. With a Cu electrode on top of the TaO_X/2H-TaS₂ structure, the TaO_X acts as a memristor operating around ∼2 V for nonvolatile bipolar and unipolar mode memories. The functionalities of the TaO_X/2H-TaS₂ platform become more distinguished finally when the Cu/TaO_X/2H-TaS₂ memristor and β-Ga₂O₃ MOSFET are integrated to form a resistive memory switching circuit. The circuit nicely demonstrates the multilevel memory functions.

Printed Electronics Based on 2D Material Inks: Preparation, Properties, and Applications toward Memristors

Printed electronics, which fabricate electrical components and circuits on various substrates by leveraging functional inks and advanced printing technologies, have recently attracted tremendous attention due to their capability of large-scale, high-speed, and cost-effective manufacturing and also their great potential in flexible and wearable devices. To further achieve multifunctional, practical, and commercial applications, various printing technologies toward smarter pattern-design, higher resolution, greater production flexibility, and novel ink formulations toward multi-functionalities and high quality have been insensitively investigated. 2D materials, possessing atomically thin thickness, unique properties and excellent solution-processable ability, hold great potential for high-quality inks. Besides, the great variety of 2D materials ranging from metals, semiconductors to insulators offers great freedom to formulate versatile inks to construct various printed electronics. Here, a detailed review of the progress on 2D material inks formulation and its printed applications has been provided, specifically with an emphasis on emerging printed memristors. Finally, the challenges facing the field and prospects of 2D material inks and printed electronics are discussed.

Integrated Memory Devices Based on 2D Materials

With the advent of the Internet of Things and big data, massive data must be rapidly processed and stored within a short timeframe. This imposes stringent requirements on memory hardware implementation in terms of operation speed, energy consumption, and integration density. To fulfill these demands, 2D materials, which are excellent electronic building blocks, provide numerous possibilities for developing advanced memory device arrays with high performance, smart computing architectures, and desirable downscaling. Over the past few years, 2D-material-based memory-device arrays with different working mechanisms, including defects, filaments, charges, ferroelectricity, and spins, have been increasingly developed. These arrays can be used to implement brain-inspired computing or sensing with extraordinary performance, architectures, and functionalities. Here, recent research into integrated, state-of-the-art memory devices made from 2D materials, as well as their implications for brain-inspired computing are surveyed. The existing challenges at the array level are discussed, and the scope for future research is presented.

Two-dimensional devices and integration towards the silicon lines

Despite technical efforts and upgrades, advances in complementary metal-oxide-semiconductor circuits have become unsustainable in the face of inherent silicon limits. New materials are being sought to compensate for silicon deficiencies, and two-dimensional materials are considered promising candidates due to their atomically thin structures and exotic physical properties. However, a potentially applicable method for incorporating two-dimensional materials into silicon platforms remains to be illustrated. Here we try to bridge two-dimensional materials and silicon technology, from integrated devices to monolithic 'on-silicon' (silicon as the substrate) and 'with-silicon' (silicon as a functional component) circuits, and discuss the corresponding requirements for material synthesis, device design and circuitry integration. Finally, we summarize the role played by two-dimensional materials in the silicon-dominated semiconductor industry and suggest the way forward, as well as the technologies that are expected to become mainstream in the near future.

Reproducible Non-Volatile Multi-State Storage and Emulation of Synaptic Plasticity Based on a Copper-Nanoparticle-Embedded HfOx/ZnO Bilayer with Ultralow-Switching Current and Ideal Data Retention

The multilevel properties of a memristor are significant for applications in non-volatile multi-state storage and electronic synapses. However, the reproducibility and stability of the intermediate resistance states are still challenging. A stacked HfOx/ZnO bilayer embedded with copper nanoparticles was thus proposed to investigate its multilevel properties and to emulate synaptic plasticity. The proposed memristor operated at the microampere level, which was ascribed to the barrier at the HfOx/ZnO interface suppressing the operational current. Compared with the stacked HfOx/ZnO bilayer without nanoparticles, the proposed memristor had a larger ON/OFF resistance ratio (~330), smaller operational voltages (absolute value < 3.5 V) and improved cycle-to-cycle reproducibility. The proposed memristor also exhibited four reproducible non-volatile resistance states, which were stable and well retained for at least ~1 year at 85 °C (or ~10 years at 70 °C), while for the HfOx/ZnO bilayer without copper nanoparticles, the minimum retention time of its multiple resistance states was ~9 days at 85 °C (or ~67 days at 70 °C). Additionally, the proposed memristor was capable of implementing short-term and long-term synaptic plasticities.

Advances in Emerging Photonic Memristive and Memristive-Like Devices

Possessing the merits of high efficiency, low consumption, and versatility, emerging photonic memristive and memristive-like devices exhibit an attractive future in constructing novel neuromorphic computing and miniaturized bionic electronic system. Recently, the potential of various emerging materials and structures for photonic memristive and memristive-like devices has attracted tremendous research efforts, generating various novel theories, mechanisms, and applications. Limited by the ambiguity of the mechanism and the reliability of the material, the development and commercialization of such devices are still rare and in their infancy. Therefore, a detailed and systematic review of photonic memristive and memristive-like devices is needed to further promote its development. In this review, the resistive switching mechanisms of photonic memristive and memristive-like devices are first elaborated. Then, a systematic investigation of the active materials, which induce a pivotal influence in the overall performance of photonic memristive and memristive-like devices, is highlighted and evaluated in various indicators. Finally, the recent advanced applications are summarized and discussed. In a word, it is believed that this review provides an extensive impact on many fields of photonic memristive and memristive-like devices, and lay a foundation for academic research and commercial applications.

Physical Insights into Vacancy-Based Memtransistors: Toward Power Efficiency, Reliable Operation, and Scalability

Memtransistors that combine the properties of transistor and memristor hold significant promise for in-memory computing. While superior data storage capability is achieved in memtransistors through gate voltage-induced conductance modulation, the lateral device configuration would not only result in high write bias, which compromises the power efficiency, but also suffers from unsuccessful memory reset that leads to reliability concerns. To circumvent such performance limitations, an advanced physics-based model is required to uncover the dynamic resistive switching behavior and deduce the key driving parameters for the switching process. This work demonstrates a self-consistent physics-based model which incorporates the often-overlooked effects of lattice temperature, vacancy dynamics, and channel electrostatics to accurately solve the interaction between gate potential, ions, and carriers on the memristive switching mechanism. The completed model is carefully calibrated with an ambipolar WSe2 memtransistor and hence enables the investigation of the carrier polarity effect (electrons vs holes) on vacancy transport. Nevertheless, the validity of the model can be extended to different materials by a simple material-dependent parameter modification. Building upon the existing understanding of Schottky barrier height modulation, our study reveals three key insights─leveraging threshold voltage shifts to lower write bias; optimizing lattice temperature distribution and read bias polarity to achieve successful memory state recovery; engineering contact work function to overcome the detrimental parasitic current flow in short channel ambipolar memtransistors. Therefore, understanding the significant correlation between the switching mechanisms, different material systems, and device structures allows performance optimization of operating modes and device designs for future memtransistors-based computing systems.

An FPGA-based system for generalised electron devices testing

Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R &D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit, and \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2\times $$\end{document}2× banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${170}\,\hbox {pA}$$\end{document}170pA current noise floor, \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${40}\,\hbox {ns}$$\end{document}40ns pulse delivery at \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\pm {13.5}\,\hbox {V}$$\end{document}±13.5V and \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${12}\,\hbox {mA}$$\end{document}12mA maximum current drive/channel. We then showcase the instrument’s use in performing a selection of three characteristic measurement tasks: (a) current–voltage characterisation of a diode and a transistor, (b) fully parallel read-out of a memristor crossbar array and (c) an integral non-linearity test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies.

Applications of biomemristors in next generation wearable electronics

With the rapid development of mobile internet and artificial intelligence, wearable electronic devices have a great market prospect. In particular, information storage and processing of real-time collected data are an indispensable part of wearable electronic devices. Biomaterial-based memristive systems are suitable for storage and processing of the obtained information in wearable electronics due to the accompanying merits, i.e. sustainability, lightweight, degradability, low power consumption, flexibility and biocompatibility. So far, many biomaterial-based flexible and wearable memristive devices were prepared by spin coating or other technologies on a flexible substrate at room temperature. However, mechanical deformation caused by mechanical mismatch between devices and soft tissues leads to the instability of device performance. From the current research and practical application, the device will face great challenges when adapting to different working environments. In fact, some interesting studies have been performed to address the above issues while they were not intensively highlighted and overviewed. Herein, the progress in wearable biomemristive devices is reviewed, and the outlook and perspectives are provided in consideration of the existing challenges during the development of wearable biomemristive systems.

Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing

Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their development in next-generation information storage and neuromorphic computing. Here, wafer-scale integration of solution-processed two-dimensional MoS₂ memristor arrays are reported. The MoS₂ memristors achieve excellent endurance, long memory retention, low device variations, and high analog on/off ratio with linear conductance update characteristics. The two-dimensional nanosheets appear to enable a unique way to modulate switching characteristics through the inter-flake sulfur vacancies diffusion, which can be controlled by the flake size distribution. Furthermore, the MNIST handwritten digits recognition shows that the MoS₂ memristors can operate with a high accuracy of >98.02%, which demonstrates its feasibility for future analog memory applications. Finally, a monolithic three-dimensional memory cube has been demonstrated by stacking the two-dimensional MoS₂ layers, paving the way for the implementation of two memristor into high-density neuromorphic computing system.

Neuromorphic computing requires the realization of high-density and reliable random-access memories. Here, Thean et al. demonstrate wafer-scale integration of solution-processed 2D MoS2 memristor arrays which show long endurance, long memory retention, low device variations, and high on/off ratio.

Controllable Preparation of 2D Vertical van der Waals Heterostructures and Superlattices for Functional Applications

2D van der Waals heterostructures (vdWHs) and superlattices (SLs) with exotic physical properties and applications for new devices have attracted immense interest. Compared to conventionally bonded heterostructures, the dangling-bond-free surface of 2D layered materials allows for the feasible integration of various materials to produce vdWHs without the requirements of lattice matching and processing compatibility. The quality of interfaces in artificially stacked vdWHs/vdWSLs and scalability of production remain among the major challenges in the field of 2D materials. Fortunately, bottom-up methods exhibit relatively high controllability and flexibility. The growth parameters, such as the temperature, precursors, substrate, and carrier gas, can be carefully and comprehensively controlled to produce high-quality interfaces and wafer-scale products of vdWHs/vdWSLs. This review focuses on three types of bottom-up methods for the assembly of vdWHs and vdWSLs with atomically clean and electronically sharp interfaces: chemical/physical vapor deposition, metal-organic chemical vapor deposition, and ultrahigh vacuum growth. These methods can intuitively illustrate the great flexibility and controllability of bottom-up methods for the preparation of vdWHs/vdWSLs. The latest progress in vdWHs and vdWSLs, related physical phenomena, and (opto)electronic devices are summarized. Finally, the authors discuss current challenges and future perspectives in the synthesis and application of vdWHs and vdWSLs.

NeuroPack: An Algorithm-Level Python-Based Simulator for Memristor-Empowered Neuro-Inspired Computing

Emerging two-terminal nanoscale memory devices, known as memristors, have demonstrated great potential for implementing energy-efficient neuro-inspired computing architectures over the past decade. As a result, a wide range of technologies have been developed that, in turn, are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors’ attributes in novel neuro-inspired topologies. In this study, we present NeuroPack, a modular, algorithm-level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to choose from a variety of neuron models, learning rules, and memristor models. Its hierarchical structure empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameter options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.

A van der Waals Integrated Damage-Free Memristor Based on Layered 2D Hexagonal Boron Nitride

2D materials with intriguing properties have been widely used in optoelectronics. However, electronic devices suffered from structural damage due to the ultrathin materials and uncontrolled defects at interfaces upon metallization, which hindered the development of reliable devices. Here, a damage-free Au/h-BN/Au memristor is reported using a clean, water-assisted metal transfer approach by physically assembling Au electrodes onto the layered h-BN which minimized the structural damage and undesired interfacial defects. The memristors demonstrate significantly improved performance with the coexistence of nonpolar and threshold switching as well as tunable current levels by controlling the compliance current, compared with devices with evaporated contacts. The devices integrated into an array show suppressed sneak path current and can work as both logic gates and latches to implement logic operations allowing in-memory computing. Cross-sectional scanning transmission electron microscopy analysis validates the feasibility of this nondestructive metal integration approach, the crucial role of high-quality atomically sharp interface in resistive switching, and a direct observation of percolation path. The underlying mechanism of boron vacancies-assisted transport is further supported experimentally by conductive atomic force microscopy free from process-induced damage, and theoretically by ab initio simulations.

Emerging 2D Memory Devices for In-Memory Computing

It is predicted that the conventional von Neumann computing architecture cannot meet the demands of future data-intensive computing applications due to the bottleneck between the processing and memory units. To try to solve this problem, in-memory computing technology, where calculations are carried out in situ within each nonvolatile memory unit, has been intensively studied. Among various candidate materials, 2D layered materials have recently demonstrated many new features that have been uniquely exploited to build next-generation electronics. Here, the recent progress of 2D memory devices is reviewed for in-memory computing. For each memory configuration, their operation mechanisms and memory characteristics are described, and their pros and cons are weighed. Subsequently, their versatile applications for in-memory computing technology, including logic operations, electronic synapses, and random number generation are presented. Finally, the current challenges and potential strategies for future 2D in-memory computing systems are also discussed at the material, device, circuit, and architecture levels. It is hoped that this manuscript could give a comprehensive review of 2D memory devices and their applications in in-memory computing, and be helpful for this exciting research area.

Ultrafast, Kinetically Limited, Ambient Synthesis of Vanadium Dioxides through Laser Direct Writing on Ultrathin Chalcogenide Matrix

Vanadium dioxide (VO₂) is a strongly correlated electronic material and has attracted significant attention due to its metal-to-insulator transition and diverse smart applications. Traditional synthesis of VO₂ usually requires minutes or hours of global heating and low oxygen partial pressure to achieve thermodynamic control of the valence state. Further patterning of VO₂ through a series of lithography and etching processes may inevitably change its surface valence, which poses a great challenge for the assembly of micro- and nanoscale VO₂-based heterojunction devices. Herein, we report an ultrafast method to simultaneously synthesize and pattern VO₂ on the time scale of seconds under ambient conditions through laser direct writing on a V₅S₈ "canvas". The successful ambient synthesis of VO₂ is attributed to the ultrafast local heating and cooling process, resulting in controlled freezing of the intermediate oxidation phase during the relatively long kinetic reaction. A Mott memristor based on a V₅S₈-VO₂-V₅S₈ lateral heterostructure can be fabricated and integrated with a MoS₂ channel, delivering a transistor with abrupt switching transfer characteristics. The other device with a VS_xO_y channel exhibits a large negative temperature coefficient of approximately 4.5%/K, which is highly desirable for microbolometers. The proposed approach enables fast and efficient integration of VO₂-based heterojunction devices and is applicable to other intriguing intermediate phases of oxides.

High-Stability Memristive Devices Based on Pd Conductive Filaments and Its Applications in Neuromorphic Computing

Memristive devices with high-density and high-speed performance have considerable potential for neuromorphic computing applications in data storage and artificial synapses. However, current memristive devices that are based on conductive filaments, such as silver, are unstable owing to the high mobility and low thermodynamic stability of the filaments. A high-quality SnSe film was deposited using the pulsed laser deposition technology, and high-performance Pd/SnSe/NSTO devices were fabricated. High-stability memristive devices can not only implement simple arithmetic function but also exhibit the centralized distribution of SET/RESET voltage and cell-cell uniformity. The SET/RESET power can achieve approximately 4.1 and 61 μW power. The possibility of Pd filament formation and Pd²⁺ diffusion in SnSe thin films is first confirmed by combining high-resolution transmission electron microscopy, energy-dispersive spectrometer mapping, and first principle calculation. The formation and destruction process of Pd filaments can simulate the influx and extrusion kinetics of K⁺, Ca²⁺, or Na⁺ in biological synapses and implements considerable synaptic functions. This study thus provides a new idea for improving device performance using different filament materials, which can greatly facilitate the development of neuromorphic computing.

Bi2O2Se-Based Memristor-Aided Logic

The implementation of two-dimensional materials into memristor architectures has recently been a new research focus by taking advantage of their atomic thickness, unique lattice, and physical and electronic properties. Among the van der Waals family, Bi₂O₂Se is an emerging ternary two-dimensional layered material with ambient stability, suitable band structure, and high conductivity that exhibits high potential for use in electronic applications. In this work, we propose and experimentally demonstrate a Bi₂O₂Se-based memristor-aided logic. By carefully tuning the electric field polarity of Bi₂O₂Se through a Pd contact, a reconfigurable NAND gate with zero static power consumption is realized. To provide more knowledge on NAND operation, a kinetic Monte Carlo simulation is carried out. Because the NAND gate is a universal logic gate, cascading additional NAND gates can exhibit versatile logic functions. Therefore, the proposed Bi₂O₂Se-based MAGIC can be a promising building block for developing next-generation in-memory logic computers with multiple functions.

A synaptic memristor based on two-dimensional layered WSe2 nanosheets with short- and long-term plasticity

Neural synapses with diverse synaptic functions of short- and long-term plasticity are highly desired for developing complex neuromorphic systems. A memristor with its two terminals serving as pre- and post-neurons, respectively, can emulate two neuronal-based synaptic functions. In this work, multilayer two-dimensional (2D) layered WSe₂ nanosheets are synthesized by a salt-assisted chemical vapor deposition (CVD) method. Two-terminal memristors with a planar structure are fabricated based on the CVD-grown triangular WSe₂ nanosheets. The fabricated devices exhibit typical bipolar nonvolatile resistive switching behaviors with a high current ON/OFF ratio of up to 6 × 10³ and good retention and endurance properties, suggesting good stability and reliability of the WSe₂-based memristors. Furthermore, the developed memristors demonstrate synaptic functions of short- and long-term plasticity (STP and LTP), as well as a transition from STP to LTP by applying consecutive pulse voltages. Moreover, the WSe₂-based memristors exhibits biological synaptic functions of long-term potentiation and depression, and paired-pulse facilitation. Thus, our 2D WSe₂ nanosheet based memristors not only exhibit stable and reliable nonvolatile resistive switching behaviors, but also show potential applications in mimicking biological synapses.

Self-Selective Multi-Terminal Memtransistor Crossbar Array for In-Memory Computing

Two-terminal resistive switching devices are commonly plagued with longstanding scientific issues including interdevice variability and sneak current that lead to computational errors and high-power consumption. This necessitates the integration of a separate selector in a one-transistor-one-RRAM (1T-1R) configuration to mitigate crosstalk issue, which compromises circuit footprint. Here, we demonstrate a multi-terminal memtransistor crossbar array with increased parallelism in programming via independent gate control, which allows in situ computation at a dense cell size of 3-4.5 F² and a minimal sneak current of 0.1 nA. Moreover, a low switching energy of 20 fJ/bit is achieved at a voltage of merely 0.42 V. The architecture is capable of performing multiply-and-accumulate operation, a core computing task for pattern classification. A high MNIST recognition accuracy of 96.87% is simulated owing to the linear synaptic plasticity. Such computing paradigm is deemed revolutionary toward enabling data-centric applications in artificial intelligence and Internet-of-things.

Ultrasensitive Magnetic Sensors Enabled by Heterogeneous Integration of Graphene Hall Elements and Silicon Processing Circuits

Graphene Hall elements (GHEs) have been demonstrated to be promising magnetic field sensors with excellent sensitivity, linearity, temperature stability, and compatibility with complementary-metal-oxide-semiconductor (CMOS)-integrated circuits (ICs). However, the demonstrated GHEs have still not exhibited a comprehensive advantage in performance over commercial integrated Hall sensors which were implemented in integrated Hall element and CMOS processing ICs. In this work, we develop a technology for the three-dimensional (3D) heterogeneous integration of silicon-based CMOS ICs and GHEs, and the fabricated magnetic field sensors outperform commercial high-end integrated Hall sensors. Specifically, the integrated Hall sensors are implemented in a stacked integration on Si based on a chopper programmable-gain amplifier (CPGA), a chopper-stabilized second-order sigma-delta modulator (CSDM), and graphene-based Hall elements on monochips. GHEs with high sensitivity (up to 1000 A/VT) are fabricated with a compatible process on a smoothened silicon nitride passivation layer of silicon-based CMOS ICs, and the two device layers are connected by an interlayer. The heterogeneous integrated Hall ICs exhibit current and voltage magnetic sensitivities up to 64 000 A/VT and 6.12 V/VT, respectively, which are much higher than those in all other reported nanomaterial-based Hall sensors and even in high-end commercial Hall ICs. Furthermore, the 3D heterogeneous integration technology used here can be extended as a universal technology for integrating nanomaterial-based sensors and Si CMOS ICs.

Logic-in-memory based on an atomically thin semiconductor

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von-Neumann architectures, brain-inspired in-memory computing uses the same basic device structure for logic operations and data storage^1–3, thus promising to reduce the energy cost of data-centric computing significantly⁴. While there is ample research focused on exploring new device architectures, the engineering of material platforms suitable for such device designs remains a challenge. Two-dimensional materials^5,6 such as semiconducting MoS2 could stand out as a promising candidate to face this obstacle thanks to their exceptional electrical and mechanical properties^7–9. Here, we explore large-area grown MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFET). The conductance of our FGFETs can be precisely and continuously tuned, allowing us to use them as building blocks for reconfigurable logic circuits where logic operations can be directly performed using the memory elements. After demonstrating a programmable NOR gate, we show that this design can be simply extended to implement more complex programmable logic and functionally complete sets of functions. Our findings highlight the potential of atomically thin semiconductors for the development of next-generation low-power electronics.

Thickness Trends of Electron and Hole Conduction and Contact Carrier Injection in Surface Charge Transfer Doped 2D Field Effect Transistors

One of the main limiting factors in the performance of devices based on two-dimensional (2D) materials is Fermi level pinning at the contacts, which creates Schottky barriers (SBs) that increase contact resistance and, for most transition metal dichalcogenides (TMDs), limit hole conduction. A promising method to mitigate these problems is surface charge transfer doping (SCTD), which places fixed charge at the surface of the material and thins the SBs by locally shifting the energy bands. We use a mild O₂ plasma to convert the top few layers of a given TMD into a substoichiometric oxide that serves as a p-type SCTD layer. A comprehensive experimental study, backed by TCAD simulations, involving MoS₂, MoSe₂, MoTe₂, WS₂, and WSe₂ flakes of various thicknesses exposed to different plasma times is used to investigate the underlying mechanisms responsible for SCTD. The surface charge at the top of the channel and the gate-modulated surface potential at the bottom are found to have competing effects on the channel potential, which results in a decrease in the doping-induced threshold shift and an increase in minimum OFF state current with increasing thickness. Additionally, an undoped channel region is shown to mitigate carrier injection issues in sufficiently thin flakes. Notably, the band movements underlying the SCTD effects are independent of the particular semiconductor material, SCTD strategy, and doping polarity. Consequently, our findings provide critical insights for the design of high-performance transistors for a wide range of materials and SCTD mechanisms including TMD devices with strong hole conduction.

Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for defect-tolerant neuromorphic systems

A crossbar array architecture employing resistive switching memory (RRAM) as a synaptic element accelerates vector-matrix multiplication in a parallel fashion, enabling energy-efficient pattern recognition. To implement the function of the synapse in the RRAM, multilevel resistance states are required. More importantly, a large on/off ratio of the RRAM should be preferentially obtained to ensure a reasonable margin between each state taking into account the inevitable variability caused by the inherent switching mechanism. The on/off ratio is basically adjusted in two ways by modulating measurement conditions such as compliance current or voltage pulses modulation. The latter technique is not only more suitable for practical systems, but also can achieve multiple states in low current range. However, at the expense of applying a high negative voltage aimed at enlarging the on/off ratio, a breakdown of the RRAM occurs unexpectedly. This stuck-at-short fault of the RRAM adversely affects the recognition process based on reading and judging each column current changed by the multiplication of the input voltage and resistance of the RRAM in the array, degrading the accuracy. To address this challenge, we introduce a boost-factor adjustment technique as a fault-tolerant scheme based on simple circuitry that eliminates the additional process to identify specific locations of the failed RRAMs in the array. Spectre circuit simulation is performed to verify the effect of the scheme on Modified National Institute of Standards and Technology dataset using convolutional neural networks in non-ideal crossbar arrays, where experimentally observed imperfective RRAMs are configured. Our results show that the recognition accuracy can be maintained similar to the ideal case because the interruption of the failure is suppressed by the scheme.

Filamentary Resistive Switching and Capacitance-Voltage Characteristics of the a-IGZO/TiO2 Memory

In this study, molybdenum tungsten/amorphous InGaZnO (a-IGZO)/TiO₂/n-type Si-based resistive random access memory (ReRAM) is manufactured. After deposition of the a-IGZO, annealing was performed at 200, 300, 400, and 500 °C for approximately 1 h in order to analyze the effect of temperature change on the ReRAM after post annealing in a furnace. As a result of measuring the current-voltage curve, the a-IGZO/TiO₂-based ReRAM annealed at 400 °C reached compliance current in a low-resistance state, and showed the most complete hysteresis curve. In the a-IGZO layer annealed at 400 °C, the O₁/O_total value increased most significantly, to approximately 78.2%, and the O₃/O_total value decreased the most, to approximately 2.6%. As a result, the a-IGZO/TiO₂-based ReRAM annealed at 400 °C reduced conductivity and prevented an increase in leakage current caused by oxygen vacancies with sufficient recovery of the metal-oxygen bond. Scanning electron microscopy analysis revealed that the a-IGZO surface showed hillocks at a high post annealing temperature of 500 °C, which greatly increased the surface roughness and caused the surface area performance to deteriorate. Finally, as a result of measuring the capacitance-voltage curve in the a-IGZO/TiO₂-based ReRAM in the range of −2 V to 4 V, the accumulation capacitance value of the ReRAM annealed at 400 °C increased most in a nonvolatile behavior.

Artificial Intelligence Algorithm Enabled Industrial-Scale Graphene Characterization

No characterization method is available to quickly perform quality inspection of 2D materials produced on an industrial scale. This hinders the adoption of 2D materials for product manufacturing in many industries. Here, we report an artificial-intelligence-assisted Raman analysis to quickly probe the quality of centimeter-large graphene samples in a non-destructive manner. Chemical vapor deposition of graphene is devised in this work such that two types of samples were obtained: layer-plus-islands and layer-by-layer graphene films, at centimeter scales. Using these samples, we implemented and integrated an unsupervised learning algorithm with an automated Raman spectroscopy to precisely cluster 20,250 and 18,000 Raman spectra collected from layer-plus-islands and layer-by-layer graphene films, respectively, into five and two clusters. Each cluster represents graphene patches with different layer numbers and stacking orders. For instance, the two clusters detected in layer-by-layer graphene films represent monolayer and bilayer graphene based on their Raman fingerprints. Our intelligent Raman analysis is fully automated, with no human operation involved, is highly reliable (99.95% accuracy), and can be generalized to other 2D materials, paving the way towards industrialization of 2D materials for various applications in the future.