Implementing in-situ self-organizing maps with memristor crossbar arrays for data mining and optimization

Hyperplane tree-based data mining with a multi-functional memristive crossbar array

This study explores the stochastic and binary switching behaviors of a Ta/HfO2/RuO2 memristor to implement a combined data mining approach for outlier detection and data clustering algorithms in a multi-functional memristive crossbar array. The memristor switches stochastically with high state dispersion in the stochastic mode and deterministically between two states with low dispersion in the binary mode, while they can be controlled by varying operating voltages. The stochastic mode facilitates the parallel generation of random hyperplanes in a tree structure, used to compress spatial information of the dataset in the Euclidian space into binary format, still retaining sufficient spatial features. The ensemble effect from multiple trees improved the classification performance. The binary mode facilitates parallel Hamming distance calculation of the binary codes containing spatial information, which measures similarity. These two modes enable efficient implementation of the newly proposed minority-based outlier detection method and modified K-means method on the same hardware. Array measurements and hardware simulations investigate various hyperparameters' impact and validate the proposed methods with practical datasets. The proposed methods show linear O(n) time complexity and high energy efficiency, consuming <1% of the energy compared to digital computing with conventional algorithms while demonstrating software-comparable performance in both tasks.

Heterogeneous density-based clustering with a dual-functional memristive array

In the big data era, the requirement for data clustering methods that can handle massive and heterogeneous datasets with varying distributions increases. This study proposes a clustering algorithm for data sets with heterogeneous density using a dual-mode memristor crossbar array for data clustering. The array consists of a Ta/HfO2/RuO2 memristor operating in analog or digital modes, controlled by the reset voltage. The digital mode shows low dispersion and a high resistance ratio, and the analog mode enables precise conductance tuning. The local outlier factor is introduced to handle a heterogeneous density, and the required Euclidean and K-distances within the given dataset are calculated in the analog mode in parallel. In the digital mode, clustering is performed based on the connectivity among data points after excluding the detected outliers. The proposed algorithm boasts linear time complexity for the entire process. Extensive evaluations of synthetic datasets demonstrate significant improvement over representative density-based algorithms, and the datasets with heterogeneous density are clustered feasibly. Finally, the proposed algorithm is used to cluster the single-molecule localization microscopy data, demonstrating the feasibility of the suggested method for real-world problems.

Machine learning without a processor: Emergent learning in a nonlinear analog network

Standard deep learning algorithms require differentiating large nonlinear networks, a process that is slow and power-hungry. Electronic contrastive local learning networks (CLLNs) offer potentially fast, efficient, and fault-tolerant hardware for analog machine learning, but existing implementations are linear, severely limiting their capabilities. These systems differ significantly from artificial neural networks as well as the brain, so the feasibility and utility of incorporating nonlinear elements have not been explored. Here, we introduce a nonlinear CLLN-an analog electronic network made of self-adjusting nonlinear resistive elements based on transistors. We demonstrate that the system learns tasks unachievable in linear systems, including XOR (exclusive or) and nonlinear regression, without a computer. We find our decentralized system reduces modes of training error in order (mean, slope, curvature), similar to spectral bias in artificial neural networks. The circuitry is robust to damage, retrainable in seconds, and performs learned tasks in microseconds while dissipating only picojoules of energy across each transistor. This suggests enormous potential for fast, low-power computing in edge systems like sensors, robotic controllers, and medical devices, as well as manufacturability at scale for performing and studying emergent learning.

Reconfigurable Ag/HfO2/NiO/Pt Memristors with Stable Synchronous Synaptic and Neuronal Functions for Renewable Homogeneous Neuromorphic Computing System

Artificial synapses and bionic neurons offer great potential in highly efficient computing paradigms. However, complex requirements for specific electronic devices in neuromorphic computing have made memristors face the challenge of process simplification and universality. Herein, reconfigurable Ag/HfO2/NiO/Pt memristors are designed for feasible switching between volatile and nonvolatile modes by compliance current controlled Ag filaments, which enables stable and reconfigurable synaptic and neuronal functions. A neuromorphic computing system effectively replicates the biological synaptic weight alteration and continuously accomplishes excitation and reset of artificial neurons, which consist of bionic synapses and artificial neurons based on isotype Ag/HfO2/NiO/Pt memristors. This reconfigurable electrical performance of the Ag/HfO2/NiO/Pt memristors takes advantage of simplified hardware design and delivers integrated circuits with high density, which exhibits great potency for future neural networks.

Unveiling IoT Customer Behaviour: Segmentation and Insights for Enhanced IoT-CRM Strategies: A Real Case Study

In today's competitive landscape, achieving customer-centricity is paramount for the sustainable growth and success of organisations. This research is dedicated to understanding customer preferences in the context of the Internet of things (IoT) and employs a two-part modeling approach tailored to this digital era. In the first phase, we leverage the power of the self-organizing map (SOM) algorithm to segment IoT customers based on their connected device usage patterns. This segmentation approach reveals three distinct customer clusters, with the second cluster demonstrating the highest propensity for IoT device adoption and usage. In the second phase, we introduce a robust decision tree methodology designed to prioritize various factors influencing customer satisfaction in the IoT ecosystem. We employ the classification and regression tree (CART) technique to analyze 17 key questions that assess the significance of factors impacting IoT device purchase decisions. By aligning these factors with the identified IoT customer clusters, we gain profound insights into customer behaviour and preferences in the rapidly evolving world of connected devices. This comprehensive analysis delves into the factors contributing to customer retention in the IoT space, with a strong emphasis on crafting logical marketing strategies, enhancing customer satisfaction, and fostering customer loyalty in the digital realm. Our research methodology involves surveys and questionnaires distributed to 207 IoT users, categorizing them into three distinct IoT customer groups. Leveraging analytical statistical methods, regression analysis, and IoT-specific tools and software, this study rigorously evaluates the factors influencing IoT device purchases. Importantly, this approach not only effectively clusters the IoT customer relationship management (IoT-CRM) dataset but also provides valuable visualisations that are essential for understanding the complex dynamics of the IoT customer landscape. Our findings underscore the critical role of logical marketing strategies, customer satisfaction, and customer loyalty in enhancing customer retention in the IoT era. This research offers a significant contribution to businesses seeking to optimize their IoT-CRM strategies and capitalize on the opportunities presented by the IoT ecosystem.

Reconfigurable Neuromorphic Computing: Materials, Devices, and Integration

Neuromorphic computing has been attracting ever-increasing attention due to superior energy efficiency, with great promise to promote the next wave of artificial general intelligence in the post-Moore era. Current approaches are, however, broadly designed for stationary and unitary assignments, thus encountering reluctant interconnections, power consumption, and data-intensive computing in that domain. Reconfigurable neuromorphic computing, an on-demand paradigm inspired by the inherent programmability of brain, can maximally reallocate finite resources to perform the proliferation of reproducibly brain-inspired functions, highlighting a disruptive framework for bridging the gap between different primitives. Although relevant research has flourished in diverse materials and devices with novel mechanisms and architectures, a precise overview remains blank and urgently desirable. Herein, the recent strides along this pursuit are systematically reviewed from material, device, and integration perspectives. At the material and device level, one comprehensively conclude the dominant mechanisms for reconfigurability, categorized into ion migration, carrier migration, phase transition, spintronics, and photonics. Integration-level developments for reconfigurable neuromorphic computing are also exhibited. Finally, a perspective on the future challenges for reconfigurable neuromorphic computing is discussed, definitely expanding its horizon for scientific communities.

Flash-Based Computing-in-Memory Architecture to Implement High-Precision Sparse Coding

To address the concerns with power consumption and processing efficiency in big-size data processing, sparse coding in computing-in-memory (CIM) architectures is gaining much more attention. Here, a novel Flash-based CIM architecture is proposed to implement large-scale sparse coding, wherein various matrix weight training algorithms are verified. Then, with further optimizations of mapping methods and initialization conditions, the variation-sensitive training (VST) algorithm is designed to enhance the processing efficiency and accuracy of the applications of image reconstructions. Based on the comprehensive characterizations observed when considering the impacts of array variations, the experiment demonstrated that the trained dictionary could successfully reconstruct the images in a 55 nm flash memory array based on the proposed architecture, irrespective of current variations. The results indicate the feasibility of using Flash-based CIM architectures to implement high-precision sparse coding in a wide range of applications.

A Robust Memristor-Enhanced Polynomial Hyper-Chaotic Map and Its Multi-Channel Image Encryption Application

Nowadays, the utilization of memristors to enhance the dynamical properties of chaotic systems has become a popular research topic. In this paper, we present the design of a novel 2D memristor-enhanced polynomial hyper-chaotic map (2D-MPHM) by utilizing the cross-coupling of two TiO2 memristors. The dynamical properties of the 2D-MPHM were investigated using Lyapunov exponents, bifurcation diagrams, and trajectory diagrams. Additionally, Kolmogorov entropy and sample entropy were also employed to evaluate the complexity of the 2D-MPHM. Numerical analysis has demonstrated the superiority of the 2D-MPHM. Subsequently, the proposed 2D-MPHM was applied to a multi-channel image encryption algorithm (MIEA-MPHM) whose excellent security was demonstrated by key space, key sensitivity, plaintext sensitivity, information entropy, pixel distribution, correlation analysis, and robustness analysis. Finally, the encryption efficiency of the MIEA-MPHM was evaluated via numerous encryption efficiency tests. These tests demonstrate that the MIEA-MPHM not only possesses excellent security but also offers significant efficiency advantages, boasting an average encryption rate of up to 87.2798 Mbps.

Open-loop analog programmable electrochemical memory array

Emerging memories have been developed as new physical infrastructures for hosting neural networks owing to their low-power analog computing characteristics. However, accurately and efficiently programming devices in an analog-valued array is still largely limited by the intrinsic physical non-idealities of the devices, thus hampering their applications in in-situ training of neural networks. Here, we demonstrate a passive electrochemical memory (ECRAM) array with many important characteristics necessary for accurate analog programming. Different image patterns can be open-loop and serially programmed into our ECRAM array, achieving high programming accuracies without any feedback adjustments. The excellent open-loop analog programmability has led us to in-situ train a bilayer neural network and reached software-like classification accuracy of 99.4% to detect poisonous mushrooms. The training capability is further studied in simulation for large-scale neural networks such as VGG-8. Our results present a new solution for implementing learning functions in an artificial intelligence hardware using emerging memories.

Two-Terminal MoS2 Memristor and the Homogeneous Integration with a MoS2 Transistor for Neural Networks

Memristors are promising candidates for constructing neural networks. However, their dissimilar working mechanism to that of the addressing transistors can result in a scaling mismatch, which may hinder efficient integration. Here, we demonstrate two-terminal MoS₂ memristors that work with a charge-based mechanism similar to that in transistors, which enables the homogeneous integration with MoS₂ transistors to realize one-transistor-one-memristor addressable cells for assembling programmable networks. The homogenously integrated cells are implemented in a 2 × 2 network array to demonstrate the enabled addressability and programmability. The potential for assembling a scalable network is evaluated in a simulated neural network using obtained realistic device parameters, which achieves over 91% pattern recognition accuracy. This study also reveals a generic mechanism and strategy that can be applied to other semiconducting devices for the engineering and homogeneous integration of memristive systems.

Technology Roadmap for Flexible Sensors

Humans rely increasingly on sensors to address grand challenges and to improve quality of life in the era of digitalization and big data. For ubiquitous sensing, flexible sensors are developed to overcome the limitations of conventional rigid counterparts. Despite rapid advancement in bench-side research over the last decade, the market adoption of flexible sensors remains limited. To ease and to expedite their deployment, here, we identify bottlenecks hindering the maturation of flexible sensors and propose promising solutions. We first analyze challenges in achieving satisfactory sensing performance for real-world applications and then summarize issues in compatible sensor-biology interfaces, followed by brief discussions on powering and connecting sensor networks. Issues en route to commercialization and for sustainable growth of the sector are also analyzed, highlighting environmental concerns and emphasizing nontechnical issues such as business, regulatory, and ethical considerations. Additionally, we look at future intelligent flexible sensors. In proposing a comprehensive roadmap, we hope to steer research efforts towards common goals and to guide coordinated development strategies from disparate communities. Through such collaborative efforts, scientific breakthroughs can be made sooner and capitalized for the betterment of humanity.

Recent progress in bio-voltage memristors working with ultralow voltage of biological amplitude

Neuromorphic systems built from memristors that emulate bioelectrical information processing in the brain may overcome the limitations of traditional computing architectures. However, functional emulation alone may still not attain all the merits of bio-computation, which uses action potentials of 50-120 mV at least 10 times lower than signal amplitude in conventional electronics to achieve extraordinary power efficiency and effective functional integration. Reducing the functional voltage in memristors to this biological amplitude can thus advance neuromorphic engineering and bio-emulated integration. This review aims to provide a timely update on the effort and progress in this burgeoning research direction, covering the aspects of device material composition, performance, working mechanism, and potential application.

A review of memristor: material and structure design, device performance, applications and prospects

With the booming growth of artificial intelligence (AI), the traditional von Neumann computing architecture based on complementary metal oxide semiconductor devices are facing memory wall and power wall. Memristor based in-memory computing can potentially overcome the current bottleneck of computer and achieve hardware breakthrough. In this review, the recent progress of memory devices in material and structure design, device performance and applications are summarized. Various resistive switching materials, including electrodes, binary oxides, perovskites, organics, and two-dimensional materials, are presented and their role in the memristor are discussed. Subsequently, the construction of shaped electrodes, the design of functional layer and other factors influencing the device performance are analyzed. We focus on the modulation of the resistances and the effective methods to enhance the performance. Furthermore, synaptic plasticity, optical-electrical properties, the fashionable applications in logic operation and analog calculation are introduced. Finally, some critical issues such as the resistive switching mechanism, multi-sensory fusion, system-level optimization are discussed.

An Effective Sneak-Path Solution Based on a Transient-Relaxation Device

An efficient strategy for addressing individual devices is required to unveil the full potential of memristors for high-density memory and computing applications. Existing strategies using two-terminal selectors that are preferable for compact integration have trade-offs in reduced generality or functional window. A strategy that applies to broad memristors and maintains their full-range functional window is proposed. This strategy uses a type of unipolar switch featuring a transient relaxation or retention as the selector. The unidirectional current flow in the switch suppresses the sneak-path current, whereas the transient-relaxation window is exploited for bidirectional programming. A unipolar volatile memristor with ultralow switching voltage (e.g., <100 mV), constructed from a protein nanowire dielectric harvested from Geobacter sulfurreducens, is specifically employed as the example switch to highlight the advantages and scalability in the strategy for array integration.