Scalable integration of hybrid high-κ dielectric materials on two-dimensional semiconductors

Ultraflat single-crystal hexagonal boron nitride for wafer-scale integration of a 2D-compatible high-κ metal gate

Hexagonal boron nitride (hBN) has emerged as a promising protection layer for dielectric integration in the next-generation large-scale integrated electronics. Although numerous efforts have been devoted to growing single-crystal hBN film, wafer-scale ultraflat hBN has still not been achieved. Here, we report the epitaxial growth of 4 in. ultraflat single-crystal hBN on Cu0.8Ni0.2(111)/sapphire wafers. The strong coupling between hBN and Cu0.8Ni0.2(111) suppresses the formation of wrinkles and ensures the seamless stitching of parallelly aligned hBN domains, resulting in an ultraflat single-crystal hBN film on a wafer scale. Using the ultraflat hBN as a protective layer, we integrate the wafer-scale ultrathin high-κ dielectrics onto two-dimensional (2D) materials with a damage-free interface. The obtained hBN/HfO2 composite dielectric exhibits an ultralow current leakage (2.36 × 10-6 A cm-2) and an ultrathin equivalent oxide thickness of 0.52 nm, which meets the targets of the International Roadmap for Devices and Systems. Our findings pave the way to the synthesis of ultraflat 2D materials and integration of future 2D electronics.

Morphological Evolution of Atomic Layer Deposited Hafnium Oxide on Aligned Carbon Nanotube Arrays

Microscopic study of the nucleation and growth of atomic layer deposition (ALD) dielectrics onto carbon nanotubes (CNTs) is an essential while challenging task toward high-performance devices. Here, we capture the morphological evolution and growth behaviors of ALD-HfO2 onto SiO2/Si-supported aligned CNT arrays (A-CNTs) under three ALD recipes via cross-sectional high-resolution scanning transmission electron microscopy. The HfO2 in ALD I (200 °C) preferentially nucleates on the SiO2 substrate in heterogeneous growth mode, resulting in films with considerable pinholes, while ALD II (90 °C) and III (90 °C and extra H2O presoak) exhibit homogeneous growth with nucleation on both SiO2 and CNTs, yielding uniform films. Arrangement defects in A-CNTs exacerbate nonuniformity of HfO2 and tube-tube separation plays deterministic roles affecting the HfO2-CNT interfacial morphology. Electrical measurements from A-CNTs metaloxide-semiconductor devices validate these findings. Our investigation contributes valuable insights for optimizing ALD processes for enhanced dielectric integration on A-CNTs in next-generation electronics.

Ultra-High-k Ferroelectric BaTiO3 Perovskite in the Gate Stack for Two-Dimensional WSe2 p-Type High-Performance Transistors

The experimental demonstration of a p-type 2D WSe2 transistor with a ferroelectric perovskite BaTiO3 gate oxide is presented. The 30 nm thick BaTiO3 gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm2 and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe2/BaTiO3 stack due to its high dielectric constant of 323. We demonstrate one of the best ON currents for perovskite gate 2D transistors in the literature. This is enabled by high-quality epitaxial growth of BaTiO3 and a single 2D layer transfer based fabrication method that is shown to be amenable to silicon platforms. This demonstration is an important milestone toward the integration of crystalline complex oxides with 2D channel materials for scaled CMOS and low-voltage ferroelectric logic applications.

Comprehensive Insights on MXene-Based TENGs: from Structures, Functions to Applications

The rapid advancement of triboelectric nanogenerators (TENGs) has introduced a transformative approach to energy harvesting and self-powered sensing in recent years. Nonetheless, the untapped potential of TENGs in practical scenarios necessitates multiple strategies like material selections and structure designs to enhance their output performance. Given the various superior properties, MXenes, a kind of novel 2D materials, have demonstrated great promise in enhancing TENG functionality. Here, this review comprehensively delineates the advantages of incorporating MXenes into TENGs, majoring in six pivotal aspects. First, an overview of TENGs is provided, stating their theoretical foundations, working modes, material considerations, and prevailing challenges. Additionally, the structural characteristics, fabrication methodologies, and family of MXenes, charting their developmental trajectory are highlighted. The selection of MXenes as various functional layers (negative and positive triboelectric layer, electrode layer) while designing TENGs is briefed. Furthermore, the distinctive advantages of MXene-based TENGs and their applications are emphasized. Last, the existing challenges are highlighted, and the future developing directions of MXene-based TENGs are forecasted.

Low-Symmetry 2D t-InTe for Polarization-Sensitive UV-Vis-NIR Photodetection

Polarization-sensitive photodetection grounded on low-symmetry 2D materials has immense potential in improving detection accuracy, realizing intelligent detection, and enabling multidimensional visual perception, which has promising application prospects in bio-identification, optical communications, near-infrared imaging, radar, military, and security. However, the majority of the reported polarized photodetection are limited by UV-vis response range and low anisotropic photoresponsivity factor, limiting the achievement of high-performance anisotropic photodetection. Herein, 2D t-InTe crystal is introduced into anisotropic systems and developed to realize broadband-response and high-anisotropy-ratio polarized photodetection. Stemming from its narrow band gap and intrinsic low-symmetry lattice characteristic, 2D t-InTe-based photodetector exhibits a UV-vis-NIR broadband photoresponse and significant photoresponsivity anisotropy behavior, with an exceptional in-plane anisotropic factor of 1.81@808 nm laser, surpassing the performance of most reported 2D counterparts. This work expounds the anisotropic structure-activity relationship of 2D t-InTe crystal, and identifies 2D t-InTe as a prospective candidate for high-performance polarization-sensitive optoelectronics, laying the foundation for future multifunctional device applications.

Low-Symmetry Van der Waals Dielectric GaInS3 Triggered 2D MoS2 Giant Anisotropy via Symmetry Engineering

Low-symmetry structures in van der Waals materials have facilitated the advancement of anisotropic electronic and optoelectronic devices. However, the intrinsic low symmetry structure exhibits a small adjustable anisotropy ratio (1-10), which hinders its further assembly and processing into high-performance devices. Here, a novel 2D anisotropic dielectric, GaInS3 (GIS), which induces isotropic MoS2 to exhibit significant anisotropic optical and electrical responses is demonstrated. With the excellent gate modulation ability of 2D GIS (dielectric constant k ∼12), MoS2 field effect transistor (FET) shows an adjustable conductance ratio from isotropic to anisotropic under dual-gate modulation, up to 106. Theoretical calculations indicate that anisotropy originates from lattice mismatch-induced charge density deformation at the interface. Moreover, the MoS2/GIS photodetector demonstrates high responsivity (≈4750 A W-1) and a large dichroic ratio (≈167). The anisotropic van der Waals dielectric GIS paves the way for the development of 2D transition metal dichalcogenides (TMDCs) in the fields of anisotropic photonics, electronics, and optoelectronics.

Large-Area Epitaxial Growth of Transition Metal Dichalcogenides

Over the past decade, research on atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) has expanded rapidly due to their unique properties such as high carrier mobility, significant excitonic effects, and strong spin-orbit couplings. Considerable attention from both scientific and industrial communities has fully fueled the exploration of TMDs toward practical applications. Proposed scenarios, such as ultrascaled transistors, on-chip photonics, flexible optoelectronics, and efficient electrocatalysis, critically depend on the scalable production of large-area TMD films. Correspondingly, substantial efforts have been devoted to refining the synthesizing methodology of 2D TMDs, which brought the field to a stage that necessitates a comprehensive summary. In this Review, we give a systematic overview of the basic designs and significant advancements in large-area epitaxial growth of TMDs. We first sketch out their fundamental structures and diverse properties. Subsequent discussion encompasses the state-of-the-art wafer-scale production designs, single-crystal epitaxial strategies, and techniques for structure modification and postprocessing. Additionally, we highlight the future directions for application-driven material fabrication and persistent challenges, aiming to inspire ongoing exploration along a revolution in the modern semiconductor industry.

Synthesis, Modulation, and Application of Two-Dimensional TMD Heterostructures

Two-dimensional (2D) transition metal dichalcogenide (TMD) heterostructures have attracted a lot of attention due to their rich material diversity and stack geometry, precise controllability of structure and properties, and potential practical applications. These heterostructures not only overcome the inherent limitations of individual materials but also enable the realization of new properties through appropriate combinations, establishing a platform to explore new physical and chemical properties at micro-nano-pico scales. In this review, we systematically summarize the latest research progress in the synthesis, modulation, and application of 2D TMD heterostructures. We first introduce the latest techniques for fabricating 2D TMD heterostructures, examining the rationale, mechanisms, advantages, and disadvantages of each strategy. Furthermore, we emphasize the importance of characteristic modulation in 2D TMD heterostructures and discuss some approaches to achieve novel functionalities. Then, we summarize the representative applications of 2D TMD heterostructures. Finally, we highlight the challenges and future perspectives in the synthesis and device fabrication of 2D TMD heterostructures and provide some feasible solutions.

Two-Dimensional Semiconductors for State-of-the-Art Complementary Field-Effect Transistors and Integrated Circuits

As the trajectory of transistor scaling defined by Moore's law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities.

Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlOx/Al2O3 and a double-gate structure employing high-k dielectric HfO2. Due to the superior subthreshold characteristics, monolayer WS2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage (VDD) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm-1 at VDD = 1 V. In addition, the monolayer WS2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS2 for high-gain and low-power logic circuits and validate the practical application in large areas.

Atomic Precision Processing of Two-Dimensional Materials for Next-Generation Microelectronics

The growth of the information era economy is driving the pursuit of advanced materials for microelectronics, spurred by exploration into "Beyond CMOS" and "More than Moore" paradigms. Atomically thin 2D materials, such as transition metal dichalcogenides (TMDCs), show great potential for next-generation microelectronics due to their properties and defect engineering capabilities. This perspective delves into atomic precision processing (APP) techniques like atomic layer deposition (ALD), epitaxy, atomic layer etching (ALE), and atomic precision advanced manufacturing (APAM) for the fabrication and modification of 2D materials, essential for future semiconductor devices. Additive APP methods like ALD and epitaxy provide precise control over composition, crystallinity, and thickness at the atomic scale, facilitating high-performance device integration. Subtractive APP techniques, such as ALE, focus on atomic-scale etching control for 2D material functionality and manufacturing. In APAM, modification techniques aim at atomic-scale defect control, offering tailored device functions and improved performance. Achieving optimal performance and energy efficiency in 2D material-based microelectronics requires a comprehensive approach encompassing fundamental understanding, process modeling, and high-throughput metrology. The outlook for APP in 2D materials is promising, with ongoing developments poised to impact manufacturing and fundamental materials science. Integration with advanced metrology and codesign frameworks will accelerate the realization of next-generation microelectronics enabled by 2D materials.

Quantifying Structural Polarization by Continuous Regulation of Lone-Pair Electron Expression in Molecular Crystals

Rational design of structural polarization is vital for modern technologies, as it allows the physical properties of functional materials to be tailored. An effective approach for governing polarization involves the utilization of stereochemical lone-pair electrons (LPEs). However, despite the recognized significance of LPEs in controlling structural polarization, there remains a lack of understanding regarding the quantitative relationship between their expression and the extent of structural polarization. Here, by using pressure to continuously tune the LPE expression, we achieve the precise control and quantification of structural polarization, which brings enhanced second harmonic generation (SHG) of the molecular crystal SbI3·3S8. We introduce the I-Sb-I angle (α̅) that describes the degree of LPE expression and establishes a quantitative relationship between α̅ and structural polarization. That is, decreasing α̅ shapes LPE expression from delocalization to localization, which repels the bonding pairs of electrons and thus enhances the structural polarization. In addition, we extend this quantified relationship to a series of molecular crystals and demonstrate its applicability to the design of structural polarization by tailoring LPE expression.

Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor

Two-dimensional (2D) transition metal dichalcogenides (TMDs) allow for atomic-scale manipulation, challenging the conventional limitations of semiconductor materials. This capability may overcome the short-channel effect, sparking significant advancements in electronic devices that utilize 2D TMDs. Exploring the dimension and performance limits of transistors based on 2D TMDs has gained substantial importance. This review provides a comprehensive investigation into these limits of the single 2D-TMD transistor. It delves into the impacts of miniaturization, including the reduction of channel length, gate length, source/drain contact length, and dielectric thickness on transistor operation and performance. In addition, this review provides a detailed analysis of performance parameters such as source/drain contact resistance, subthreshold swing, hysteresis loop, carrier mobility, on/off ratio, and the development of p-type and single logic transistors. This review details the two logical expressions of the single 2D-TMD logic transistor, including current and voltage. It also emphasizes the role of 2D TMD-based transistors as memory devices, focusing on enhancing memory operation speed, endurance, data retention, and extinction ratio, as well as reducing energy consumption in memory devices functioning as artificial synapses. This review demonstrates the two calculating methods for dynamic energy consumption of 2D synaptic devices. This review not only summarizes the current state of the art in this field but also highlights potential future research directions and applications. It underscores the anticipated challenges, opportunities, and potential solutions in navigating the dimension and performance boundaries of 2D transistors.

Interface States in Gate Stack of Carbon Nanotube Array Transistors

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/μm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Epitaxial Integration of Transferable High-κ Dielectric and 2D Semiconductor

The synthesis of high-dielectric-constant (high-κ) dielectric materials and their integration with channel materials have been the key challenges in the state-of-the-art transistor architecture, as they can provide strong gate control and low operating voltage. For next-generation electronics, high-mobility two-dimensional (2D) layered semiconductors with dangling-bond-free surfaces and an atomic-thick thickness are being explored as channel materials to achieve shorter channel lengths and less interfacial scattering. Nowadays, the integration of high-κ dielectrics with high-mobility 2D semiconductors mainly relies on atomic layer deposition or transfer stacking, which may cause several undesirable problems, such as channel damage and interface traps. Here, we demonstrate the integration of high-mobility 2D semiconducting Bi2O2Se with transferable high-κ SrTiO3 as a 2D field-effect transistor by direct epitaxial growth. Remarkably, such 2D heterostructures can be efficiently transferred from the water-soluble Sr3Al2O6 sacrificial layer onto arbitrary substrates. The as-fabricated 2D Bi2O2Se/SrTiO3 transistors exhibit an on/off ratio over 104 and a subthreshold swing down to 90 mV/dec. Furthermore, the 2D Bi2O2Se/SrTiO3 heterostructures can be easily transferred onto flexible polyethylene terephthalate (PET) substrates, and the as-fabricated transistors exhibit good potential in flexible electronics. Our study opens up a new avenue for the integration of high-κ dielectrics with high-mobility 2D semiconductors and paves the way for the exploration of multifunctional electronic devices.

Mixed-Dimensional Integration of 3D-on-2D Heterostructures for Advanced Electronics

Two-dimensional (2D) materials have garnered significant attention due to their exceptional properties requisite for next-generation electronics, including ultrahigh carrier mobility, superior mechanical flexibility, and unusual optical characteristics. Despite their great potential, one of the major technical difficulties toward lab-to-fab transition exists in the seamless integration of 2D materials with classic material systems, typically composed of three-dimensional (3D) materials. Owing to the self-passivated nature of 2D surfaces, it is particularly challenging to achieve well-defined interfaces when forming 3D materials on 2D materials (3D-on-2D) heterostructures. Here, we comprehensively review recent progress in 3D-on-2D incorporation strategies, ranging from direct-growth- to layer-transfer-based approaches and from non-epitaxial to epitaxial integration methods. Their technological advances and obstacles are rigorously discussed to explore optimal, yet viable, integration strategies of 3D-on-2D heterostructures. We conclude with an outlook on mixed-dimensional integration processes, identifying key challenges in state-of-the-art technology and suggesting potential opportunities for future innovation.

Discovery and Manipulation of van der Waals Polarons in Sb2O3 Ultrathin Molecular Crystal

Manipulating single electrons at the atomic scale is vital for mastering complex surface processes governed by the transfer of individual electrons. Polarons, composed of electrons stabilized by electron-phonon coupling, offer a pivotal medium for such manipulation. Here, using scanning tunneling microscopy and spectroscopy (STM/STS) and density functional theory (DFT) calculations, we report the identification and manipulation of a new type of polaron, dubbed van der Waals (vdW) polaron, within mono- to trilayer ultrathin films composed of Sb2O3 molecules that are bonded via vdW attractions. The Sb2O3 films were grown on a graphene-covered SiC(0001) substrate via molecular beam epitaxy. Unlike prior molecular polarons, STM imaging observed polarons at the interstitial sites of the molecular film, presenting unique electronic states and localized band bending. DFT calculations revealed the lowest conduction band as an intermolecular bonding state, capable of ensnaring an extra electron through locally diminished intermolecular distances, thereby forming an intermolecular vdW polaron. We also demonstrated the ability to generate, move, and erase such vdW polarons using an STM tip. Our work uncovers a new type of polaron stabilized by coupling with intermolecular vibrations where vdW interactions dominate, paving the way for designing atomic-scale electron transfer processes and enabling precise tailoring of electron-related properties and functionalities.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60 mV dec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

The future of two-dimensional semiconductors beyond Moore's law

The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.

Van der Waals Epitaxially Grown Molecular Crystal Dielectric Sb2O3 for 2D Electronics

Two-dimensional (2D) semiconducting materials have attracted significant interest as promising candidates for channel materials owing to their high mobility and gate tunability at atomic-layer thickness. However, the development of 2D electronics is impeded due to the difficulty in formation of high-quality dielectrics with a clean and nondestructive interface. Here, we report the direct van der Waals epitaxial growth of a molecular crystal dielectric, Sb2O3, on 2D materials by physical vapor deposition. The grown Sb2O3 nanosheets showed epitaxial relations of 0 and 180° with the 2D template, maintaining high crystallinity and an ultrasharp vdW interface with the 2D materials. As a result, the Sb2O3 nanosheets exhibited a high breakdown field of 18.6 MV/cm for 2L Sb2O3 with a thickness of 1.3 nm and a very low leakage current of 2.47 × 10-7 A/cm2 for 3L Sb2O3 with a thickness of 1.96 nm. We also observed two types of grain boundaries (GBs) with misorientation angles of 0 and 60°. The 0°-GB with a well-stitched boundary showed higher electrical and thermal stabilities than those of the 60°-GB with a disordered boundary. Our work demonstrates a method to epitaxially grow molecular crystal dielectrics on 2D materials without causing any damage, a requirement for high-performance 2D electronics.

Solution-Processable and Printable Two-Dimensional Transition Metal Dichalcogenide Inks

Two-dimensional (2D) transition metal dichalcogenides (TMDs) with layered crystal structures have been attracting enormous research interest for their atomic thickness, mechanical flexibility, and excellent electronic/optoelectronic properties for applications in diverse technological areas. Solution-processable 2D TMD inks are promising for large-scale production of functional thin films at an affordable cost, using high-throughput solution-based processing techniques such as printing and roll-to-roll fabrications. This paper provides a comprehensive review of the chemical synthesis of solution-processable and printable 2D TMD ink materials and the subsequent assembly into thin films for diverse applications. We start with the chemical principles and protocols of various synthesis methods for 2D TMD nanosheet crystals in the solution phase. The solution-based techniques for depositing ink materials into solid-state thin films are discussed. Then, we review the applications of these solution-processable thin films in diverse technological areas including electronics, optoelectronics, and others. To conclude, a summary of the key scientific/technical challenges and future research opportunities of solution-processable TMD inks is provided.

J-MISFET Hybrid Dual-Gate Switching Device for Multifunctional Optoelectronic Logic Gate Applications

High-performance and low operating voltage are becoming increasingly significant device parameters to meet the needs of future integrated circuit (IC) processors and ensure their energy-efficient use in upcoming mobile devices. In this study, we suggest a hybrid dual-gate switching device consisting of the vertically stacked junction and metal-insulator-semiconductor (MIS) gate structure, named J-MISFET. It shows excellent device performances of low operating voltage (<0.5 V), drain current ON/OFF ratio (∼4.7 × 105), negligible hysteresis window (<0.5 mV), and near-ideal subthreshold slope (SS) (60 mV/dec), making it suitable for low-power switching operation. Furthermore, we investigated the switchable NAND/NOR logic gate operations and the photoresponse characteristics of the J-MISFET under the small supply voltage (0.5 V). To advance the applications further, we successfully demonstrated an integrated optoelectronic security logic system comprising 2-electric inputs (for encrypted data) and 1-photonic input signal (for password key) as a hardware security device for data protection. Thus, we believe that our J-MISFET, with its heterogeneous hybrid gate structures, will illuminate the path toward future device configurations for next-generation low-power electronics and multifunctional security logic systems in a data-driven society.

Can 2D Semiconductors Be Game-Changers for Nanoelectronics and Photonics?

2D semiconductors have interesting physical and chemical attributes that have led them to become one of the most intensely investigated semiconductor families in recent history. They may play a crucial role in the next technological revolution in electronics as well as optoelectronics or photonics. In this Perspective, we explore the fundamental principles and significant advancements in electronic and photonic devices comprising 2D semiconductors. We focus on strategies aimed at enhancing the performance of conventional devices and exploiting important properties of 2D semiconductors that allow fundamentally interesting device functionalities for future applications. Approaches for the realization of emerging logic transistors and memory devices as well as photovoltaics, photodetectors, electro-optical modulators, and nonlinear optics based on 2D semiconductors are discussed. We also provide a forward-looking perspective on critical remaining challenges and opportunities for basic science and technology level applications of 2D semiconductors.

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Silicon transistors are approaching their physical limit, calling for the emergence of a technological revolution. As the acknowledged ultimate version of transistor channels, 2D semiconductors are of interest for the development of post-Moore electronics due to their useful properties and all-in-one potentials. Here, the promise and current status of 2D semiconductors and transistors are reviewed, from materials and devices to integrated applications. First, we outline the evolution and challenges of silicon-based integrated circuits, followed by a detailed discussion on the properties and preparation strategies of 2D semiconductors and van der Waals heterostructures. Subsequently, the significant progress of 2D transistors, including device optimization, large-scale integration, and unconventional devices, are presented. We also examine 2D semiconductors for advanced heterogeneous and multifunctional integration beyond CMOS. Finally, the key technical challenges and potential strategies for 2D transistors and integrated circuits are also discussed. We envision that the field of 2D semiconductors and transistors could yield substantial progress in the upcoming years and hope this review will trigger the interest of scientists planning their next experiment.

Emerging van der Waals Dielectrics of Inorganic Molecular Crystals for 2D Electronics

In the landscape of continuous downscaling metal-oxide-semiconductor field-effect transistors, two-dimensional (2D) semiconductors with atomic thinness emerge as promising channel materials for ultimate scaled devices. However, integrating compatible dielectrics with 2D semiconductors, particularly in a scalable way, remains a critical challenge that hinders the development of 2D devices. Recently, 2D inorganic molecular crystals (IMCs), which are free of dangling bonds and possess excellent dielectric properties and simplicity for scalable fabrication, have emerged as alternatives for gate dielectric integration in 2D devices. In this Perspective, we start with the introduction of structure and synthesis methods of IMCs and then discuss the explorations of using IMCs as the dielectrics, as well as some remaining relevant issues to be unraveled. Moreover, we look at the future opportunities of IMC dielectrics in 2D devices both for practical applications and fundamental research.

What Makes On-Chip Microdevices Stand Out in Electrocatalysis?

Clean and sustainable energy conversion and storage through electrochemistry shows great promise as an alternative to traditional fuel or fossil-consumption energy systems. With regards to practical and high-efficient electrochemistry application, the rational design of active sites and the accurate description of mechanism remain a challenge. Toward this end, in this Perspective, a unique on-chip micro/nano device coupling nanofabrication and low-dimensional electrochemical materials is presented, in which material structure analysis, field-effect regulation, in situ monitoring, and simulation modeling are highlighted. The critical mechanisms that influence electrochemical response are discussed, and how on-chip micro/nano device distinguishes itself is emphasized. The key challenges and opportunities of on-chip electrochemical platforms are also provided through the Perspective.

Enhancement of Carrier Mobility in Multilayer InSe Transistors by van der Waals Integration

Two-dimensional material indium selenide (InSe) holds great promise for applications in electronics and optoelectronics by virtue of its fascinating properties. However, most multilayer InSe-based transistors suffer from extrinsic scattering effects from interface disorders and the environment, which cause carrier mobility and density fluctuations and hinder their practical application. In this work, we employ the non-destructive method of van der Waals (vdW) integration to improve the electron mobility of back-gated multilayer InSe FETs. After introducing the hexagonal boron nitride (h-BN) as both an encapsulation layer and back-gate dielectric with the vdW interface, as well as graphene serving as a buffer contact layer, the electron mobilities of InSe FETs are substantially enhanced. The vdW-integrated devices exhibit a high electron mobility exceeding 103 cm2 V-1 s-1 and current on/off ratios of ~108 at room temperature. Meanwhile, the electron densities are found to exceed 1012 cm-2. In addition, the fabricated devices show an excellent stability with a negligible electrical degradation after storage in ambient conditions for one month. Electrical transport measurements on InSe FETs in different configurations suggest that a performance enhancement with vdW integration should arise from a sufficient screening effect on the interface impurities and an effective passivation of the air-sensitive surface.