Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning

Mitigation of Device Heterogeneity in Graphene Hall Sensor Arrays Using Per-Element Backgate Tuning

Graphene Hall-effect magnetic field sensors (GHSs) exhibit high performance comparable to state-of-the-art commercial Hall sensors made from III-V semiconductors. Graphene is also amenable to CMOS-compatible fabrication processes, making GHSs attractive candidates for implementing magnetic sensor arrays for imaging fields in biosensing and scanning probe applications. However, their practical appeal is limited by response heterogeneity and drift, arising from the high sensitivity of two-dimensional (2D) materials to local device imperfections. To address this challenge, we designed a GHS array in which an individual backgate is added to each GHS, allowing the carrier density of each sensor to be electrostatically tuned independent of other sensors in the array. Compared to the constraints encountered when all devices are tuned with the same backgate, we expected that the flexibility afforded by individual tuning would allow for the array's sensitivity, uniformity, and reconfigurability to be enhanced. We fabricated an array of 16 GHSs, each with its own backgate terminal, and characterized the ability to modulate GHS carrier density and Hall sensitivity within CMOS-compatible voltage ranges. We then demonstrated that individual device tuning can be used to break the trade-off between device sensitivity and uniformity in the GHS array, allowing for enhancement of both objectives. Our results showed that GHS arrays exhibiting >30% variability under single-backgate operation could be compensated using individual tuning to achieve <2% variability with minimal impact on the array sensitivity.

Thermal Dehydrogenation Impact on Positive Bias Stability of Amorphous InSnZnO Thin-Film Transistors

Recently, the growing demand for amorphous oxide semiconductor thin-film transistors (AOS TFTs) with high mobility and good stability to implement ultrahigh-resolution displays has made tracking the role of hydrogen in oxide semiconductor films increasingly important. Hydrogen is an essential element that contributes significantly to the field effect mobility and bias stability characteristics of AOS TFTs. However, because hydrogen is the lightest atom and has high reactivity to metal and oxide materials, elucidating its impact on AOS thin films has been challenging. Therefore, in this study, we propose controlling the hydrogen quantities in amorphous InSnZnO (a-ITZO) thin films through thermal dehydrogenation to precisely reveal the hydrogen influences on the electrical characteristics of a-ITZO TFTs. The as-deposited device containing 15.69 × 1015 atoms/cm2 of hydrogen exhibited a relatively low saturation mobility of 18.1 cm2/V·s and poor positive bias stress stability. However, depending on the extent of thermal dehydrogenation, not only did the hydrogen quantity and interface defect density (DIT) decrease but also the conductivity and surface energy increased due to the rise in oxygen vacancies and hydroxyl groups in a-ITZO thin films. As a result, the a-ITZO TFT with a hydrogen amount of 4.828 × 1015 atoms/cm2 showed that the saturation mobility improved up to 36.8 cm2/V·s, and positive bias stress stability was remarkably enhanced. Hence, we report the ability to manage the hydrogen quantity with thermal dehydrogenation and demonstrate that high-performance a-ITZO TFTs can be realized when an appropriate hydrogen concentration is achieved.

Strong doping reduction on wafer-scale CVD graphene devices via Al2O3ALD encapsulation

We present the electrical characterization of wafer-scale graphene devices fabricated with an industrially-relevant, contact-first integration scheme combined with Al2O3encapsulation via atomic layer deposition. All the devices show a statistically significant reduction in the Dirac point position,Vcnp, from around +47 V to between -5 and 5 V (on 285 nm SiO2), while maintaining the mobility values. The data and methods presented are relevant for further integration of graphene devices, specifically sensors, at the back-end-of-line of a standard CMOS flow.

The future of two-dimensional semiconductors beyond Moore's law

The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.

Ultrafast Laser Processing of 2D Materials: Novel Routes to Advanced Devices

Ultrafast laser processing has emerged as a versatile technique for modifying materials and introducing novel functionalities. Over the past decade, this method has demonstrated remarkable advantages in the manipulation of 2D layered materials, including synthesis, structuring, functionalization, and local patterning. Unlike continuous-wave and long-pulsed optical methods, ultrafast lasers offer a solution for thermal heating issues. Nonlinear interactions between ultrafast laser pulses and the atomic lattice of 2D materials substantially influence their chemical and physical properties. This paper highlights the transformative role of ultrafast laser pulses in maskless green technology, enabling subtractive, and additive processes that unveil ways for advanced devices. Utilizing the synergetic effect between the energy states within the atomic layers and ultrafast laser irradiation, it is feasible to achieve unprecedented resolutions down to several nanometers. Recent advancements are discussed in functionalization, doping, atomic reconstruction, phase transformation, and 2D and 3D micro- and nanopatterning. A forward-looking perspective on a wide array of applications of 2D materials, along with device fabrication featuring novel physical and chemical properties through direct ultrafast laser writing, is also provided.

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Silicon transistors are approaching their physical limit, calling for the emergence of a technological revolution. As the acknowledged ultimate version of transistor channels, 2D semiconductors are of interest for the development of post-Moore electronics due to their useful properties and all-in-one potentials. Here, the promise and current status of 2D semiconductors and transistors are reviewed, from materials and devices to integrated applications. First, we outline the evolution and challenges of silicon-based integrated circuits, followed by a detailed discussion on the properties and preparation strategies of 2D semiconductors and van der Waals heterostructures. Subsequently, the significant progress of 2D transistors, including device optimization, large-scale integration, and unconventional devices, are presented. We also examine 2D semiconductors for advanced heterogeneous and multifunctional integration beyond CMOS. Finally, the key technical challenges and potential strategies for 2D transistors and integrated circuits are also discussed. We envision that the field of 2D semiconductors and transistors could yield substantial progress in the upcoming years and hope this review will trigger the interest of scientists planning their next experiment.

Gap engineering effects on transport and tunneling magnetoresistance properties in phosphorene ferromagnetic/normal/ferromagnetic junction

Tuning the band gap is of utmost importance for the practicality of two-dimensional materials in the semiconductor industry. In this study, we investigate the ballistic transport and the tunneling magnetoresistance (TMR) properties within a modulated gap in a ferromagnetic/normal/ferromagnetic (F/N/F) phosphorene junction. The theoretical framework is established on a Dirac-like Hamiltonian, the transfer matrix method, and the Landauer-Büttiker formalism to characterize electron behavior and obtain transmittance, conductance and TMR. Our results reveal that a reduction in gap energy leads to an enhancement of conductance for both parallel and anti-parallel magnetization configurations. In contrast, a significant reduction and redshift in TMR have been observed. Notably, the application of an electrostatic field in a gapless phosphorene F/N/F junction induces a blueshift and a slight increase in TMR. Furthermore, we found that introducing an asymmetrically applied electrostatic field in this gapless junction results in a significant reduction and redshift in TMR. Additionally, intensifying the applied magnetic field leads to a substantial increase in TMR. These findings could be useful for designing and implementing practical applications that require precise control over the TMR properties of a phosphorene F/N/F junction with a modulated gap.

Probing charge traps at the 2D semiconductor/dielectric interface

The family of 2-dimensional (2D) semiconductors is a subject of intensive scientific research due to their potential in next-generation electronics. While offering many unique properties like atomic thickness and chemically inert surfaces, the integration of 2D semiconductors with conventional dielectric materials is challenging. The charge traps at the semiconductor/dielectric interface are among many issues to be addressed before these materials can be of industrial relevance. Conventional electrical characterization methods remain inadequate to quantify the traps at the 2D semiconductor/dielectric interface since the estimations of the density of interface traps, Dit, by different techniques may yield more than an order-of-magnitude discrepancy, even when extracted from the same device. Therefore, the challenge to quantify Dit at the 2D semiconductor/dielectric interface is about finding an accurate and reliable measurement method. In this review, we discuss characterization techniques which have been used to study the 2D semiconductor/dielectric interface. Specifically, we discuss the methods based on small-signal AC measurements, subthreshold slope measurements and low-frequency noise measurements. While these approaches were developed for silicon-based technology, 2D semiconductor devices possess a set of unique challenges requiring a careful re-evaluation when using these characterization techniques. We examine the conventional methods based on their efficacy and accuracy in differentiating various types of trap states and provide guidance to find an appropriate method for charge trap analysis and estimation of Dit at 2D semiconductor/dielectric interfaces.

Investigating charge traps in MoTe2field-effect transistors: SiO2insulator traps and MoTe2bulk traps

Two-dimensional material-based field-effect transistors are promising for future use in electronic and optoelectronic applications. However, trap states existing in the transistors are known to hinder device performance. They capture/release carriers in the channel and lead to hysteresis in the transfer characteristics. In this work, we fabricated MoTe2field-effect transistors on two different gate dielectrics, SiO2and h-BN, and investigated temperature-dependent charge trapping behavior on the hysteresis in their transfer curves. We observed that devices with SiO2back-gate dielectric are affected by both SiO2insulator traps and MoTe2intrinsic bulk traps, with the latter becoming prominent at temperatures above 310 K. Conversely, devices with h-BN back-gate dielectric, which host a negligible number of insulator traps, primarily exhibit MoTe2bulk traps at high temperatures, enabling us to estimate the trap energy level at 389 meV below the conduction band edge. A similar energy level of 396 meV below the conduction band edge was observed from the emission current transient measurement. From a previous computational study, we expect these trap states to be the tellurium vacancy. Our results suggest that charge traps in MoTe2field-effect transistors can be reduced by careful selection of gate insulators, thus providing guidelines for device fabrication.

Dielectrics for Two-Dimensional Transition-Metal Dichalcogenide Applications

Despite over a decade of intense research efforts, the full potential of two-dimensional transition-metal dichalcogenides continues to be limited by major challenges. The lack of compatible and scalable dielectric materials and integration techniques restrict device performances and their commercial applications. Conventional dielectric integration techniques for bulk semiconductors are difficult to adapt for atomically thin two-dimensional materials. This review provides a brief introduction into various common and emerging dielectric synthesis and integration techniques and discusses their applicability for 2D transition metal dichalcogenides. Dielectric integration for various applications is reviewed in subsequent sections including nanoelectronics, optoelectronics, flexible electronics, valleytronics, biosensing, quantum information processing, and quantum sensing. For each application, we introduce basic device working principles, discuss the specific dielectric requirements, review current progress, present key challenges, and offer insights into future prospects and opportunities.

2D fin field-effect transistors integrated with epitaxial high-k gate oxide

Precise integration of two-dimensional (2D) semiconductors and high-dielectric-constant (k) gate oxides into three-dimensional (3D) vertical-architecture arrays holds promise for developing ultrascaled transistors1-5, but has proved challenging. Here we report the epitaxial synthesis of vertically aligned arrays of 2D fin-oxide heterostructures, a new class of 3D architecture in which high-mobility 2D semiconductor fin Bi2O2Se and single-crystal high-k gate oxide Bi2SeO5 are epitaxially integrated. These 2D fin-oxide epitaxial heterostructures have atomically flat interfaces and ultrathin fin thickness down to one unit cell (1.2 nm), achieving wafer-scale, site-specific and high-density growth of mono-oriented arrays. The as-fabricated 2D fin field-effect transistors (FinFETs) based on Bi2O2Se/Bi2SeO5 epitaxial heterostructures exhibit high electron mobility (μ) up to 270 cm2 V-1 s-1, ultralow off-state current (IOFF) down to about 1 pA μm-1, high on/off current ratios (ION/IOFF) up to 108 and high on-state current (ION) up to 830 μA μm-1 at 400-nm channel length, which meet the low-power specifications projected by the International Roadmap for Devices and Systems (IRDS)6. The 2D fin-oxide epitaxial heterostructures open up new avenues for the further extension of Moore's law.

Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors

During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication technique or a technique which is compatible with CMOS due to the inherent low costs, scalability, and potential for mass production that this technology provides. While chemiresistive semiconductor metal oxide (SMO) gas sensors have been the principal semiconductor-based gas sensor technology investigated in the past, resulting in their eventual commercialization, they need high-temperature operation to provide sufficient energies for the surface chemical reactions essential for the molecular detection of gases in the ambient. Therefore, the integration of a microheater in a MEMS structure is a requirement, which can be quite complex. This is, therefore, undesirable and room temperature, or at least near-room temperature, solutions are readily being investigated and sought after. Room-temperature SMO operation has been achieved using UV illumination, but this further complicates CMOS integration. Recent studies suggest that two-dimensional (2D) materials may offer a solution to this problem since they have a high likelihood for integration with sophisticated CMOS fabrication while also providing a high sensitivity towards a plethora of gases of interest, even at room temperature. This review discusses many types of promising 2D materials which show high potential for integration as channel materials for digital logic field effect transistors (FETs) as well as chemiresistive and FET-based sensing films, due to the presence of a sufficiently wide band gap. This excludes graphene from this review, while recent achievements in gas sensing with graphene oxide, reduced graphene oxide, transition metal dichalcogenides (TMDs), phosphorene, and MXenes are examined.

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials

For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.