In situ training of feed-forward and recurrent convolutional memristor networks

Demonstration of In-Memory Biosignal Analysis: Novel High-Density and Low-Power 3D Flash Memory Array for Arrhythmia Detection

Smart healthcare systems integrated with advanced deep neural networks enable real-time health monitoring, early disease detection, and personalized treatment. In this work, a novel 3D AND-type flash memory array with a rounded double channel for computing-in-memory (CIM) architecture to overcome the limitations of conventional smart healthcare systems: the necessity of high area and energy efficiency while maintaining high classification accuracy is proposed. The fabricated array, characterized by low-power operations and high scalability with double independent channels per floor, exhibits enhanced cell density and energy efficiency while effectively emulating the features of biological synapses. The CIM architecture leveraging the fabricated array achieves high classification accuracy (93.5%) for electrocardiogram signals, ensuring timely detection of potentially life-threatening arrhythmias. Incorporated with a simplified spike-timing-dependent plasticity learning rule, the CIM architecture is suitable for robust, area- and energy-efficient in-memory arrhythmia detection systems. This work effectively addresses the challenges of conventional smart healthcare systems, paving the way for a more refined healthcare paradigm.

Predicting Blood Glucose Levels with Organic Neuromorphic Micro-Networks

Accurate glucose prediction is vital for diabetes management. Artificial intelligence and artificial neural networks (ANNs) are showing promising results for reliable glucose predictions, offering timely warnings for glucose fluctuations. The translation of these software-based ANNs into dedicated computing hardware opens a route toward automated insulin delivery systems ultimately enhancing the quality of life for diabetic patients. ANNs are transforming this field, potentially leading to implantable smart prediction devices and ultimately to a fully artificial pancreas. However, this transition presents several challenges, including the need for specialized, compact, lightweight, and low-power hardware. Organic polymer-based electronics are a promising solution as they have the ability to implement the behavior of neural networks, operate at low voltage, and possess key attributes like flexibility, stretchability, and biocompatibility. Here, the study focuses on implementing software-based neural networks for glucose prediction into hardware systems. How to minimize network requirements, downscale the architecture, and integrate the neural network with electrochemical neuromorphic organic devices, meeting the strict demands of smart implants for in-body computation of glucose prediction is investigated.

Memristor-Based Neuromorphic Chips

In the era of information, characterized by an exponential growth in data volume and an escalating level of data abstraction, there has been a substantial focus on brain-like chips, which are known for their robust processing power and energy-efficient operation. Memristors are widely acknowledged as the optimal electronic devices for the realization of neuromorphic computing, due to their innate ability to emulate the interconnection and information transfer processes witnessed among neurons. This review paper focuses on memristor-based neuromorphic chips, which provide an extensive description of the working principle and characteristic features of memristors, along with their applications in the realm of neuromorphic chips. Subsequently, a thorough discussion of the memristor array, which serves as the pivotal component of the neuromorphic chip, as well as an examination of the present mainstream neural networks, is delved. Furthermore, the design of the neuromorphic chip is categorized into three crucial sections, including synapse-neuron cores, networks on chip (NoC), and neural network design. Finally, the key performance metrics of the chip is highlighted, as well as the key metrics related to the memristor devices are employed to realize both the synaptic and neuronal components.

Nanofluidic memristor based on the elastic deformation of nanopores with nanoparticle adsorption

The memristor is the building block of neuromorphic computing. We report a new type of nanofluidic memristor based on the principle of elastic strain on polymer nanopores. With nanoparticles absorbed at the wall of a single conical polymer nanopore, we find a pinched hysteresis of the current within a scanning frequency range of 0.01-0.1 Hz, switching to a diode below 0.01 Hz and a resistor above 0.1 Hz. We attribute the current hysteresis to the elastic strain at the tip side of the nanopore, caused by electrical force on the particles adsorbed at the inner wall surface. Our simulation and analytical equations match well with experimental results, with a phase diagram for predicting the system transitions. We demonstrate the plasticity of our nanofluidic memristor to be similar to a biological synapse. Our findings pave a new way for ionic neuromorphic computing using nanofluidic memristors.

Pruning and quantization algorithm with applications in memristor-based convolutional neural network

The human brain's ultra-low power consumption and highly parallel computational capabilities can be accomplished by memristor-based convolutional neural networks. However, with the rapid development of memristor-based convolutional neural networks in various fields, more complex applications and heavier computations lead to the need for a large number of memristors, which makes power consumption increase significantly and the network model larger. To mitigate this problem, this paper proposes an SBT-memristor-based convolutional neural network architecture and a hybrid optimization method combining pruning and quantization. Firstly, SBT-memristor-based convolutional neural network is constructed by using the good thresholding property of the SBT memristor. The memristive in-memory computing unit, activation unit and max-pooling unit are designed. Then, the hybrid optimization method combining pruning and quantization is used to improve the SBT-memristor-based convolutional neural network architecture. This hybrid method can simplify the memristor-based neural network and represent the weights at the memristive synapses better. Finally, the results show that the SBT-memristor-based convolutional neural network reduces a large number of memristors, decreases the power consumption and compresses the network model at the expense of a little precision loss. The SBT-memristor-based convolutional neural network obtains faster recognition speed and lower power consumption in MNIST recognition. It provides new insights for the complex application of convolutional neural networks.

MARR-GAN: Memristive Attention Recurrent Residual Generative Adversarial Network for Raindrop Removal

Since machine learning techniques for raindrop removal have not been capable of completely removing raindrops and have failed to take into account the constraints of edge devices with limited resources, a novel software-hardware co-designed method with a memristor for raindrop removal, named memristive attention recurrent residual generative adversarial network (MARR-GAN), is introduced in this research. A novel raindrop-removal network is specifically designed based on attention gate connections and recurrent residual convolutional blocks. By replacing the basic convolution unit with recurrent residual convolution unit, improved capturing of the changes in raindrop appearance over time is achieved, while preserving the position and shape information in the image. Additionally, an attention gate is utilized instead of the original skip connection to enhance the overall structural understanding and local detail preservation, facilitating a more comprehensive removal of raindrops across various areas of the image. Furthermore, a hardware implementation scheme for MARR-GAN is presented in this paper, where deep learning algorithms are seamlessly integrated with neuro inspired computing chips, utilizing memristor crossbar arrays for accelerated real-time image-data processing. Compelling evidence of the efficacy and superiority of MARR-GAN in raindrop removal and image restoration is provided by the results of the empirical study.

Adapted MLP-Mixer network based on crossbar arrays of fast and multilevel switching (Co-Fe-B)x(LiNbO3)100-x nanocomposite memristors

MLP-Mixer based on multilayer perceptrons (MLPs) is a novel architecture of a neuromorphic computing system (NCS) introduced for image classification tasks without convolutional layers. Its software realization demonstrates high classification accuracy, although the number of trainable weights is relatively low. One more promising way of improving the NCS performance, especially in terms of power consumption, is its hardware realization using memristors. Therefore, in this work, we proposed an NCS with an adapted MLP-Mixer architecture and memristive weights. For this purpose, we used a passive crossbar array of (Co-Fe-B)x(LiNbO3)100-x memristors. Firstly, we studied the characteristics of such memristors, including their minimal resistive switching time, which was extrapolated to be in the picosecond range. Secondly, we created a fully hardware NCS with memristive weights that are capable of classification of simple 4-bit vectors. The system was shown to be robust to noise introduction in the input patterns. Finally, we used experimental memristive characteristics to simulate an adapted MLP-Mixer architecture that demonstrated a classification accuracy of (94.7 ± 0.3)% on the Modified National Institute of Standards and Technology (MNIST) dataset. The obtained results are the first steps toward the realization of memristive NCS with a promising MLP-Mixer architecture.

Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its estimated gradient. Additionally, we adopt a fixed kernel method, where inputs are sequentially applied to a crossbar array with a differential memristor pair scheme, reducing unused cell waste. The binary activation has robust characteristics against device state variations, and a neuron circuit is experimentally demonstrated on a customized breadboard. Thanks to the analogue switching characteristics of the memristor device, the accurate vector-matrix multiplication (VMM) operations can be experimentally demonstrated by combining sequential inputs and the weights obtained through tuning operations in the crossbar array. In addition, the feature images extracted by VMM during the hardware inference operations on 100 test samples are classified, and the classification performance by off-chip training is compared with the software results. Finally, inference results depending on the tolerance are statistically verified through several tuning cycles.

Purely self-rectifying memristor-based passive crossbar array for artificial neural network accelerators

Memristor-integrated passive crossbar arrays (CAs) could potentially accelerate neural network (NN) computations, but studies on these devices are limited to software-based simulations owing to their poor reliability. Herein, we propose a self-rectifying memristor-based 1 kb CA as a hardware accelerator for NN computations. We conducted fully hardware-based single-layer NN classification tasks involving the Modified National Institute of Standards and Technology database using the developed passive CA, and achieved 100% classification accuracy for 1500 test sets. We also investigated the influences of the defect-tolerance capability of the CA, impact of the conductance range of the integrated memristors, and presence or absence of selection functionality in the integrated memristors on the image classification tasks. We offer valuable insights into the behavior and performance of CA devices under various conditions and provide evidence of the practicality of memristor-integrated passive CAs as hardware accelerators for NN applications.

Bio-inspired synaptic behavior simulation in thin-film transistors based on molybdenum disulfide

Synaptic behavior simulation in transistors based on MoS2 has been reported. MoS2 was utilized as the active layer to prepare ambipolar thin-film transistors. The excitatory postsynaptic current phenomenon was simulated, observing a gradual voltage decay following the removal of applied pulses, ultimately resulting in a response current slightly higher than the initial current. Subsequently, ±5 V voltages were separately applied for ten consecutive pulse voltage tests, revealing short-term potentiation and short-term depression behaviors. After 92 consecutive positive pulses, the device current transitioned from an initial value of 0.14 to 28.3 mA. Similarly, following 88 consecutive negative pulses, the device current changed, indicating long-term potentiation and long-term depression behaviors. We also employed a pair of continuous triangular wave pulses to evaluate paired-pulse facilitation behavior, observing that the response current of the second stimulus pulse was ∼1.2× greater than that of the first stimulus pulse. The advantages and prospects of using MoS2 as a material for thin-film transistors were thoroughly displayed.

High-Performance Neuromorphic Computing and Logic Operation Based on a Self-Assembled Vertically Aligned Nanocomposite SrTiO3:MgO Film Memristor

Neuromorphic computing based on memristors capable of in-memory computing is promising to break the energy and efficiency bottleneck of well-known von Neumann architectures. However, unstable and nonlinear conductance updates compromise the recognition accuracy and block the integration of neural network hardware. To this end, we present a highly stable memristor with self-assembled vertically aligned nanocomposite (VAN) SrTiO3:MgO films that achieve excellent resistive switching with low set/reset voltage variability (4.7%/-5.6%) and highly linear conductivity variation (nonlinearity = 0.34) by spatially limiting the conductive channels at the vertical interfaces. Various synaptic behaviors are simulated by continuously modulating the conductance. Especially, convolutional image processing using diverse crossbar kernels is demonstrated, and the artificial neural network achieves an overwhelming recognition accuracy of up to 97.50% for handwritten digits. Even under the perturbation of Poisson noise (λ = 10), 6% Salt and Pepper noise, and 5% Gaussian noise, the high recognition accuracies are retained at 95.43%, 94.56%, and 95.97%, respectively. Importantly, the logic memory function is proven experimentally based on the nonvolatile properties. This work provides a material system and design idea to achieve high-performance neuromorphic computing and logic operation.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

In-Sensor Computing Realization Using Fully CMOS-Compatible TiN/HfOx-Based Neuristor Array

With the evolution of artificial intelligence, the explosive growth of data from sensory terminals gives rise to severe energy-efficiency bottleneck issues due to cumbersome data interactions among sensory, memory, and computing modules. Heterogeneous integration methods such as chiplet technology can significantly reduce unnecessary data movement; however, they fail to address the fundamental issue of the substantial time and energy overheads resulting from the physical separation of computing and sensory components. Brain-inspired in-sensor neuromorphic computing (ISNC) has plenty of room for such data-intensive applications. However, one key obstacle in developing ISNC systems is the lack of compatibility between material systems and manufacturing processes deployed in sensors and computing units. This study successfully addresses this challenge by implementing fully CMOS-compatible TiN/HfOx-based neuristor array. The developed ISNC system demonstrates several advantageous features, including multilevel analogue modulation, minimal dispersion, and no significant degradation in conductance (@125 °C). These characteristics enable stable and reproducible neuromorphic computing. Additionally, the device exhibits modulatable sensory and multi-store memory processes. Furthermore, the system achieves information recognition with a high accuracy rate of 93%, along with frequency selectivity and notable activity-dependent plasticity. This work provides a promising route to affordable and highly efficient sensory neuromorphic systems.

Open-loop analog programmable electrochemical memory array

Emerging memories have been developed as new physical infrastructures for hosting neural networks owing to their low-power analog computing characteristics. However, accurately and efficiently programming devices in an analog-valued array is still largely limited by the intrinsic physical non-idealities of the devices, thus hampering their applications in in-situ training of neural networks. Here, we demonstrate a passive electrochemical memory (ECRAM) array with many important characteristics necessary for accurate analog programming. Different image patterns can be open-loop and serially programmed into our ECRAM array, achieving high programming accuracies without any feedback adjustments. The excellent open-loop analog programmability has led us to in-situ train a bilayer neural network and reached software-like classification accuracy of 99.4% to detect poisonous mushrooms. The training capability is further studied in simulation for large-scale neural networks such as VGG-8. Our results present a new solution for implementing learning functions in an artificial intelligence hardware using emerging memories.

Generative complex networks within a dynamic memristor with intrinsic variability

Artificial neural networks (ANNs) have gained considerable momentum in the past decade. Although at first the main task of the ANN paradigm was to tune the connection weights in fixed-architecture networks, there has recently been growing interest in evolving network architectures toward the goal of creating artificial general intelligence. Lagging behind this trend, current ANN hardware struggles for a balance between flexibility and efficiency but cannot achieve both. Here, we report on a novel approach for the on-demand generation of complex networks within a single memristor where multiple virtual nodes are created by time multiplexing and the non-trivial topological features, such as small-worldness, are generated by exploiting device dynamics with intrinsic cycle-to-cycle variability. When used for reservoir computing, memristive complex networks can achieve a noticeable increase in memory capacity a and respectable performance boost compared to conventional reservoirs trivially implemented as fully connected networks. This work expands the functionality of memristors for ANN computing.

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

Neuromorphic computing (NC) architecture inspired by biological nervous systems has been actively studied to overcome the limitations of conventional von Neumann architectures. In this work, we propose a reconfigurable NC block using a flash-type synapse array, emerging positive feedback (PF) neuron devices, and CMOS peripheral circuits, and integrate them on the same substrate to experimentally demonstrate the operations of the proposed NC block. Conductance modulation in the flash memory enables the NC block to be easily calibrated for output signals. In addition, the proposed NC block uses a reduced number of devices for analog-to-digital conversions due to the super-steep switching characteristics of the PF neuron device, substantially reducing the area overhead of NC block. Our NC block shows high energy efficiency (37.9 TOPS/W) with high accuracy for CIFAR-10 image classification (91.80%), outperforming prior works. This work shows the high engineering potential of integrating synapses and neurons in terms of system efficiency and high performance.

Simulation of a Fully Digital Computing-in-Memory for Non-Volatile Memory for Artificial Intelligence Edge Applications

In recent years, digital computing in memory (CIM) has been an efficient and high-performance solution in artificial intelligence (AI) edge inference. Nevertheless, digital CIM based on non-volatile memory (NVM) is less discussed for the sophisticated intrinsic physical and electrical behavior of non-volatile devices. In this paper, we propose a fully digital non-volatile CIM (DNV-CIM) macro with compressed coding look-up table (LUT) multiplier (CCLUTM) using the 40 nm technology, which is highly compatible with the standard commodity NOR Flash memory. We also provide a continuous accumulation scheme for machine learning applications. When applied to a modified ResNet18 network trained under the CIFAR-10 dataset, the simulations indicate that the proposed CCLUTM-based DNV-CIM can achieve a peak energy efficiency of 75.18 TOPS/W with 4-bit multiplication and accumulation (MAC) operations.

Self-Curable Synaptic Ferroelectric FET Arrays for Neuromorphic Convolutional Neural Network

With the recently increasing prevalence of deep learning, both academia and industry exhibit substantial interest in neuromorphic computing, which mimics the functional and structural features of the human brain. To realize neuromorphic computing, an energy-efficient and reliable artificial synapse must be developed. In this study, the synaptic ferroelectric field-effect-transistor (FeFET) array is fabricated as a component of a neuromorphic convolutional neural network. Beyond the single transistor level, the long-term potentiation and depression of synaptic weights are achieved at the array level, and a successful program-inhibiting operation is demonstrated in the synaptic array, achieving a learning accuracy of 79.84% on the Canadian Institute for Advanced Research (CIFAR)-10 dataset. Furthermore, an efficient self-curing method is proposed to improve the endurance of the FeFET array by tenfold, utilizing the punch-through current inherent to the device. Low-frequency noise spectroscopy is employed to quantitatively evaluate the curing efficiency of the proposed self-curing method. The results of this study provide a method to fabricate and operate reliable synaptic FeFET arrays, thereby paving the way for further development of ferroelectric-based neuromorphic computing.

Prediction of Temperature and Loading History Dependent Lumbar Spine Biomechanics Under Cyclic Loading Using Recurrent Neural Networks

Extended-duration cyclic loading of the spine is known to be correlated to lower back pain (LBP). Therefore, it is important to understand how the loading history affects the entire structural behavior of the spine, including the viscoelastic effects. Six human spinal segments (L4L5) were loaded with pure moments up to 7.5 Nm cyclically for half an hour, kept unloaded for 15 min, and loaded with three cycles. This procedure was performed in flexion-extension (FE), axial rotation (AR), and lateral bending (LB) and repeated six times per direction for a total of 18 h of testing per segment. A Long Short-Term Memory (LSTM) Recurrent Neural Network (RNN) was trained to predict the change in the biomechanical response under cyclic loading. A strong positive correlation between the total testing time and the ratio of the third cycle to the last cycle of the loading sequence was found (BT: [Formula: see text] =  0.3469, p = 0.0003, RT: [Formula: see text] =0.1988, p  =   0.0377). The moment-range of motion (RoM) curves could be very well predicted with an RNN ([Formula: see text]=0.988), including the correlation between testing time and testing temperature as inputs. This study shows successfully the feasibility of using RNNs to predict changing moment-RoM curves under cyclic moment loading.

Wearable in-sensor reservoir computing using optoelectronic polymers with through-space charge-transport characteristics for multi-task learning

In-sensor multi-task learning is not only the key merit of biological visions but also a primary goal of artificial-general-intelligence. However, traditional silicon-vision-chips suffer from large time/energy overheads. Further, training conventional deep-learning models is neither scalable nor affordable on edge-devices. Here, a material-algorithm co-design is proposed to emulate human retina and the affordable learning paradigm. Relying on a bottle-brush-shaped semiconducting p-NDI with efficient exciton-dissociations and through-space charge-transport characteristics, a wearable transistor-based dynamic in-sensor Reservoir-Computing system manifesting excellent separability, fading memory, and echo state property on different tasks is developed. Paired with a 'readout function' on memristive organic diodes, the RC recognizes handwritten letters and numbers, and classifies diverse costumes with accuracies of 98.04%, 88.18%, and 91.76%, respectively (higher than all reported organic semiconductors). In addition to 2D images, the spatiotemporal dynamics of RC naturally extract features of event-based videos, classifying 3 types of hand gestures at an accuracy of 98.62%. Further, the computing cost is significantly lower than that of the conventional artificial-neural-networks. This work provides a promising material-algorithm co-design for affordable and highly efficient photonic neuromorphic systems.

Humanlike spontaneous motion coordination of robotic fingers through spatial multi-input spike signal multiplexing

With advances in robotic technology, the complexity of control of robot has been increasing owing to fundamental signal bottlenecks and limited expressible logic state of the von Neumann architecture. Here, we demonstrate coordinated movement by a fully parallel-processable synaptic array with reduced control complexity. The synaptic array was fabricated by connecting eight ion-gel-based synaptic transistors to an ion gel dielectric. Parallel signal processing and multi-actuation control could be achieved by modulating the ionic movement. Through the integration of the synaptic array and a robotic hand, coordinated movement of the fingers was achieved with reduced control complexity by exploiting the advantages of parallel multiplexing and analog logic. The proposed synaptic control system provides considerable scope for the advancement of robotic control systems.

Retention Secured Nonlinear and Self-Rectifying Analog Charge Trap Memristor for Energy-Efficient Neuromorphic Hardware

A memristive crossbar array (MCA) is an ideal platform for emerging memory and neuromorphic hardware due to its high bitwise density capability. A charge trap memristor (CTM) is an attractive candidate for the memristor cell of the MCA, because the embodied rectifying characteristic frees it from the sneak current issue. Although the potential of the CTM devices has been suggested, their practical viability needs to be further proved. Here, a Pt/Ta2 O5 /Nb2 O5- x /Al2 O3- y /Ti CTM stack exhibiting high retention and array-level uniformity is proposed, allowing a highly reliable selector-less MCA. It shows high self-rectifying and nonlinear current-voltage characteristics below 1 µA of programming current with a continuous analog switching behavior. Also, its retention is longer than 105 s at 150 °C, suggesting the device is highly stable for non-volatile analog applications. A plausible band diagram model is proposed based on the electronic spectroscopy results and conduction mechanism analysis. The self-rectifying and nonlinear characteristics allow reducing the on-chip training energy consumption by 71% for the MNIST dataset training task with an optimized programming scheme.

Ferroelectric Polarized in Transistor Channel Polarity Modulation for Reward-Modulated Spike-Time-Dependent Plasticity Application

Reward signals reflect the developmental tendency of reinforcement learning (RL) agents. Reward-modulated spike-time-dependent plasticity (R-STDP) is an efficient and concise information processing feature in RL. However, the physical construction of R-STDP normally demands complex circuit design engineering, resulting in large power consumption and large area. In this work, we studied the role of ferroelectric polarization in the modulation of carbon nanotube transistor channel polarity. Furthermore, we applied a modulating channel method to construct a 2T synaptic component by spin-coating technology. Based on the nonvolatility of ferroelectric polarization, the synaptic component constructed has the characteristics of reconfigurable polarity. One channel could be modulated to n-type and the other to p-type. One modulated channel was used to perform the STDP function when the reward signal arrived, and the other modulated channel was used to perform the anti-STDP function when the punishment signal arrived. Finally, R-STDP learning rules are implemented on hardware. This work provides a strategy for hardware construction of RL.

Second-order associative memory circuit hardware implemented by the evolution from battery-like capacitance to resistive switching memory

Memristor-based Pavlov associative memory circuit presented today only realizes the simple condition reflex process. The secondary condition reflex endows the simple condition reflex process with more bionic, but it is only demonstrated in design and involves the large number of redundant circuits. A FeOx-based memristor exhibits an evolution process from battery-like capacitance (BLC) state to resistive switching (RS) memory as the I-V sweeping increase. The BLC is triggered by the active metal ion and hydroxide ion originated from water molecule splitting at different interfaces, while the RS memory behavior is dominated by the diffusion and migration of ion in the FeOx switching function layer. The evolution processes share the nearly same biophysical mechanism with the second-order conditioning. It enables a hardware-implemented second-order associative memory circuit to be feasible and simple. This work provides a novel path to realize the associative memory circuit with the second-order conditioning at hardware level.

Convolutional Neural Network Based on Crossbar Arrays of (Co-Fe-B)x(LiNbO3)100-x Nanocomposite Memristors

Convolutional neural networks (CNNs) have been widely used in image recognition and processing tasks. Memristor-based CNNs accumulate the advantages of emerging memristive devices, such as nanometer critical dimensions, low power consumption, and functional similarity to biological synapses. Most studies on memristor-based CNNs use either software models of memristors for simulation analysis or full hardware CNN realization. Here, we propose a hybrid CNN, consisting of a hardware fixed pre-trained and explainable feature extractor and a trainable software classifier. The hardware part was realized on passive crossbar arrays of memristors based on nanocomposite (Co-Fe-B)_x(LiNbO₃)_100-x structures. The constructed 2-kernel CNN was able to classify the binarized Fashion-MNIST dataset with ~ 84% accuracy. The performance of the hybrid CNN is comparable to the other reported memristor-based systems, while the number of trainable parameters for the hybrid CNN is substantially lower. Moreover, the hybrid CNN is robust to the variations in the memristive characteristics: dispersion of 20% leads to only a 3% accuracy decrease. The obtained results pave the way for the efficient and reliable realization of neural networks based on partially unreliable analog elements.

Self-organization of an inhomogeneous memristive hardware for sequence learning

Learning is a fundamental component of creating intelligent machines. Biological intelligence orchestrates synaptic and neuronal learning at multiple time scales to self-organize populations of neurons for solving complex tasks. Inspired by this, we design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorporates resistive memory (RRAM) in its synapses and neurons which configure their state based on Hebbian and Homeostatic plasticity respectively. For the first time, we derive these plasticity rules directly from the statistical measurements of our fabricated RRAM-based neurons and synapses. These "technologically plausible” learning rules exploit the intrinsic variability of the devices and improve the accuracy of the network on a sequence learning task by 30%. Finally, we compare the performance of MEMSORN to a fully-randomly-set-up spiking recurrent network on the same task, showing that self-organization improves the accuracy by more than 15%. This work demonstrates the importance of the device-circuit-algorithm co-design approach for implementing brain-inspired computing hardware.

One gap between the neuro-inspired computing and its applications lies in the intrinsic variability of the devices. Here, Payvand et al. suggest a technologically plausible co-design of the hardware architecture which takes into account and exploits the physics behind memristors.

Constructing van der Waals heterostructures by dry-transfer assembly for novel optoelectronic device

Since the first successful exfoliation of graphene, the superior physical and chemical properties of two-dimensional (2D) materials, such as atomic thickness, strong in-plane bonding energy and weak inter-layer van der Waals (vdW) force have attracted wide attention. Meanwhile, there is a surge of interest in novel physics which is absent in bulk materials. Thus, vertical stacking of 2D materials could be critical to discover such physics and develop novel optoelectronic applications. Although vdW heterostructures have been grown by chemical vapor deposition, the available choices of materials for stacking is limited and the device yield is yet to be improved. Another approach to build vdW heterostructure relies on wet/dry transfer techniques like stacking Lego bricks. Although previous reviews have surveyed various wet transfer techniques, novel dry transfer techniques have been recently been demonstrated, featuring clean and sharp interfaces, which also gets rid of contamination, wrinkles, bubbles formed during wet transfer. This review summarizes the optimized dry transfer methods, which paves the way towards high-quality 2D material heterostructures with optimized interfaces. Such transfer techniques also lead to new physical phenomena while enable novel optoelectronic applications on artificial vdW heterostructures, which are discussed in the last part of this review.

A Learning-Rate Modulable and Reliable TiOx Memristor Array for Robust, Fast, and Accurate Neuromorphic Computing

Realization of memristor-based neuromorphic hardware system is important to achieve energy efficient bigdata processing and artificial intelligence in integrated device system-level. In this sense, uniform and reliable titanium oxide (TiO_x ) memristor array devices are fabricated to be utilized as constituent device element in hardware neural network, representing passive matrix array structure enabling vector-matrix multiplication process between multisignal and trained synaptic weight. In particular, in situ convolutional neural network hardware system is designed and implemented using a multiple 25 × 25 TiO_x memristor arrays and the memristor device parameters are developed to bring global constant voltage programming scheme for entire cells in crossbar array without any voltage tuning peripheral circuit such as transistor. Moreover, the learning rate modulation during in situ hardware training process is successfully achieved due to superior TiO_x memristor performance such as threshold uniformity (≈2.7%), device yield (> 99%), repetitive stability (≈3000 spikes), low asymmetry value of ≈1.43, ambient stability (6 months), and nonlinear pulse response. The learning rate modulable fast-converging in situ training based on direct memristor operation shows five times less training iterations and reduces training energy compared to the conventional hardware in situ training at ≈95.2% of classification accuracy.

Neuro-inspired electronic skin for robots

Touch is a complex sensing modality owing to large number of receptors (mechano, thermal, pain) nonuniformly embedded in the soft skin all over the body. These receptors can gather and encode the large tactile data, allowing us to feel and perceive the real world. This efficient somatosensation far outperforms the touch-sensing capability of most of the state-of-the-art robots today and suggests the need for neural-like hardware for electronic skin (e-skin). This could be attained through either innovative schemes for developing distributed electronics or repurposing the neuromorphic circuits developed for other sensory modalities such as vision and audio. This Review highlights the hardware implementations of various computational building blocks for e-skin and the ways they can be integrated to potentially realize human skin-like or peripheral nervous system-like functionalities. The neural-like sensing and data processing are discussed along with various algorithms and hardware architectures. The integration of ultrathin neuromorphic chips for local computation and the printed electronics on soft substrate used for the development of e-skin over large areas are expected to advance robotic interaction as well as open new avenues for research in medical instrumentation, wearables, electronics, and neuroprosthetics.

Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks

Recent years have seen a rapid rise of artificial neural networks being employed in a number of cognitive tasks. The ever-increasing computing requirements of these structures have contributed to a desire for novel technologies and paradigms, including memristor-based hardware accelerators. Solutions based on memristive crossbars and analog data processing promise to improve the overall energy efficiency. However, memristor nonidealities can lead to the degradation of neural network accuracy, while the attempts to mitigate these negative effects often introduce design trade-offs, such as those between power and reliability. In this work, authors design nonideality-aware training of memristor-based neural networks capable of dealing with the most common device nonidealities. The feasibility of using high-resistance devices that exhibit high I-V nonlinearity is demonstrated-by analyzing experimental data and employing nonideality-aware training, it is estimated that the energy efficiency of memristive vector-matrix multipliers is improved by almost three orders of magnitude (0.715 TOPs^-1 W^-1 to 381 TOPs^-1 W^-1 ) while maintaining similar accuracy. It is shown that associating the parameters of neural networks with individual memristors allows to bias these devices toward less conductive states through regularization of the corresponding optimization problem, while modifying the validation procedure leads to more reliable estimates of performance. The authors demonstrate the universality and robustness of this approach when dealing with a wide range of nonidealities.

Toward memristive in-memory computing: principles and applications

With the rapid growth of computer science and big data, the traditional von Neumann architecture suffers the aggravating data communication costs due to the separated structure of the processing units and memories. Memristive in-memory computing paradigm is considered as a prominent candidate to address these issues, and plentiful applications have been demonstrated and verified. These applications can be broadly categorized into two major types: soft computing that can tolerant uncertain and imprecise results, and hard computing that emphasizes explicit and precise numerical results for each task, leading to different requirements on the computational accuracies and the corresponding hardware solutions. In this review, we conduct a thorough survey of the recent advances of memristive in-memory computing applications, both on the soft computing type that focuses on artificial neural networks and other machine learning algorithms, and the hard computing type that includes scientific computing and digital image processing. At the end of the review, we discuss the remaining challenges and future opportunities of memristive in-memory computing in the incoming Artificial Intelligence of Things era.

Implementing in-situ self-organizing maps with memristor crossbar arrays for data mining and optimization

A self-organizing map (SOM) is a powerful unsupervised learning neural network for analyzing high-dimensional data in various applications. However, hardware implementation of SOM is challenging because of the complexity in calculating the similarities and determining neighborhoods. We experimentally demonstrated a memristor-based SOM based on Ta/TaO_x/Pt 1T1R chips for the first time, which has advantages in computing speed, throughput, and energy efficiency compared with the CMOS digital counterpart, by utilizing the topological structure of the array and physical laws for computing without complicated circuits. We employed additional rows in the crossbar arrays and identified the best matching units by directly calculating the similarities between the input vectors and the weight matrix in the hardware. Using the memristor-based SOM, we demonstrated data clustering, image processing and solved the traveling salesman problem with much-improved energy efficiency and computing throughput. The physical implementation of SOM in memristor crossbar arrays extends the capability of memristor-based neuromorphic computing systems in machine learning and artificial intelligence.

Self-organizing maps are data mining tools for unsupervised learning algorithms dealing with big data problems. The authors experimentally demonstrate a memristor-based self-organizing map that is more efficient in computing speed and energy consumption for data clustering, image processing and solving optimization problems.

Memristor-based analogue computing for brain-inspired sound localization with in situ training

The human nervous system senses the physical world in an analogue but efficient way. As a crucial ability of the human brain, sound localization is a representative analogue computing task and often employed in virtual auditory systems. Different from well-demonstrated classification applications, all output neurons in localization tasks contribute to the predicted direction, introducing much higher challenges for hardware demonstration with memristor arrays. In this work, with the proposed multi-threshold-update scheme, we experimentally demonstrate the in-situ learning ability of the sound localization function in a 1K analogue memristor array. The experimental and evaluation results reveal that the scheme improves the training accuracy by ∼45.7% compared to the existing method and reduces the energy consumption by ∼184× relative to the previous work. This work represents a significant advance towards memristor-based auditory localization system with low energy consumption and high performance.

Exploiting Non-idealities of Resistive Switching Memories for Efficient Machine Learning

Novel computing architectures based on resistive switching memories (also known as memristors or RRAMs) have been shown to be promising approaches for tackling the energy inefficiency of deep learning and spiking neural networks. However, resistive switch technology is immature and suffers from numerous imperfections, which are often considered limitations on implementations of artificial neural networks. Nevertheless, a reasonable amount of variability can be harnessed to implement efficient probabilistic or approximate computing. This approach turns out to improve robustness, decrease overfitting and reduce energy consumption for specific applications, such as Bayesian and spiking neural networks. Thus, certain non-idealities could become opportunities if we adapt machine learning methods to the intrinsic characteristics of resistive switching memories. In this short review, we introduce some key considerations for circuit design and the most common non-idealities. We illustrate the possible benefits of stochasticity and compression with examples of well-established software methods. We then present an overview of recent neural network implementations that exploit the imperfections of resistive switching memory, and discuss the potential and limitations of these approaches.

The Image Identification Application with HfO2-Based Replaceable 1T1R Neural Networks

This paper mainly studies the hardware implementation of a fully connected neural network based on the 1T1R (one-transistor-one-resistor) array and its application in handwritten digital image recognition. The 1T1R arrays are prepared by connecting the memristor and nMOSFET in series, and a single-layer and a double-layer fully connected neural network are established. The recognition accuracy of 8 × 8 handwritten digital images reaches 95.19%. By randomly replacing the devices with failed devices, it is found that the stuck-off devices have little effect on the accuracy of the network, but the stuck-on devices will cause a sharp reduction of accuracy. By using the measured conductivity adjustment range and precision data of the memristor, the relationship between the recognition accuracy of the network and the number of hidden neurons is simulated. The simulation results match the experimental results. Compared with the neural network based on the precision of 32-bit floating point, the difference is lower than 1%.

Nanostructured perovskites for nonvolatile memory devices

Perovskite materials have driven tremendous advances in constructing electronic devices owing to their low cost, facile synthesis, outstanding electric and optoelectronic properties, flexible dimensionality engineering, and so on. Particularly, emerging nonvolatile memory devices (eNVMs) based on perovskites give birth to numerous traditional paradigm terminators in the fields of storage and computation. Despite significant exploration efforts being devoted to perovskite-based high-density storage and neuromorphic electronic devices, research studies on materials' dimensionality that has dominant effects on perovskite electronics' performances are paid little attention; therefore, a review from the point of view of structural morphologies of perovskites is essential for constructing perovskite-based devices. Here, recent advances of perovskite-based eNVMs (memristors and field-effect-transistors) are reviewed in terms of the dimensionality of perovskite materials and their potentialities in storage or neuromorphic computing. The corresponding material preparation methods, device structures, working mechanisms, and unique features are showcased and evaluated in detail. Furthermore, a broad spectrum of advanced technologies (e.g., hardware-based neural networks, in-sensor computing, logic operation, physical unclonable functions, and true random number generator), which are successfully achieved for perovskite-based electronics, are investigated. It is obvious that this review will provide benchmarks for designing high-quality perovskite-based electronics for application in storage, neuromorphic computing, artificial intelligence, information security, etc.

In-Memory Realization of Eligibility Traces Based on Conductance Drift of Phase Change Memory for Energy-Efficient Reinforcement Learning

Reinforcement learning (RL) has shown outstanding performance in handling complex tasks in recent years. Eligibility trace (ET), a fundamental and important mechanism in reinforcement learning, records critical states with attenuation and guides the update of policy, which plays a crucial role in accelerating the convergence of RL training. However, ET implementation on conventional digital computing hardware is energy hungry and restricted by the memory wall due to massive calculation of exponential decay functions. Here, in-memory realization of ET for energy-efficient reinforcement learning with outstanding performance in discrete- and continuous-state RL tasks is demonstrated. For the first time, the inherent conductance drift of phase change memory is exploited as physical decay function to realize in-memory eligibility trace, demonstrating excellent performance during RL training in various tasks. The spontaneous in-memory decay computing and storage of policy in the same phase change memory give rise to significantly enhanced energy efficiency compared with traditional graphics processing unit platforms. This work therefore provides a holistic energy and hardware efficient method for both training and inference of reinforcement learning.

Application of mathematical morphology operation with memristor-based computation-in-memory architecture for detecting manufacturing defects

Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis. These data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units (CPUs) and graphics processing units (GPUs). Computation-in-memory (CIM) provides a possible solution for highly efficient morphology operations. In this study, we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromorphic computation on a multi-array-based memristor system. Pixel-by-pixel logic computations with low parallelism are converted to parallel operations using memristors. Moreover, hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit (IC) manufacturing and medical image analysis. In addition, we developed a new implementation scheme employing a four-layer network to realize small-object detection with high parallelism. The system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed, respectively, exhibiting the advantage of the proposed memristor-based morphology operation.

Gradient Decomposition Methods for Training Neural Networks With Non-ideal Synaptic Devices

While promising for high-capacity machine learning accelerators, memristor devices have non-idealities that prevent software-equivalent accuracies when used for online training. This work uses a combination of Mini-Batch Gradient Descent (MBGD) to average gradients, stochastic rounding to avoid vanishing weight updates, and decomposition methods to keep the memory overhead low during mini-batch training. Since the weight update has to be transferred to the memristor matrices efficiently, we also investigate the impact of reconstructing the gradient matrixes both internally (rank-seq) and externally (rank-sum) to the memristor array. Our results show that streaming batch principal component analysis (streaming batch PCA) and non-negative matrix factorization (NMF) decomposition algorithms can achieve near MBGD accuracy in a memristor-based multi-layer perceptron trained on the MNIST (Modified National Institute of Standards and Technology) database with only 3 to 10 ranks at significant memory savings. Moreover, NMF rank-seq outperforms streaming batch PCA rank-seq at low-ranks making it more suitable for hardware implementation in future memristor-based accelerators.

A fully hardware-based memristive multilayer neural network

Memristive crossbar arrays promise substantial improvements in computing throughput and power efficiency through in-memory analog computing. Previous machine learning demonstrations with memristive arrays, however, relied on software or digital processors to implement some critical functionalities, leading to frequent analog/digital conversions and more complicated hardware that compromises the energy efficiency and computing parallelism. Here, we show that, by implementing the activation function of a neural network in analog hardware, analog signals can be transmitted to the next layer without unnecessary digital conversion, communication, and processing. We have designed and built compact rectified linear units, with which we constructed a two-layer perceptron using memristive crossbar arrays, and demonstrated a recognition accuracy of 93.63% for the Modified National Institute of Standard and Technology (MNIST) handwritten digits dataset. The fully hardware-based neural network reduces both the data shuttling and conversion, capable of delivering much higher computing throughput and power efficiency.

A High-Precision Implementation of the Sigmoid Activation Function for Computing-in-Memory Architecture

Computing-In-Memory (CIM), based on non-von Neumann architecture, has lately received significant attention due to its lower overhead in delay and higher energy efficiency in convolutional and fully-connected neural network computing. Growing works have given the priority to researching the array of memory and peripheral circuits to achieve multiply-and-accumulate (MAC) operation, but not enough attention has been paid to the high-precision hardware implementation of non-linear layers up to now, which still causes time overhead and power consumption. Sigmoid is a widely used non-linear activation function and most of its studies provided an approximation of the function expression rather than totally matched, inevitably leading to considerable error. To address this issue, we propose a high-precision circuit implementation of the sigmoid, matching the expression exactly for the first time. The simulation results with the SMIC 40 nm process suggest that the proposed circuit implemented high-precision sigmoid perfectly achieves the properties of the ideal sigmoid, showing the maximum error and average error between the proposed simulated sigmoid and ideal sigmoid is 2.74% and 0.21%, respectively. In addition, a multi-layer convolutional neural network based on CIM architecture employing the simulated high-precision sigmoid activation function verifies the similar recognition accuracy on the test database of handwritten digits compared to utilize the ideal sigmoid in software, with online training achieving 97.06% and with offline training achieving 97.74%.

A Quantized Convolutional Neural Network Implemented With Memristor for Image Denoising and Recognition

The interference of noise will cause the degradation of image quality, which can have a negative impact on the subsequent image processing and visual effect. Although the existing image denoising algorithms are relatively perfect, their computational efficiency is restricted by the performance of the computer, and the computational process consumes a lot of energy. In this paper, we propose a method for image denoising and recognition based on multi-conductance states of memristor devices. By regulating the evolution of Pt/ZnO/Pt memristor wires, 26 continuous conductance states were obtained. The image feature preservation and noise reduction are realized via the mapping between the conductance state and the image pixel. Furthermore, weight quantization of convolutional neural network is realized based on multi-conductance states. The simulation results show the feasibility of CNN for image denoising and recognition based on multi-conductance states. This method has a certain guiding significance for the construction of high-performance image noise reduction hardware system.

Self-rectifying resistive memory in passive crossbar arrays

Conventional computing architectures are poor suited to the unique workload demands of deep learning, which has led to a surge in interest in memory-centric computing. Herein, a trilayer (Hf0.8Si0.2O2/Al2O3/Hf0.5Si0.5O2)-based self-rectifying resistive memory cell (SRMC) that exhibits (i) large selectivity (ca. 104), (ii) two-bit operation, (iii) low read power (4 and 0.8 nW for low and high resistance states, respectively), (iv) read latency (<10 μs), (v) excellent non-volatility (data retention >104 s at 85 °C), and (vi) complementary metal-oxide-semiconductor compatibility (maximum supply voltage ≤5 V) is introduced, which outperforms previously reported SRMCs. These characteristics render the SRMC highly suitable for the main memory for memory-centric computing which can improve deep learning acceleration. Furthermore, the low programming power (ca. 18 nW), latency (100 μs), and endurance (>106) highlight the energy-efficiency and highly reliable random-access memory of our SRMC. The feasible operation of individual SRMCs in passive crossbar arrays of different sizes (30 × 30, 160 × 160, and 320 × 320) is attributed to the large asymmetry and nonlinearity in the current-voltage behavior of the proposed SRMC, verifying its potential for application in large-scale and high-density non-volatile memory for memory-centric computing.

Adaptive Extreme Edge Computing for Wearable Devices

Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions toward smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g., memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices.

In-sensor reservoir computing for language learning via two-dimensional memristors

The dynamic processing of optoelectronic signals carrying temporal and sequential information is critical to various machine learning applications including language processing and computer vision. Despite extensive efforts to emulate the visual cortex of human brain, large energy/time overhead and extra hardware costs are incurred by the physically separated sensing, memory, and processing units. The challenge is further intensified by the tedious training of conventional recurrent neural networks for edge deployment. Here, we report in-sensor reservoir computing for language learning. High dimensionality, nonlinearity, and fading memory for the in-sensor reservoir were achieved via two-dimensional memristors based on tin sulfide (SnS), uniquely having dual-type defect states associated with Sn and S vacancies. Our in-sensor reservoir computing demonstrates an accuracy of 91% to classify short sentences of language, thus shedding light on a low training cost and the real-time solution for processing temporal and sequential signals for machine learning applications at the edge.

In-Memory Computing with Resistive Memory Circuits: Status and Outlook

In-memory computing (IMC) refers to non-von Neumann architectures where data are processed in situ within the memory by taking advantage of physical laws. Among the memory devices that have been considered for IMC, the resistive switching memory (RRAM), also known as memristor, is one of the most promising technologies due to its relatively easy integration and scaling. RRAM devices have been explored for both memory and IMC applications, such as neural network accelerators and neuromorphic processors. This work presents the status and outlook on the RRAM for analog computing, where the precision of the encoded coefficients, such as the synaptic weights of a neural network, is one of the key requirements. We show the experimental study of the cycle-to-cycle variation of set and reset processes for HfO2-based RRAM, which indicate that gate-controlled pulses present the least variation in conductance. Assuming a constant variation of conductance σG, we then evaluate and compare various mapping schemes, including multilevel, binary, unary, redundant and slicing techniques. We present analytical formulas for the standard deviation of the conductance and the maximum number of bits that still satisfies a given maximum error. Finally, we discuss RRAM performance for various analog computing tasks compared to other computational memory devices. RRAM appears as one of the most promising devices in terms of scaling, accuracy and low-current operation.

Dielectric Engineered Two-Dimensional Neuromorphic Transistors

Two-dimensional (2D) materials, which exhibit planar-wafer technique compatibility and pure electrically triggered communication, have established themselves as potential candidates in neuromorphic architecture integration. However, the current 2D artificial synapses are mainly realized at a single-device level, where the development of 2D scalable synaptic arrays with complementary metal-oxide-semiconductor compatibility remains challenging. Here, we report a 2D transition metal dichalcogenide-based synaptic array fabricated on commercial silicon-rich silicon nitride (sr-SiN_x) substrate. The array demonstrates uniform performance with sufficiently high analogue on/off ratio and linear conductance update, and low cycle-to-cycle variability (1.5%) and device-to-device variability (5.3%), which are essential for neuromorphic hardware implementation. On the basis of the experimental data, we further prove that the artificial synapses can achieve a recognition accuracy of 91% on the MNIST handwritten data set. Our findings offer a simple approach to achieve 2D synaptic arrays by using an industry-compatible sr-SiN_x dielectric, promoting a brand-new paradigm of 2D materials in neuromorphic computing.

Self-Powered Memristive Systems for Storage and Neuromorphic Computing

A neuromorphic computing chip that can imitate the human brain’s ability to process multiple types of data simultaneously could fundamentally innovate and improve the von-neumann computer architecture, which has been criticized. Memristive devices are among the best hardware units for building neuromorphic intelligence systems due to the fact that they operate at an inherent low voltage, use multi-bit storage, and are cost-effective to manufacture. However, as a passive device, the memristor cell needs external energy to operate, resulting in high power consumption and complicated circuit structure. Recently, an emerging self-powered memristive system, which mainly consists of a memristor and an electric nanogenerator, had the potential to perfectly solve the above problems. It has attracted great interest due to the advantages of its power-free operations. In this review, we give a systematic description of self-powered memristive systems from storage to neuromorphic computing. The review also proves a perspective on the application of artificial intelligence with the self-powered memristive system.