The influence of atmosphere on the performance of pure-phase WZ and ZB InAs nanowire transistors

Near-Infrared Artificial Optical Synapse Based on the P(VDF-TrFE)-Coated InAs Nanowire Field-Effect Transistor

Optical synapse is the basic component for optical neuromorphic computing and is attracting great attention, mainly due to its great potential in many fields, such as image recognition, artificial intelligence and artificial visual perception systems. However, optical synapse with infrared (IR) response has rarely been reported. InAs nanowires (NWs) have a direct narrow bandgap and a large surface to volume ratio, making them a promising material for IR detection. Here, we demonstrate a near-infrared (NIR) (750 to 1550 nm) optical synapse for the first time based on a poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE))-coated InAs NW field-effect transistor (FET). The responsivity of the P(VDF-TrFE)-coated InAs NW FET reaches 839.3 A/W under 750 nm laser illumination, demonstrating the advantage of P(VDF-TrFE) coverage. The P(VDF-TrFE)-coated InAs NW device exhibits optical synaptic behaviors in response to NIR light pulses, including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF) and a transformation from short-term plasticity (STP) to long-term plasticity (LTP). The working mechanism is attributed to the polarization effect in the ferroelectric P(VDF-TrFE) layer, which dominates the trapping and de-trapping characteristics of photogenerated holes. These findings have significant implications for the development of artificial neural networks.

Enhancing the electrical performance of InAs nanowire field-effect transistors by improving the surface and interface properties by coating with thermally oxidized Y2O3

Due to their excellent electrical characteristics, InAs nanowires (NWs) have great potential as conducting channels in integrated circuits. However, the surface effect and loose native oxide coverage can deteriorate the performance of InAs NW transistors. Y₂O₃, a high-k dielectric with low Gibbs free energy, has been proposed to modify the InAs NW surface. Here, we systematically investigate the effect of Y₂O₃ coating on the performance of InAs NW field-effect transistors (FETs). We first explore the influence of the thermal oxidation process of Y₂O₃ on the performance of back-gated FETs. We then observe that the coverage of Y₂O₃/HfO₂ bilayers on the NW decreases the hysteresis (the smallest value reaches 0.1 V), subthreshold swing (SS, down to 169 mV dec^-1) and on-state resistance R_on, and increases the field-effect mobility μ_FE (up to 4876.1 cm² V^-1 s^-1) and the on-off ratio, mainly owing to the passivation effect on the NW surface. Finally, paired top-gated NW FETs with a Y₂O₃/HfO₂ bilayer and a single layer of HfO₂ dielectric are fabricated and compared. The Y₂O₃/HfO₂ bilayer provides better gate control (SS_min = 113 mV dec^-1) under a smaller gate oxide capacitance, with an interface trap density as low as 1.93 × 10¹² eV^-1 cm^-2. The use of the Y₂O₃/HfO₂ stack provides an effective strategy to enhance the performance of III-V-based transistors for future applications.

High-Throughput Electrical Characterization of Nanomaterials from Room to Cryogenic Temperatures

We present multiplexer methodology and hardware for nanoelectronic device characterization. This high-throughput and scalable approach to testing large arrays of nanodevices operates from room temperature to milli-Kelvin temperatures and is universally compatible with different materials and integration techniques. We demonstrate the applicability of our approach on two archetypal nanomaterials-graphene and semiconductor nanowires-integrated with a GaAs-based multiplexer using wet or dry transfer methods. A graphene film grown by chemical vapor deposition is transferred and patterned into an array of individual devices, achieving 94% yield. Device performance is evaluated using data fitting methods to obtain electrical transport metrics, showing mobilities comparable to nonmultiplexed devices fabricated on oxide substrates using wet transfer techniques. Separate arrays of indium-arsenide nanowires and micromechanically exfoliated monolayer graphene flakes are transferred using pick-and-place techniques. For the nanowire array mean values for mobility μ_FE = 880/3180 cm² V^-1 s^-1 (lower/upper bound), subthreshold swing 430 mV dec^-1, and on/off ratio 3.1 decades are extracted, similar to nonmultiplexed devices. In another array, eight mechanically exfoliated graphene flakes are transferred using techniques compatible with fabrication of two-dimensional superlattices, with 75% yield. Our results are a proof-of-concept demonstration of a versatile platform for scalable fabrication and cryogenic characterization of nanomaterial device arrays, which is compatible with a broad range of nanomaterials, transfer techniques, and device integration strategies from the forefront of quantum technology research.

Conductometric Sensing with Individual InAs Nanowires

In this work, we isolate individual wurtzite InAs nanowires and fabricate electrical contacts at both ends, exploiting the single nanostructures as building blocks to realize two different architectures of conductometric sensors: (a) the nanowire is drop-casted onto-supported by-a SiO2/Si substrate, and (b) the nanowire is suspended at approximately 250 nm from the substrate. We test the source-drain current upon changes in the concentration of humidity, ethanol, and NO2, using synthetic air as a gas carrier, moving a step forward towards mimicking operational environmental conditions. The supported architecture shows higher response in the mid humidity range (50% relative humidity), with shorter response and recovery times and lower detection limit with respect to the suspended nanowire. These experimental pieces of evidence indicate a minor role of the InAs/SiO2 contact area; hence, there is no need for suspended nanostructures to improve the sensing performance. Moreover, the sensing capability of single InAs nanowires for detection of NO2 and ethanol in the ambient atmosphere is reported and discussed.

Simultaneous Growth of Pure Wurtzite and Zinc Blende Nanowires

The opportunity to engineer III-V nanowires in wurtzite and zinc blende crystal structure allows for exploring properties not conventionally available in the bulk form as well as opening the opportunity for use of additional degrees of freedom in device fabrication. However, the fundamental understanding of the nature of polytypism in III-V nanowire growth is still lacking key ingredients to be able to connect the results of modeling and experiments. Here we show InP nanowires of both pure wurtzite and pure zinc blende grown simultaneously on the same InP [100]-oriented substrate. We find wurtzite nanowires to grow along [Formula: see text] and zinc blende counterparts along [Formula: see text]. Further, we discuss the nucleation, growth, and polytypism of our nanowires against the background of existing theory. Our results demonstrate, first, that the crystal growth conditions for wurtzite and zinc blende nanowire growth are not mutually exclusive and, second, that the interface energies predominantly determine the crystal structure of the nanowires.

Improving the electrical properties of InAs nanowire field effect transistors by covering them with Y2O3/HfO2 layers

Quasi-one-dimensional semiconducting materials have attracted increasing attention due to their excellent ability to downscale the size of transistors. However, in quasi-one-dimensional nanowire (NW) transistors, their surface and interface properties play a very important role mainly due to the large surface-to-volume ratio of NWs and surface scattering, which degrade their carrier mobility. Herein, we developed a new method to cover the channel surface of InAs NW field effect transistors (FETs) with Y₂O₃/HfO₂ layers to improve their electrical properties. We successfully fabricated nine FETs and measured their electrical properties, which improve after depositing the Y₂O₃/HfO₂ layers, including an increase in on-state current, decrease in off-state current, increase in transconductance, increase in electron mobility and decrease in subthreshold swing. By comparing the properties of Y₂O₃/HfO₂-covered devices with that of the FETs fabricated without the Y₂O₃ covering or without annealing, we prove that it is the combined Y₂O₃/HfO₂ layers instead of only the Y₂O₃ or HfO₂ layer that improve the electrical properties of the FETs. The Cs-corrected high-resolution scanning transmission electron microscopy study demonstrates that Y can actually diffuse through the native oxide layer (confirmed to be InO_x) and reach the surface of the InAs NWs. Our results indicate that the desirable characteristics of Y₂O₃ and the surface passivation by HfO₂ improve the electrical properties of the InAs NW FETs, in which Y₂O₃ plays an important role to modify and stabilize the interface between the InAs NWs and the outside dielectric layer. Furthermore, this method should also be applicable to other III-V materials.

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10³ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Engineering the Photoresponse of InAs Nanowires

We report on individual-InAs nanowire optoelectronic devices which can be tailored to exhibit either negative or positive photoconductivity (NPC or PPC). The NPC photoresponse time and magnitude is found to be highly tunable by varying the nanowire diameter under controlled growth conditions. Using hysteresis characterization, we decouple the observed photoexcitation-induced hot electron trapping from conventional electric field-induced trapping to gain a fundamental insight into the interface trap states responsible for NPC. Furthermore, we demonstrate surface passivation without chemical etching which both enhances the field-effect mobility of the nanowires by approximately an order of magnitude and effectively eliminates the hot carrier trapping found to be responsible for NPC, thus restoring an "intrinsic" positive photoresponse. This opens pathways toward engineering semiconductor nanowires for novel optical-memory and photodetector applications.