Low-power circuits for brain-machine interfaces

Brain-computer interface: trend, challenges, and threats

Brain-computer interface (BCI), an emerging technology that facilitates communication between brain and computer, has attracted a great deal of research in recent years. Researchers provide experimental results demonstrating that BCI can restore the capabilities of physically challenged people, hence improving the quality of their lives. BCI has revolutionized and positively impacted several industries, including entertainment and gaming, automation and control, education, neuromarketing, and neuroergonomics. Notwithstanding its broad range of applications, the global trend of BCI remains lightly discussed in the literature. Understanding the trend may inform researchers and practitioners on the direction of the field, and on where they should invest their efforts more. Noting this significance, we have analyzed 25,336 metadata of BCI publications from Scopus to determine advancement of the field. The analysis shows an exponential growth of BCI publications in China from 2019 onwards, exceeding those from the United States that started to decline during the same period. Implications and reasons for this trend are discussed. Furthermore, we have extensively discussed challenges and threats limiting exploitation of BCI capabilities. A typical BCI architecture is hypothesized to address two prominent BCI threats, privacy and security, as an attempt to make the technology commercially viable to the society.

Inhibition of Long-Term Variability in Decoding Forelimb Trajectory Using Evolutionary Neural Networks With Error-Correction Learning

Objective: In brain machine interfaces (BMIs), the functional mapping between neural activities and kinematic parameters varied over time owing to changes in neural recording conditions. The variability in neural recording conditions might result in unstable long-term decoding performance. Relevant studies trained decoders with several days of training data to make them inherently robust to changes in neural recording conditions. However, these decoders might not be robust to changes in neural recording conditions when only a few days of training data are available. In time-series prediction and feedback control system, an error feedback was commonly adopted to reduce the effects of model uncertainty. This motivated us to introduce an error feedback to a neural decoder for dealing with the variability in neural recording conditions. Approach: We proposed an evolutionary constructive and pruning neural network with error feedback (ECPNN-EF) as a neural decoder. The ECPNN-EF with partially connected topology decoded the instantaneous firing rates of each sorted unit into forelimb movement of a rat. Furthermore, an error feedback was adopted as an additional input to provide kinematic information and thus compensate for changes in functional mapping. The proposed neural decoder was trained on data collected from a water reward-related lever-pressing task for a rat. The first 2 days of data were used to train the decoder, and the subsequent 10 days of data were used to test the decoder. Main Results: The ECPNN-EF under different settings was evaluated to better understand the impact of the error feedback and partially connected topology. The experimental results demonstrated that the ECPNN-EF achieved significantly higher daily decoding performance with smaller daily variability when using the error feedback and partially connected topology. Significance: These results suggested that the ECPNN-EF with partially connected topology could cope with both within- and across-day changes in neural recording conditions. The error feedback in the ECPNN-EF compensated for decreases in decoding performance when neural recording conditions changed. This mechanism made the ECPNN-EF robust against changes in functional mappings and thus improved the long-term decoding stability when only a few days of training data were available.

Simultaneous Multimodal PC Access for People With Disabilities by Integrating Head Tracking, Speech Recognition, and Tongue Motion

Multimodal Tongue Drive System (mTDS) is a highly integrated wireless assistive technology (AT) in the form of a lightweight wearable headset that utilizes three remaining key control and communication abilities in people with severe physical disabilities, such as tetraplegia, to provide them with effective access to computers: 1) tongue motion for discrete/switch-based control (e.g., clicking), 2) head tracking for proportional control (e.g., mouse pointer movements), and 3) speech recognition for typing, all available simultaneously. The mTDS architecture is presented here with new sensor signal processing algorithm for head tracking. To evaluate the device performance, it was compared against keyboard-and-mouse (KnM) combination, the gold standard in computer input methods, by 15 able-bodied participants, who used both mTDS and KnM to generate and sent an email with randomly selected content, under a 5-minute time constraint. In four repetitions, in the last trial, it took participants only 1.8 times longer to complete the email task, on average, using the mTDS versus KnM at 82.4% typing accuracy. Mean task completion time and typing accuracy improved 24.6% and 18.8% from first to fourth trial using mTDS. Multimodal simultaneous discrete and proportional control input options of mTDS, plus rapid typing, is expected to provide more effective computer access to people with severe physical disabilities.

A 128-Channel Extreme Learning Machine-Based Neural Decoder for Brain Machine Interfaces

Currently, state-of-the-art motor intention decoding algorithms in brain-machine interfaces are mostly implemented on a PC and consume significant amount of power. A machine learning coprocessor in 0.35- μm CMOS for the motor intention decoding in the brain-machine interfaces is presented in this paper. Using Extreme Learning Machine algorithm and low-power analog processing, it achieves an energy efficiency of 3.45 pJ/MAC at a classification rate of 50 Hz. The learning in second stage and corresponding digitally stored coefficients are used to increase robustness of the core analog processor. The chip is verified with neural data recorded in monkey finger movements experiment, achieving a decoding accuracy of 99.3% for movement type. The same coprocessor is also used to decode time of movement from asynchronous neural spikes. With time-delayed feature dimension enhancement, the classification accuracy can be increased by 5% with limited number of input channels. Further, a sparsity promoting training scheme enables reduction of number of programmable weights by ≈ 2X.

A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition

In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm (2) for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

Brain-Machine Interfaces for Motor Control: A Guide for Neuroscience Clinicians

With the growing interdependence between medicine and technology, the prospect of connecting machines to the human brain is rapidly being realized. The field of neuroprosthetics is transitioning from the proof of concept stage to the development of advanced clinical treatments. In one area of brain-machine interfaces (BMIs) related to the motor system, also termed ‘motor neuroprosthetics’, research successes with implanted microelectrodes in animals have demonstrated immense potential for restoring motor deficits. Early human trials have also begun, with some success but also highlighting several technical challenges. Here we review the concepts and anatomy underlying motor BMI designs, review their early use in clinical applications, and offer a framework to evaluate these technologies in order to predict their eventual clinical utility. Ultimately, we hope to help neuroscience clinicians understand and participate in this burgeoning field.

A digitally assisted, signal folding neural recording amplifier

A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.

A frequency shaping neural recorder with 3 pF input capacitance and 11 plus 4.5 bits dynamic range

This paper presents a frequency-shaping (FS) neural recording architecture and its implementation in a 0.13 μ m CMOS process. Compared with its conventional counterpart, the proposed architecture inherently rejects electrode offset, increases input impedance 5-10 fold, compresses neural data dynamic range (DR) by 4.5-bit, simultaneously records local field potentials (LFPs) and extracellular spikes, and is more suitable for long-term recording experiments. Measured at a 40 kHz sampling clock and ± 0.6 V supply, the recorder consumes 50 μW/ch, of which 22 μW per FS amplifier, 24 μ W per buffer, 4 μ W per 11-bit successive approximation register analog-to-digital converter (SAR ADC). The input-referred noise for LFPs and extracellular spikes are 13 μ Vrms and 7 μVrms, respectively, which are sufficient to achieve high-fidelity full-spectrum neural data. In addition, the designed recorder has a 3 pF input capacitance and allows " 11+4.5"-bit neural data DR without system saturation, where the extra 4.5-bit owes to the FS technique. Its figure-of-merit (FOM) based on data DR reaches 36.0 fJ/conversion-step.

MedMon: securing medical devices through wireless monitoring and anomaly detection

Rapid advances in personal healthcare systems based on implantable and wearable medical devices promise to greatly improve the quality of diagnosis and treatment for a range of medical conditions. However, the increasing programmability and wireless connectivity of medical devices also open up opportunities for malicious attackers. Unfortunately, implantable/wearable medical devices come with extreme size and power constraints, and unique usage models, making it infeasible to simply borrow conventional security solutions such as cryptography. We propose a general framework for securing medical devices based on wireless channel monitoring and anomaly detection. Our proposal is based on a medical security monitor (MedMon) that snoops on all the radio-frequency wireless communications to/from medical devices and uses multi-layered anomaly detection to identify potentially malicious transactions. Upon detection of a malicious transaction, MedMon takes appropriate response actions, which could range from passive (notifying the user) to active (jamming the packets so that they do not reach the medical device). A key benefit of MedMon is that it is applicable to existing medical devices that are in use by patients, with no hardware or software modifications to them. Consequently, it also leads to zero power overheads on these devices. We demonstrate the feasibility of our proposal by developing a prototype implementation for an insulin delivery system using off-the-shelf components (USRP software-defined radio). We evaluate its effectiveness under several attack scenarios. Our results show that MedMon can detect virtually all naive attacks and a large fraction of more sophisticated attacks, suggesting that it is an effective approach to enhancing the security of medical devices.

Simultaneous neural and movement recording in large-scale immersive virtual environments

Virtual reality (VR) allows precise control and manipulation of rich, dynamic stimuli that, when coupled with on-line motion capture and neural monitoring, can provide a powerful means both of understanding brain behavioral relations in the high dimensional world and of assessing and treating a variety of neural disorders. Here we present a system that combines state-of-the-art, fully immersive, 3D, multi-modal VR with temporally aligned electroencephalographic (EEG) recordings. The VR system is dynamic and interactive across visual, auditory, and haptic interactions, providing sight, sound, touch, and force. Crucially, it does so with simultaneous EEG recordings while subjects actively move about a 20 × 20 ft² space. The overall end-to-end latency between real movement and its simulated movement in the VR is approximately 40 ms. Spatial precision of the various devices is on the order of millimeters. The temporal alignment with the neural recordings is accurate to within approximately 1 ms. This powerful combination of systems opens up a new window into brain-behavioral relations and a new means of assessment and rehabilitation of individuals with motor and other disorders.

Estimation of bladder volume from afferent neural activity

Refractive urinary dysfunction in individuals suffering from neurogenic bladder syndrome can be treated with implanted neurostimulators that restore, to some degree, the control of the urinary bladder. A sensor capable of relaying feedback from bladder activity to the implanted neurostimulator is required to implement a closed-loop system to improve overall implant efficacy and minimize deleterious effects to neural tissue caused by continuous electrical stimulation. In this paper, we present a method that allows real-time estimation of bladder volume from the primary afferent activity of bladder mechanoreceptors. Our method was validated with data acquired from anesthetized rats in acute experiments. It was possible to qualitatively estimate three states of bladder fullness in 100% of trials when the recorded afferent activity exhibited a Spearman's correlation coefficient of 0.6 or better. Furthermore, we could quantitatively estimate bladder volume, and also its pressure, using timeframes of properly chosen duration. The mean volume estimation error was 5.8 ±3.1%. Our results also demonstrate that it is possible to quantify both phasic and tonic bladder responses during slow filling and isovolumetric measurements, respectively.

Efficient universal computing architectures for decoding neural activity

The ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain– machine interfaces (BMIs). Such systems require input from tens to hundreds of brain-implanted recording electrodes in order to deliver robust and accurate performance; in serving that primary function they should also minimize power dissipation in order to avoid damaging neural tissue; and they should transmit data wirelessly in order to minimize the risk of infection associated with chronic, transcutaneous implants. Electronic architectures for brain– machine interfaces must therefore minimize size and power consumption, while maximizing the ability to compress data to be transmitted over limited-bandwidth wireless channels. Here we present a system of extremely low computational complexity, designed for real-time decoding of neural signals, and suited for highly scalable implantable systems. Our programmable architecture is an explicit implementation of a universal computing machine emulating the dynamics of a network of integrate-and-fire neurons; it requires no arithmetic operations except for counting, and decodes neural signals using only computationally inexpensive logic operations. The simplicity of this architecture does not compromise its ability to compress raw neural data by factors greater than . We describe a set of decoding algorithms based on this computational architecture, one designed to operate within an implanted system, minimizing its power consumption and data transmission bandwidth; and a complementary set of algorithms for learning, programming the decoder, and postprocessing the decoded output, designed to operate in an external, nonimplanted unit. The implementation of the implantable portion is estimated to require fewer than 5000 operations per second. A proof-of-concept, 32-channel field-programmable gate array (FPGA) implementation of this portion is consequently energy efficient. We validate the performance of our overall system by decoding electrophysiologic data from a behaving rodent.

Computationally efficient neural feature extraction for spike sorting in implantable high-density recording systems

Modern microelectrode arrays acquire neural signals from hundreds of neurons in parallel that are subsequently processed for spike sorting. It is important to identify, extract, and transmit appropriate features that allow accurate spike sorting while using minimum computational resources. This paper describes a new set of spike sorting features, explicitly framed to be computationally efficient and shown to outperform principal component analysis (PCA)-based spike sorting. A hardware friendly architecture, feasible for implantation, is also presented for detecting neural spikes and extracting features to be transmitted for off chip spike classification. The proposed feature set does not require any off-chip training, and requires about 5% of computations as compared to the PCA-based features for the same classification accuracy, tested for spike trains with a broad range of signal-to-noise ratio. Our simulations show a reduction of required bandwidth to about 2% of original data rate, with an average classification accuracy of greater than 94% at a typical signal to noise ratio of 5 dB.

A glucose fuel cell for implantable brain-machine interfaces

We have developed an implantable fuel cell that generates power through glucose oxidation, producing steady-state power and up to peak power. The fuel cell is manufactured using a novel approach, employing semiconductor fabrication techniques, and is therefore well suited for manufacture together with integrated circuits on a single silicon wafer. Thus, it can help enable implantable microelectronic systems with long-lifetime power sources that harvest energy from their surrounds. The fuel reactions are mediated by robust, solid state catalysts. Glucose is oxidized at the nanostructured surface of an activated platinum anode. Oxygen is reduced to water at the surface of a self-assembled network of single-walled carbon nanotubes, embedded in a Nafion film that forms the cathode and is exposed to the biological environment. The catalytic electrodes are separated by a Nafion membrane. The availability of fuel cell reactants, oxygen and glucose, only as a mixture in the physiologic environment, has traditionally posed a design challenge: Net current production requires oxidation and reduction to occur separately and selectively at the anode and cathode, respectively, to prevent electrochemical short circuits. Our fuel cell is configured in a half-open geometry that shields the anode while exposing the cathode, resulting in an oxygen gradient that strongly favors oxygen reduction at the cathode. Glucose reaches the shielded anode by diffusing through the nanotube mesh, which does not catalyze glucose oxidation, and the Nafion layers, which are permeable to small neutral and cationic species. We demonstrate computationally that the natural recirculation of cerebrospinal fluid around the human brain theoretically permits glucose energy harvesting at a rate on the order of at least 1 mW with no adverse physiologic effects. Low-power brain–machine interfaces can thus potentially benefit from having their implanted units powered or recharged by glucose fuel cells.

Approaches for the efficient extraction and processing of biopotentials in implantable neural interfacing microsystems

The accelerating pace of research in neurosciences and rehabilitation engineering has created a considerable demand for implantable microsystems capable of interfacing with large groups of neurons. Such microsystems must provide multiple recording channels incorporating low-noise amplifiers, filters, data converters, neural signal processing circuitry, power management units and low-power transmitters to extract and wirelessly transfer the relevant neural data outside the body for computing and storage. This paper is reviewing several electronic recording strategies to address the challenge of operating large numbers of channels to gather the neural information from several neurons within very low-power constraints.

A low-power 32-channel digitally programmable neural recording integrated circuit

We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm(2) and 0.02 mm(2) respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems.

A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices

In this paper, we present a fully integrated asynchronous step-down switched capacitor dc-dc conversion structure suitable for supporting ultra-low-power circuits commonly found in biomedical implants. The proposed converter uses a fully digital asynchronous state machine as the heart of the control circuitry to generate the drive signals. To minimize the switching losses, the asynchronous controller scales the switching frequency of the drive signals according to the loading conditions. It also turns on additional parallel switches when needed and has a backup synchronous drive mode. This circuit regulates load voltages from 300 mV to 1.1 V derived from a 1.2-V input voltage. A total of 350 pF on-chip capacitance was implemented to support a maximum of 230-μ W load power, while providing efficiency up to 80%. The circuit validating the proposed concepts was fabricated in 0.13- μm complementary metal-oxide semiconductor technology. Experimental test results confirm the expected functionality and performance of the proposed circuit.

Recent advances in neural recording microsystems

The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons. These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications. They can extract the relevant control signals directly from the brain enabling individuals with severe disabilities to communicate their intentions to other devices, like computers or various prostheses. Such microsystems are self-contained devices composed of a neural probe attached with an integrated circuit for extracting neural signals from multiple channels, and transferring the data outside the body. The greatest challenge facing development of such emerging devices into viable clinical systems involves addressing their small form factor and low-power consumption constraints, while providing superior resolution. In this paper, we survey the recent progress in the design and the implementation of multi-channel neural recording Microsystems, with particular emphasis on the design of recording and telemetry electronics. An overview of the numerous neural signal modalities is given and the existing microsystem topologies are covered. We present energy-efficient sensory circuits to retrieve weak signals from neural probes and we compare them. We cover data management and smart power scheduling approaches, and we review advances in low-power telemetry. Finally, we conclude by summarizing the remaining challenges and by highlighting the emerging trends in the field.

Linear-phase delay filters for ultra-low-power signal processing in neural recording implants

We present the design and implementation of linear-phase delay filters for ultra-low-power signal processing in neural recording implants. We use these filters as low-distortion delay elements along with an automatic biopotential detector to perform integral waveform extraction and efficient power management. The presented delay elements are realized employing continuous-time OTA-C filters featuring 9th-order equiripple transfer functions with constant group delay. Such analog delay enables processing neural waveforms with reduced overhead compared to a digital delay since it does not requires sampling and digitization. It uses an allpass transfer function for achieving wider constant-delay bandwidth than all-pole does. Two filters realizations are compared for implementing the delay element: the Cascaded structure and the Inverse follow-the-leader feedback filter. Their respective strengths and drawbacks are assessed by modeling parasitics and non-idealities of OTAs, and by transistor-level simulations. A budget of 200 nA is used in both filters. Experimental measurements with the chosen filter topology are presented and discussed.

Investigating neural correlates of behavior in freely behaving rodents using inertial sensors

Simultaneous behavior and multielectrode neural recordings in freely behaving rodents holds great promise to study the neural bases of behavior and disease models in combination with genetic manipulations. Here, we introduce the use of three-axis accelerometers to characterize the behavior of rats and mice during chronic neural recordings. These sensors were small and light enough to be worn by rodents and were used to record three-axis acceleration during freely moving behavior. A two-layer neural network-based pattern recognition algorithm was developed to extract the natural behavior of mice from the acceleration data. Successful recognition of resting, eating, grooming, and rearing are shown using this approach. The inertial sensors were combined with continuous 24-h recordings of neural data from the striatum of mice to characterize variations in neural activity with circadian cycles and to study the neural correlates of spontaneous action initiation. Finally, accelerometers were used to study the performance of rodents in traditional operant conditioning, where they were used to extract the reaction time of rodents. Thus the addition of accelerometer recordings of rodents to chronic multielectrode neural recordings provides great value for a number of neuroscience applications.

Controlling biological networks by time-delayed signals

This paper describes the use of time-delayed feedback to regulate the behaviour of biological networks. The general ideas on specific transcriptional regulatory and neural networks are demonstrated. It is shown that robust yet tunable controllers can be constructed that provide the biological systems with model-engineered inputs. The results indicate that time delay modulation may serve as an efficient biocompatible control tool.

Low-power circuits for the bidirectional wireless monitoring system of the orthopedic implants

This paper proposes an architecture of the wireless monitoring system for the real-time monitoring of the orthopedic implants, which monitors the implant duty cycle, detects abnormal asymmetry, high amounts of force, and other conditions of the orthopedic implants. Data for diagnosis are communicated wirelessly by the radio-frequency (RF) signal between the embedded chip and the remote circuit. In different working modes, the system can be powered by the RF signal or stiff lead zirconate-titanate (PZT) ceramics which are able to convert mechanical energy inside the orthopedic implant into electrical energy. The power circuits with a variable ratio switched-capacitor (SC) dc-dc converter have been taped out with 0.35-mum complementary metal-oxide semiconductor (CMOS) technology. The test results show that the SC converter can transfer the input voltage that ranges from 5 V to 14 V from the PZT ceramics into the voltage ranging from 2 V to 2.5 V which will be dealt with by a low drop-out circuit in the future work. The total efficiency of the SC converter is from 28% to 42% at full-time working mode. The analog-to-digital converter (ADC) circuits have been fabricated in a 0.18-mum 1P6M CMOS process. The test results show that the ADC chip consumes only 12.5 muW in working mode and 150 nW in the sleep mode. The circuits, including RF circuits, ADC, and the microcontrol unit, have been implemented in a 0.18-mu m CMOS process. Future work includes some clinical experiments test in the application where PZT elements are used for power generation in total knee-replacement implants.

Wireless neural stimulation in freely behaving small animals

We introduce a novel wireless, low-power neural stimulation system for use in freely behaving animals. The system consists of an external transmitter and a miniature, implantable wireless receiver-stimulator. The implant uses a custom integrated chip to deliver biphasic current pulses to four addressable bipolar electrodes at 32 selectable current levels (10 microA to 1 mA). To achieve maximal battery life, the chip enters a sleep mode when not needed and can be awakened remotely when required. To test our device, we implanted bipolar stimulating electrodes into the songbird motor nucleus HVC (formerly called the high vocal center) of zebra finches. Single-neuron recordings revealed that wireless stimulation of HVC led to a strong increase of spiking activity in its downstream target, the robust nucleus of the arcopallium. When we used this device to deliver biphasic pulses of current randomly during singing, singing activity was prematurely terminated in all birds tested. Thus our device is highly effective for remotely modulating a neural circuit and its corresponding behavior in an untethered, freely behaving animal.

Power-efficient impedance-modulation wireless data links for biomedical implants

We analyze the performance of wireless data telemetry links for implanted biomedical systems. An experimental realization of a bidirectional half-duplex link that uses near-field inductive coupling between the implanted system and an external transceiver is described. Our system minimizes power consumption in the implanted system by using impedance modulation to transmit high-bandwidth information in the uplink direction, i.e., from the implanted to the external system. We measured a data rate of 2.8 Mbps at a bit error rate (BER) of <10(-6) (we could not measure error rates below 10(-6) ) and a data rate of 4.0 Mbps at a BER of 10(-3). Experimental results also demonstrate data transfer rates up to 300 kbps in the opposite, i.e., downlink direction. We also perform a theoretical analysis of the bit error rate performance. An important effect regarding the asymmetry of rising and falling edges that is inherent to impedance modulation is predicted by theory and confirmed by experiment. The link dissipates 2.5 mW in the external system and only 100 muW in the implanted system, making it among the most power-efficient inductive data links reported. Our link is compatible with FCC regulations on radiated emissions.