320-channel active probe for high-resolution neuromonitoring and responsive neurostimulation

A Scalable, Programmable Neural Stimulator for Enhancing Generalizability in Neural Interface Applications

Each application of neurostimulators requires unique stimulation parameter specifications to achieve effective stimulation. Balancing the current magnitude with stimulation resolution, waveform, size, and channel count is challenging, leading to a loss of generalizability across broad neural interfaces. To address this, this paper proposes a highly scalable, programmable neurostimulator with a System-on-Chip (SOC) capable of 32 channels of independent stimulation. The compliance voltage reaches up to ±22.5 V. A pair of 8-bit current-mode DACs support independent waveforms for source and sink operations and feature a user-selectable dual range for low-current intraparenchymal microstimulation with a resolution of 4.31 μA/bit, as well as high current stimulation for spinal cord and DBS applications with a resolution of 48.00 μA/bit, achieving a wide stimulation range of 12.24 mA while maintaining high-resolution biological stimulation. A dedicated communication protocol enables full programmable control of stimulation waveforms, effectively improving the range of stimulation parameters. In vivo electrophysiological experiments successfully validate the functionality of the proposed stimulator. This flexible stimulator architecture aims to enhance its generality across a wide range of neural interfaces and will provide more diverse and refined stimulation strategies.

A Portable and a Scalable Multi-Channel Wireless Recording System for Wearable Electromyometrial Imaging

Electromyometrial imaging (EMMI) technology has emerged as one of the promising technology that can be used for non-invasive pregnancy risk stratification and for preventing complications due to pre-term birth. Current EMMI systems are bulky and require a tethered connection to desktop instrumentation, as a result, the system cannot be used in non-clinical and ambulatory settings. In this article, we propose an approach for designing a scalable, portable wireless EMMI recording system that can be used for in-home and remote monitoring. The wearable system uses a non-equilibrium differential electrode multiplexing approach to enhance signal acquisition bandwidth and to reduce the artifacts due to electrode drifts, amplifier 1/f noise, and bio-potential amplifier saturation. A combination of active shielding, a passive filter network, and a high-end instrumentation amplifier ensures sufficient input dynamic range ([Formula: see text]) such that the system can simultaneously acquire different bio-potential signals like maternal electrocardiogram (ECG) in addition to the EMMI electromyogram (EMG) signals. We show that the switching artifacts and the channel cross-talk introduced due to non-equilibrium sampling can be reduced using a compensation technique. This enables the system to be potentially scaled to a large number of channels without significantly increasing the system power dissipation. We demonstrate the feasibility of the proposed approach in a clinical setting using an 8-channel battery-powered prototype which dissipates less than 8 μW per channel for a signal bandwidth of 1 KHz.

An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive Δ - Δ Σ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 μ W , and an input-referred noise of 7.7 ± 0.4 μ V rms in the AP band and 11.9 ± 1.1 μ V rms in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

Trends in volumetric-energy efficiency of implantable neurostimulators: a review from a circuits and systems perspective

This paper presents a comprehensive review of state-of-the-art, commercially available neurostimulators. We analyse key design parameters and performance metrics of 45 implantable medical devices across six neural target categories: deep brain, vagus nerve, spinal cord, phrenic nerve, sacral nerve and hypoglossal nerve. We then benchmark these alongside modern cardiac pacemaker devices that represent a more established market. This work studies trends in device size, electrode number, battery technology (i.e., primary and secondary use and chemistry), power consumption and longevity. This information is analysed to show the course of design decisions adopted by industry and identifying opportunity for further innovation. We identify fundamental limits in power consumption, longevity and size as well as the interdependencies and trade-offs. We propose a figure of merit to quantify volumetric efficiency within specific therapeutic targets, battery technologies/capacities, charging capabilities and electrode count. Finally, we compare commercially available implantable medical devices with recently developed systems in the research community. We envisage this analysis to aid circuit and system designers in system optimisation and identifying innovation opportunities, particularly those related to low power circuit design techniques.

A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection

This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 µW, achieving ultra-low-power operation.

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop

This article presents a direct digitizing neural recorder that uses a body-induced offset based DC servo loop to cancel electrode offset (EDO) on-chip. The bulk of the input pair is used to create an offset, counteracting the EDO. The architecture does not require AC coupling capacitors which enables the use of chopping without impedance boosting while maintaining a large input impedance of 238 M Ω over the whole 10 kHz bandwidth. Implemented in a 180 nm HV-CMOS process, the prototype occupies a silicon area of only 0.02 mm² while consuming 12.8 μW and achieving 1.82 μV[Formula: see text] of input-referred noise in the local field potential (LFP) band and a NEF of 5.75.

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μW/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μW/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

A Multi-Channel Stimulator With High-Resolution Time-to-Current Conversion for Vagal-Cardiac Neuromodulation

This paper presents a low power integrated multi-channel stimulator for a cardiac neuroprosthesis designed to restore the parasympathetic control after heart transplantation. The proposed stimulator is based on time-to-current conversion. It replaces the conventional current mode digital-to-analog converter (DAC) that uses tens of microamps for biasing, with a novel capacitor time-based DAC (CT-DAC) offering about 10-bit current amplitude resolution with a bias current of only 250 nA. A stimulator chip was designed in a 0.18 μm CMOS high-voltage (HV) technology. It consists of 16 independent channels, each capable of delivering up to 550 μA stimulus current with a HV output stage that can be operated up to 20 V. The stimulator chip performance was evaluated using both RC equivalent load and a microelectrode array in saline solution. It is power efficient, provides high-resolution current amplitude stimulation, and has good charge balance. The design is suitable for multi-channel neural stimulation applications.

A 1024-Channel 10-Bit 36- μW/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping

This paper presents a 1024-channel neural read-out integrated circuit (ROIC) for solution-gated GFET sensing probes in massive μECoG brain mapping. The proposed time-domain multiplexing of GFET-only arrays enables low-cost and scalable hybrid headstages. Low-power CMOS circuits are presented for the GFET analog frontend, including a CDS mechanism to improve preamplifier noise figures and 10-bit 10-kS/s A/D conversion. The 1024-channel ROIC has been fabricated in a standard 1.8-V 0.18- μm CMOS technology with 0.012 mm ² and 36 μ W per channel. An automated methodology for the in-situ calibration of each GFET sensor is also proposed. Experimental ROIC tests are reported using a custom FPGA-based μECoG headstage with 16×32 and 32×32 GFET probes in saline solution and agar substrate. Compared to state-of-art neural ROICs, this work achieves the largest scalability in hybrid platforms and it allows the recording of infra-slow neural signals.

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopper-stabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036 mm², an input referred noise of [Formula: see text] (1 to 200 Hz) and [Formula: see text] (0.2 to 10 kHz), power consumption of 13.7 μW from 1.8 V supply, as well as CMRR and PSRR ≥ 83 dB at 50 Hz.

Light Modulation of Brain and Development of Relevant Equipment

Light modulation plays an important role in understanding the pathology of brain disorders and improving brain function. Optogenetic techniques can activate or silence targeted neurons with high temporal and spatial accuracy and provide precise control, and have recently become a method for quick manipulation of genetically identified types of neurons. Photobiomodulation (PBM) is light therapy that utilizes non-ionizing light sources, including lasers, light emitting diodes, or broadband light. It provides a safe means of modulating brain activity without any irreversible damage and has established optimal treatment parameters in clinical practice. This manuscript reviews 1) how optogenetic approaches have been used to dissect neural circuits in animal models of Alzheimer's disease, Parkinson's disease, and depression, and 2) how low level transcranial lasers and LED stimulation in humans improves brain activity patterns in these diseases. State-of-the-art brain machine interfaces that can record neural activity and stimulate neurons with light have good prospects in the future.

Frequency-Division Multiplexing with Graphene Active Electrodes for Neurosensor Applications

Multielectrode arrays are used broadly for neural recording, both in vivo and for ex vivo cultured neurons. In most cases, recording sites are passive electrodes wired to external read-out circuitry, and the number of wires is at least equal to the number of recording sites. We present an approach to break the conventional N-wire, N-electrode array architecture using graphene active electrodes, which allow signal upconversion at the recording site and sharing of each interface wire among multiple active electrodes using frequency-division multiplexing (FDM). The presented work includes the design and implementation of a frequency modulation and readout architecture using graphene FET electrodes, a custom integrated circuit (IC) analog front-end (AFE), and digital demodulation. The AFE was fabricated in 0.18 μm CMOS; electrical characterization and multi-channel FDM results are provided, including GFET-based signal modulation and IC/DSP demodulation. Long-term, this approach can simultaneously enable high signal count, high spatial resolution, and high temporal precision to infer functional interactions between neurons while markedly decreasing access wires.

Long-Term Non Anesthetic Preclinical Study Available Extra-Cranial Brain Activator (ECBA) System for the Future Minimally Invasive Human Neuro Modulation

In recent years, electroceuticals have been spotlighted as an emerging treatment for various severe chronic brain diseases, owing to their intrinsic advantage of electrical interaction with the brain, which is the most electrically active organ. However, the majority of research has verified only the short-term efficacy through acute studies in laboratory tests owing to the lack of a reliable miniaturized platform for long-term animal studies. The construction of a sufficient integrated system for such a platform is extremely difficult because it requires multi-disciplinary work using state-of-the-art technologies in a wide range of fields. In this study, we propose a complete system of an implantable platform for long-term preclinical brain studies. Our proposed system, the extra-cranial brain activator (ECBA), consists of a titanium-packaged implantable module and a helmet-type base station that powers the module wirelessly. The ECBA can also be controlled by a remote handheld device. Using the ECBA, we performed a long-term non-anesthetic study with multiple canine subjects, and the resulting PET-CT scans demonstrated remarkable enhancement in brain activity relating to memory and sensory skills. Furthermore, the histological analysis and high-temperature aging test confirmed the reliability of the system for up to 31 months. Hence, the proposed ECBA system is expected to lead a new paradigm of human neuromodulation studies in the near future.

A Trimodal Wireless Implantable Neural Interface System-on-Chip

A wireless and battery-less trimodal neural interface system-on-chip (SoC), capable of 16-ch neural recording, 8-ch electrical stimulation, and 16-ch optical stimulation, all integrated on a 5 ×  3 mm2 chip fabricated in 0.35-μm standard CMOS process. The trimodal SoC is designed to be inductively powered and communicated. The downlink data telemetry utilizes on-off keying pulse-position modulation (OOK-PPM) of the power carrier to deliver configuration and control commands at 50 kbps. The analog front-end (AFE) provides adjustable mid-band gain of 55-70 dB, low/high cut-off frequencies of 1-100 Hz/10 kHz, and input-referred noise of 3.46 μVrms within 1 Hz-50 kHz band. AFE outputs of every two-channel are digitized by a 50 kS/s 10-bit SAR-ADC, and multiplexed together to form a 6.78 Mbps data stream to be sent out by OOK modulating a 434 MHz RF carrier through a power amplifier (PA) and 6 cm monopole antenna, which form the uplink data telemetry. Optical stimulation has a switched-capacitor based stimulation (SCS) architecture, which can sequentially charge four storage capacitor banks up to 4 V and discharge them in selected μLEDs at instantaneous current levels of up to 24.8 mA on demand. Electrical stimulation is supported by four independently driven stimulating sites at 5-bit controllable current levels in ±(25-775) μA range, while active/passive charge balancing circuits ensure safety. In vivo testing was conducted on four anesthetized rats to verify the functionality of the trimodal SoC.

Recent Advances in Electrical Neural Interface Engineering: Minimal Invasiveness, Longevity, and Scalability

Electrical neural interfaces serve as direct communication pathways that connect the nervous system with the external world. Technological advances in this domain are providing increasingly more powerful tools to study, restore, and augment neural functions. Yet, the complexities of the nervous system give rise to substantial challenges in the design, fabrication, and system-level integration of these functional devices. In this review, we present snapshots of the latest progresses in electrical neural interfaces, with an emphasis on advances that expand the spatiotemporal resolution and extent of mapping and manipulating brain circuits. We include discussions of large-scale, long-lasting neural recording; wireless, miniaturized implants; signal transmission, amplification, and processing; as well as the integration of interfaces with optical modalities. We outline the background and rationale of these developments and share insights into the future directions and new opportunities they enable.

A Software-Defined Radio Receiver for Wireless Recording From Freely Behaving Animals

To eliminate tethering effects on the small animals' behavior during electrophysiology experiments, such as neural interfacing, a robust and wideband wireless data link is needed for communicating with the implanted sensing elements without blind spots. We present a software-defined radio (SDR) based scalable data acquisition system, which can be programmed to provide coverage over standard-sized or customized experimental arenas. The incoming RF signal with the highest power among SDRs is selected in real-time to prevent data loss in the presence of spatial and angular misalignments between the transmitter (Tx) and receiver (Rx) antennas. A 32-channel wireless neural recording system-on-a-chip (SoC), known as WINeRS-8, is embedded in a headstage and transmits digitalized raw neural signals, which are sampled at 25 kHz/ch, at 9 Mbps via on-off keying (OOK) of a 434 MHz RF carrier. Measurement results show that the dual-SDR Rx system reduces the packet loss down to 0.12%, on average, by eliminating the blind spots caused by the moving Tx directionality. The system operation is verified in vivo on a freely behaving rat and compared with a commercial hardwired system.

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

Large-scale in vivo electrophysiology requires tools that enable simultaneous recording of multiple brain regions at single-neuron level. This calls for the design of more compact neural probes that offer even larger arrays of addressable sites and high channel counts. With this aim, we present in this paper a quad-shank approach to integrate as many as 5,120 sites on a single probe. Compact fully-differential recording channels were designed using a single-gain-stage neural amplifier with a 14-bit ADC, achieving a mean input-referred noise of 7.44 μV_rms in the action-potential band and 7.65 μV_rms in the local-field-potential band, a mean total harmonic distortion of 0.17% at 1 kHz and a mean input-referred offset of 169 μV. The probe base incorporates 384 channels with on-chip power management, reference-voltage generation and digital control, thus achieving the highest level of integration in a neural probe and excellent channel-to-channel uniformity. Therefore, no calibration or external circuitry are required to achieve the above-mentioned performance. With a total area of 2.2 × 8.67 mm² and a power consumption of 36.5 mW, the presented probe enables full-system miniaturization for acute or chronic use in small rodents.

Frameworks for Efficient Brain-Computer Interfacing

One challenge present in brain-computer interface (BCI) circuits is finding a balance between real-time on-chip processing in-vivo and wireless transmission of neural signals for off-chip in-silico processing. This article presents three potential frameworks for investigating an area- and energy-efficient realization of BCI circuits. The first framework performs spike detection on the filtered neural signal on a brain-implantable chip and only transmits detected spikes wirelessly for offline classification and decoding. The second framework performs in-vivo compression of the on-chip detected spikes prior to wireless transmission for substantially reducing wireless transmission overhead. The third framework performs spike sorting in-vivo on the brain-implantable chip to classify detected spikes on-chip and hence, even further reducing wireless data transmission rate at the expense of more signal processing. To alleviate the on-chip computation of spike sorting and also utilizing a more area- and energy-effective design, this work employs, for the first time, to the best of our knowledge, an artificial neural network (ANN) instead of using relatively computationally-intensive conventional spike sorting algorithms. The ASIC implementation results of the designed frameworks are presented and their feasibility for efficient in-vivo processing of neural signals is discussed. Compared to the previously-published BCI systems, the presented frameworks reduce the area and power consumption of implantable circuits.

A Dual-Band Wireless Power Transmission System for Evaluating mm-Sized Implants

Distributed neural interfaces made of many mm-sized implantable medical devices (IMDs) are poised to play a key role in future brain-computer interfaces because of less damage to the surrounding tissue. Evaluating them wirelessly at preclinical stage (e.g., in a rodent model), however, is a major challenge due to weak coupling and significant losses, resulting in limited power delivery to the IMD within a nominal experimental arena, like a homecage, without surpassing the specific absorption rate limit. To address this problem, we present a dual-band EnerCage system with two multi-coil inductive links, which first deliver power at 13.56 MHz from the EnerCage (46 × 24 × 20 cm3) to a headstage (18 × 18 × 15 mm3, 4.8 g) that is carried by the animal via a 4-coil inductive link. Then, a 60 MHz 3-coil inductive link from the headstage powers up the small IMD (2.5 × 2.5 × 1.5 mm3, 15 mg), which in this case is a free floating, wirelessly powered, implantable optical stimulator (FF-WIOS). The power transfer efficiency and power delivered to the load (PDL) from EnerCage to the headstage at 7 cm height were 14.9%-22.7% and 122 mW; and from headstage to FF-WIOS at 5 mm depth were 18% and 2.7 mW, respectively. Bidirectional data connectivity between EnerCage-headstage was established via bluetooth low energy. Between headstage and FF-WIOS, on-off keying and load-shift-keying were used for downlink and uplink data, respectively. Moreover, a closed-loop power controller stabilized PDL to both the headstage and the FF-WIOS against misalignments.

Discriminative Ratio of Spectral Power and Relative Power Features Derived via Frequency-Domain Model Ratio With Application to Seizure Prediction

The ratio of spectral power in two different bands and relative band power have been shown to be sometimes more discriminative features than the spectral power in a specific band for binary classification of a time series for seizure prediction. However, why and which ratio of spectral power and relative power features are better discriminators than a band power have not been understood. While general answers to why and which are difficult, this paper partially addresses the answer to these questions. Using auto-regressive modeling, this paper, for the first time, theoretically explains that for high signal-to-noise ratio (SNR) cases, the ratio features may sometime amplify the discriminability of one of the two states in a time series, as compared with a band power. This paper, also for the first time, introduces a novel frequency-domain model ratio (FDMR) that can be used to select the two frequency bands. The FDMR computes the ratio of the frequency responses of the two auto-regressive model filters that correspond to two different states. It is shown that the ratio implicitly cancels the effect of change of variance of the white noise that is input to the auto-regressive model in a non-stationary environment for high SNR conditions. It is also shown that under certain sufficient but not necessary conditions, the ratio of the spectral power and the relative band power, i.e., the band power divided by the total power spectral density, can be better discriminators than band power. Synthesized data and scalp EEG data from the MIT Physionet for patient-specific seizure prediction are used to explain why the ratios of spectral power obtained by a ranking algorithm in the prior literature satisfy the sufficient conditions for amplification of the ratio feature derived in this paper.

Compact and Low-Power Neural Spike Compression Using Undercomplete Autoencoders

Implantable microsystems that collect and transmit neural data are becoming very useful entities in the field of neuroscience. Limited by high data rates, on-chip compression is often required to transmit the recorded data without causing power dissipation at levels that would damage sensitive brain tissue. This paper presents a data compression system designed for brain-computer interfaces (BCIs) based on undercomplete autoencoders. To the best of our knowledge, the proposed system is the first to achieve an average spike reconstruction quality of 14-dB signal-to-noise-and-distortion ratio (SNDR) at a 32× compression ratio (CR), 18-dB SNDR at a 16× CR, 22-dB SNDR at an 8× CR, and 35-dB SNDR at a 4× CR of neural spikes. The spike detection and autoencoder-based compression modules are designed and implemented in a standard 45-nm CMOS process. The post-synthesis simulation results report that the compression module consumes between 1.4 and 222.5 [Formula: see text] of power per channel and takes between 0.018 and 0.082mm² of silicon area, depending on the desired CR and number of channels.

A Fully Integrated RF-Powered Energy-Replenishing Current-Controlled Stimulator

This paper presents a fully-integrated current-controlled stimulator that is powered directly from on-chip coil antenna and achieves adiabatic energy-replenishing operation without any bulky external components. Adiabatic supply voltages, which can reach a differential range of up to 7.2 V, are directly generated from an on-chip 190-MHz resonant LC tank via a self-cascading/folding rectifier network, bypassing the losses that would otherwise be introduced by the 0.8 V system supply-generating rectifier and regulator. The stimulator occupies 0.22 mm ² in a 180 nm silicon-on-insulator process and produces differential currents up to 145  μA. Using a charge replenishing scheme, the stimulator redirects the charges accumulated across the electrodes to the system power supplies for 63.1% of stimulation energy recycling. To benchmark the efficiency of stimulation, a figure of merit termed the stimulator efficiency factor (SEF) is introduced. The adiabatic power rails and energy replenishment scheme enabled our stimulator to achieve an SEF of 6.0.

SPICODYN: A Toolbox for the Analysis of Neuronal Network Dynamics and Connectivity from Multi-Site Spike Signal Recordings

We implemented an automated and efficient open-source software for the analysis of multi-site neuronal spike signals. The software package, named SPICODYN, has been developed as a standalone windows GUI application, using C# programming language with Microsoft Visual Studio based on .NET framework 4.5 development environment. Accepted input data formats are HDF5, level 5 MAT and text files, containing recorded or generated time series spike signals data. SPICODYN processes such electrophysiological signals focusing on: spiking and bursting dynamics and functional-effective connectivity analysis. In particular, for inferring network connectivity, a new implementation of the transfer entropy method is presented dealing with multiple time delays (temporal extension) and with multiple binary patterns (high order extension). SPICODYN is specifically tailored to process data coming from different Multi-Electrode Arrays setups, guarantying, in those specific cases, automated processing. The optimized implementation of the Delayed Transfer Entropy and the High-Order Transfer Entropy algorithms, allows performing accurate and rapid analysis on multiple spike trains from thousands of electrodes.

A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates

Closed-loop neuromodulation systems aim to treat a variety of neurological conditions by delivering and adjusting therapeutic electrical stimulation in response to a patient's neural state, recorded in real time. Existing systems are limited by low channel counts, lack of algorithmic flexibility, and the distortion of recorded signals by large and persistent stimulation artefacts. Here, we describe an artefact-free wireless neuromodulation device that enables research applications requiring high-throughput data streaming, low-latency biosignal processing, and simultaneous sensing and stimulation. The device is a miniaturized neural interface capable of closed-loop recording and stimulation on 128 channels, with on-board processing to fully cancel stimulation artefacts. In addition, it can detect neural biomarkers and automatically adjust stimulation parameters in closed-loop mode. In a behaving non-human primate, the device enabled long-term recordings of local field potentials and the real-time cancellation of stimulation artefacts, as well as closed-loop stimulation to disrupt movement preparatory activity during a delayed-reach task. The neuromodulation device may help advance neuroscientific discovery and preclinical investigations of stimulation-based therapeutic interventions.

A Chronically Implantable Neural Coprocessor for Investigating the Treatment of Neurological Disorders

Developing new tools to better understand disorders of the nervous system, with a goal to more effectively treat them, is an active area of bioelectronic medicine research. Future tools must be flexible and configurable, given the evolving understanding of both neuromodulation mechanisms and how to configure a system for optimal clinical outcomes. We describe a system, the Summit RC+S "neural coprocessor," that attempts to bring the capability and flexibility of a microprocessor to a prosthesis embedded within the nervous system. This paper describes the updated system architecture for the Summit RC+S system, the five custom integrated circuits required for bi-directional neural interfacing, the supporting firmware/software ecosystem, and the verification and validation activities to prepare for human implantation. Emphasis is placed on design changes motivated by experience with the CE-marked Activa PC+S research tool; specifically, enhancement of sense-stim performance for improved bi-directional communication to the nervous system, implementation of rechargeable technology to extend device longevity, and application of MICS-band telemetry for algorithm development and data management. The technology was validated in a chronic treatment paradigm for canines with naturally occurring epilepsy, including free ambulation in the home environment, which represents a typical use case for future human protocols.

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves <0.004 mm² area per channel, 7 µW power dissipation per channel, 5.6 µVrms input referred noise, 50 dB common mode rejection ratio, and generates 9-bit samples at 30 kHz per channel by multiplexing at 600 kHz. General considerations are discussed for rapid time domain multiplexing of high-impedance microelectrodes. Overall, this work describes a promising path forward for scaling neural recording systems to numbers of electrodes that are orders of magnitude larger.

A Scalable Optoelectronic Neural Probe Architecture With Self-Diagnostic Capability

There is a growing demand for the development of new types of implantable optoelectronics to support both basic neuroscience and optogenetic treatments for neurological disorders. Target specification requirements include multi-site optical stimulation, programmable radiance profile, safe operation, and miniaturization. It is also preferable to have a simple serial interface rather than large numbers of control lines. This paper demonstrates an optrode structure comprising of a standard complementary metal-oxide-semiconductor process with 18 optical stimulation drivers. Furthermore, diagnostic sensing circuitry is incorporated to determine the long-term functionality of the photonic elements. A digital control system is incorporated to allow independent multisite control and serial communication with external control units.

Recovery of early neural spikes from stimulation electrodes using a DC-coupled low gain high resolution data acquisition system

BACKGROUND

Neural responses to electrical stimulation provide valuable information to probe and study the network function. Especially, recording neural responses from the stimulated site provides improved neural interfacing method. However, it is difficult to measure short-delayed responses at the stimulated electrode due to the saturation of the amplifier after stimulation which is called "stimulus artifact". Despite the advances in handling stimulation artifacts, it is still very challenging to deal with the artifacts if one tries to stimulate and record from the same electrode.

NEW METHOD

In this paper, we developed a system consisting of 24 bit ADC and low gain DC-amplifier which allows us to record the entire responses including saturation-free stimulus artifact and neural responses with excellent resolution.

RESULTS

Our approach showed saturation-free recording after stimulation, which makes it possible to recover neural spike as early as in 2 ms at the stimulating electrode with digital elimination methods.

COMPARISON WITH EXISTING METHODS

With our system we could record neural signals after stimulation that was difficult with high gain and high pass filtered recording system due to amplifier saturation.

CONCLUSIONS

Our new system can enhance interface performance with its higher robustness and with simple system configuration.

On-Probe Neural Interface ASIC for Combined Electrical Recording and Optogenetic Stimulation

Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics-the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08  μV) recording channels optimized for recording local field potentials (LFPs) (0.1-300 Hz bandwidth, 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35  μm CMOS technology occupying a 1.95 mm 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.

Design and Fabrication of a Three-Dimensional Multi-Electrode Array for Neuron Electrophysiology

Neural recording and stimulation with high spatial and temporal resolution are highly desirable in the study of neurocommunication and diseases. Planar multiple microelectrode arrays (MEA) or quasi-three-dimensional (3D) MEA with fixed height have been proposed by many researchers and become commercially available. In this paper, we present the design, fabrication, and test of a novel true 3D multiple electrode array for brain slice stimulation and recording. This MEA is composed of 105 microelectrodes with 50 μm diameter and 125 μm center-to-center spacing integrated in a 1.2 × 1.2 mm2 area. This "true" 3D MEA allows us to precisely position the individual electrodes by piezoelectric-based actuators to penetrate the inactive tissue layer and to approach the active neurons so as to optimize the recording and stimulation of electrical field potential. The capability to stimulate nerve fibers and record postsynaptic field potentials was demonstrated in an experiment using mouse brain hippocampus slice.

Toward adaptive deep brain stimulation in Parkinson's disease: a review

Clinical deep brain stimulation (DBS) is now regarded as the therapeutic intervention of choice at the advanced stages of Parkinson's disease. However, some major challenges of DBS are stimulation induced side effects and limited pacemaker battery life. Side effects and shortening of pacemaker battery life are mainly as a result of continuous stimulation and poor stimulation focus. These drawbacks can be mitigated using adaptive DBS (aDBS) schemes. Side effects resulting from continuous stimulation can be reduced through adaptive control using closed-loop feedback, while those due to poor stimulation focus can be mitigated through spatial adaptation. Other advantages of aDBS include automatic, rather than manual, initial adjustment and programming, and long-term adjustments to maintain stimulation parameters with changes in patient's condition. Both result in improved efficacy. This review focuses on the major areas that are essential in driving technological advances for the various aDBS schemes. Their challenges, prospects and progress so far are analyzed. In addition, important advances and milestones in state-of-the-art aDBS schemes are highlighted – both for closed-loop adaption and spatial adaption. With perspectives and future potentials of DBS provided at the end.

A miniaturized UWB antenna for implantable data telemetry

This paper presents a miniaturized impulse radio ultra-wideband (IR-UWB) antenna which is designed for transcutaneous, short-distance data communication used in multichannel neural recording. In these systems, with the increasing number of recording channels, data rates of 10-100 Mbit/s must be transmitted with very limited power and area. Therefore, the antennas are designed as planar, ellipsoidal dipoles on a high permittivity substrate with ε_r = 10.2 to achieve high radiation efficiency with small physical size. In order to increase the robustness against misalignment, a circularly polarized antenna is used at the external receiver unit, reducing the signal power variation under angular misalignment. For the transmitting antenna a miniaturized prototype with an integrated pulse generator was designed on a round shaped PCB with a diameter of only 14mm. Measurements through porcine skin in the frequency domain show an attenuation of less than 30dB in the intended frequency band between 6 and 8.5GHz. Additional evaluations in the time domain prove possible pulse repetition rates of up to 100MHz at a transmission distance of 1.5cm.

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes

Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, a 256-channel neural sensing microsystem with a sensing area of 5 × 5 mm ² is presented based on 2.5-D through-silicon-via (TSV) integration. This microsystem composes of dissolvable μ-needles, TSV-embedded μ-probes, 256-channel neural amplifiers, 11-bit area-power-efficient successive approximation register analog-to-digital converters, and serializers. This microsystem can detect 256 electrocorticography and local field potential signals within a small area of 5 mm × 5 mm. The neural amplifier realizes 57.8 dB gain with only 9.8 μW per channel. The overall power of this microsystem is only 3.79 mW for 256-channel neural sensing. A smaller microsystem with dimension of 6 mm × 4 mm has been also implanted into rat brain for somatosensory evoked potentials (SSEPs) recording by using contralateral and ipsilateral electrical stimuli with intensity from 0.2 to 1.0 mA, and successfully observed different SSEPs from left somatosensory cortex of a rat.

16-Channel biphasic current-mode programmable charge balanced neural stimulation

BACKGROUND

Neural stimulation is an important method used to activate or inhibit action potentials of the neuronal anatomical targets found in the brain, central nerve and peripheral nerve. The neural stimulator system produces biphasic pulses that deliver balanced charge into tissue from single or multichannel electrodes. The timing and amplitude of these biphasic pulses are precisely controlled by the neural stimulator software or imbedded algorithms. Amplitude mismatch between the anodic current and cathodic current of the biphasic pulse will cause permanently damage for the neural tissues. The main goal of our circuit and layout design is to implement a 16-channel biphasic current mode programmable neural stimulator with calibration to minimize the current mismatch caused by inherent complementary metal oxide semiconductor (CMOS) manufacturing processes.

METHODS

This paper presents a 16-channel constant current mode neural stimulator chip. Each channel consists of a 7-bit controllable current DAC used as sink and source current driver. To reduce the LSB quantization error and the current mismatch, an automatic calibration circuit and flow diagram is presented in this paper. There are two modes of operation of the stimulator chip-namely, stimulation mode and calibration mode. The chip also includes a digital interface used to control the stimulator parameters and calibration levels specific for each individual channel.

RESULTS

This stimulator Application Specific Integrated Circuit (ASIC) is designed and fabricated in a 0.18 μm High-Voltage CMOS technology that allows for ±20 V power supply. The full-scale stimulation current was designed to be at 1 mA per channel. The output current was shown to be constant throughout the timing cycles over a wide range of electrode load impedances. The calibration circuit was also designed to reduce the effect of CMOS process variation of the P-channel metal oxide semiconductor (PMOS) and N-channel metal oxide semiconductor (NMOS) devices that will result in charge delivery to have less than 0.13% error.

CONCLUSIONS

A 16-channel integrated biphasic neural stimulator chip with calibration is presented in this paper. The stimulator circuit design was simulated and the chip layout was completed. The chip layout was verified using design rules check (DRC) and layout versus schematic (LVS) design check using computer aided design (CAD) software. The test results we presented show constant current stimulation with charge balance error within 0.13% least-significant-bit (LSB). This LSB error was consistent throughout a variety stimulation patterns and electrode load impedances.

Recent Progress of Development of Optogenetic Implantable Neural Probes

As a cell type-specific neuromodulation method, optogenetic technique holds remarkable potential for the realisation of advanced neuroprostheses. By genetically expressing light-sensitive proteins such as channelrhodopsin-2 (ChR2) in cell membranes, targeted neurons could be controlled by light. This new neuromodulation technique could then be applied into extensive brain networks and be utilised to provide effective therapies for neurological disorders. However, the development of novel optogenetic implants is still a key challenge in the field. The major requirements include small device dimensions, suitable spatial resolution, high safety, and strong controllability. In this paper, I present a concise review of the significant progress that has been made towards achieving a miniaturised, multifunctional, intelligent optogenetic implant. I identify the key limitations of current technologies and discuss the possible opportunities for future development.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm ². The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

Robust Wireless Power Transmission to mm-Sized Free-Floating Distributed Implants

This paper presents an inductive link for wireless power transmission (WPT) to mm-sized free-floating implants (FFIs) distributed in a large three-dimensional space in the neural tissue that is insensitive to the exact location of the receiver (Rx). The proposed structure utilizes a high-Q resonator on the target wirelessly powered plane that encompasses randomly positioned multiple FFIs, all powered by a large external transmitter (Tx). Based on resonant WPT fundamentals, we have devised a detailed method for optimization of the FFIs and explored design strategies and safety concerns, such as coil segmentation and specific absorption rate limits using realistic finite element simulation models in HFSS including head tissue layers, respectively. We have built several FFI prototypes to conduct accurate measurements and to characterize the performance of the proposed WPT method. Measurement results on 1-mm receivers operating at 60 MHz show power transfer efficiency and power delivered to the load at 2.4% and 1.3 mW, respectively, within 14-18 mm of Tx-Rx separation and 7 cm² of brain surface.

High Density, High Radiance $\mu$ LED Matrix for Optogenetic Retinal Prostheses and Planar Neural Stimulation

Optical neuron stimulation arrays are important for both in-vitro biology and retinal prosthetic biomedical applications. Hence, in this work, we present an 8100 pixel high radiance photonic stimulator. The chip module vertically combines custom made gallium nitride μ LEDs with a CMOS application specific integrated circuit. This is designed with active pixels to ensure random access and to allow continuous illumination of all required pixels. The μLEDs have been assembled on the chip using a solder ball flip-chip bonding technique which has allowed for reliable and repeatable manufacture. We have evaluated the performance of the matrix by measuring the different factors including the static, dynamic power consumption, the illumination, and the current consumption by each LED. We show that the power consumption is within a range suitable for portable use. Finally, the thermal behavior of the matrix is monitored and the matrix proved to be thermally stable.

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor

This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

Electronic Sleep Stage Classifiers: A Survey and VLSI Design Methodology

First, existing sleep stage classifier sensors and algorithms are reviewed and compared in terms of classification accuracy, level of automation, implementation complexity, invasiveness, and targeted application. Next, the implementation of a miniature microsystem for low-latency automatic sleep stage classification in rodents is presented. The classification algorithm uses one EMG (electromyogram) and two EEG (electroencephalogram) signals as inputs in order to detect REM (rapid eye movement) sleep, and is optimized for low complexity and low power consumption. It is implemented in an on-board low-power FPGA connected to a multi-channel neural recording IC, to achieve low-latency (order of 1 ms or less) classification. Off-line experimental results using pre-recorded signals from nine mice show REM detection sensitivity and specificity of 81.69% and 93.86%, respectively, with the maximum latency of 39 [Formula: see text]. The device is designed to be used in a non-disruptive closed-loop REM sleep suppression microsystem, for future studies of the effects of REM sleep deprivation on memory consolidation.

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

This paper presents a 4 × V_DD neuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

A LOW TEMPERATURE INCREASE TRANSCUTANEOUS BATTERY CHARGER FOR IMPLANTABLE MEDICAL DEVICES

Many medical groups have used wireless battery charging technology for rechargeable batteries used in implantable devices. During charging, battery heat is lost from the battery and other heat sources within an implantable device, which may be harmful to patients’ tissues. Therefore, charging batteries with minimum discomfort to patients while replenishing battery capacity as much as possible is a challenge. In this paper, a constant voltage with a different limiting current strategy for a lithium-ion polymer battery is proposed, thereby modulating the limiting current rate that reduces battery temperature increase. Experiments show that better safety charging performance for 260, 600, and 1000[Formula: see text]mAh lithium-ion polymer batteries can be obtained by the proposed current-limiting method. Compared with conventional constant-current–constant-voltage charging strategies, the maximum battery temperature increase is improved.

A 200-Channel Area-Power-Efficient Chemical and Electrical Dual-Mode Acquisition IC for the Study of Neurodegenerative Diseases

Microelectrode array (MEA) can be used in the study of neurodegenerative diseases by monitoring the chemical neurotransmitter release and the electrical potential simultaneously at the cellular level. Currently, the MEA technology is migrating to more electrodes and higher electrode density, which raises power and area constraints on the design of acquisition IC. In this paper, we report the design of a 200-channel dual-mode acquisition IC with highly efficient usage of power and area. Under the constraints of target noise and fast settling, the current channel design saves power by including a novel current buffer biased in discrete time (DT) before the TIA (transimpedance amplifier). The 200 channels are sampled at 20 kS/s and quantized by column-wise SAR ADCs. The prototype IC was fabricated in a 0.18 μm CMOS process. Silicon measurements show the current channel has 21.6 pArms noise with cyclic voltammetry (CV) and 0.48 pArms noise with constant amperometry (CA) while consuming 12.1 μW . The voltage channel has 4.07 μVrms noise in the bandwidth of 100 kHz and 0.2% nonlinearity while consuming 9.1 μW. Each channel occupies 0.03 mm(2) area, which is among the smallest.

Active C4 Electrodes for Local Field Potential Recording Applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.

Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system

Understanding neural responses to multi-site electrical stimuli would be of essential importance for developing cortical neural prostheses. In order to provide a tool for such studies in experimental animals, we recently constructed a prototype of a wireless multi-channel microstimulation system, consisting of a stimulator chip, wireless data/power transmitters and receivers, and microcomputers. The proper operations of the system in cortical neural excitations were examined in anesthetized rats in vivo, with utilizing the voltage-sensitive dye imaging technique.