Transiently chaotic simulated annealing based on intrinsic nonlinearity of memristors for efficient solution of optimization problems

Brain-inspired chaotic spiking backpropagation

Spiking neural networks (SNNs) have superior energy efficiency due to their spiking signal transmission, which mimics biological nervous systems, but they are difficult to train effectively. Although surrogate gradient-based methods offer a workable solution, trained SNNs frequently fall into local minima because they are still primarily based on gradient dynamics. Inspired by the chaotic dynamics in animal brain learning, we propose a chaotic spiking backpropagation (CSBP) method that introduces a loss function to generate brain-like chaotic dynamics and further takes advantage of the ergodic and pseudo-random nature to make SNN learning effective and robust. From a computational viewpoint, we found that CSBP significantly outperforms current state-of-the-art methods on both neuromorphic data sets (e.g. DVS-CIFAR10 and DVS-Gesture) and large-scale static data sets (e.g. CIFAR100 and ImageNet) in terms of accuracy and robustness. From a theoretical viewpoint, we show that the learning process of CSBP is initially chaotic, then subject to various bifurcations and eventually converges to gradient dynamics, consistently with the observation of animal brain activity. Our work provides a superior core tool for direct SNN training and offers new insights into understanding the learning process of a biological brain.

MEMS Oscillators-Network-Based Ising Machine with Grouping Method

Combinatorial optimization (CO) has a broad range of applications in various fields, including operations research, computer science, and artificial intelligence. However, many of these problems are classified as nondeterministic polynomial-time (NP)-complete or NP-hard problems, which are known for their computational complexity and cannot be solved in polynomial time on traditional digital computers. To address this challenge, continuous-time Ising machine solvers have been developed, utilizing different physical principles to map CO problems to ground state finding. However, most Ising machine prototypes operate at speeds comparable to digital hardware and rely on binarizing node states, resulting in increased system complexity and further limiting operating speed. To tackle these issues, a novel device-algorithm co-design method is proposed for fast sub-optimal solution finding with low hardware complexity. On the device side, a piezoelectric lithium niobate (LiNbO3) microelectromechanical system (MEMS) oscillator network-based Ising machine without second-harmonic injection locking (SHIL) is devised to solve Max-cut and graph coloring problems. The LiNbO3 oscillator operates at speeds greater than 9 GHz, making it one of the fastest oscillatory Ising machines. System-wise, an innovative grouping method is used that achieves a performance guarantee of 0.878 for Max-cut and 0.658 for graph coloring problems, which is comparable to Ising machines that utilize binarization.

Oscillatory Neural Network-Based Ising Machine Using 2D Memristors

Neural networks are increasingly used to solve optimization problems in various fields, including operations research, design automation, and gene sequencing. However, these networks face challenges due to the nondeterministic polynomial time (NP)-hard issue, which results in exponentially increasing computational complexity as the problem size grows. Conventional digital hardware struggles with the von Neumann bottleneck, the slowdown of Moore's law, and the complexity arising from heterogeneous system design. Two-dimensional (2D) memristors offer a potential solution to these hardware challenges, with their in-memory computing, decent scalability, and rich dynamic behaviors. In this study, we explore the use of nonvolatile 2D memristors to emulate synapses in a discrete-time Hopfield neural network, enabling the network to solve continuous optimization problems, like finding the minimum value of a quadratic polynomial, and tackle combinatorial optimization problems like Max-Cut. Additionally, we coupled volatile memristor-based oscillators with nonvolatile memristor synapses to create an oscillatory neural network-based Ising machine, a continuous-time analog dynamic system capable of solving combinatorial optimization problems including Max-Cut and map coloring through phase synchronization. Our findings demonstrate that 2D memristors have the potential to significantly enhance the efficiency, compactness, and homogeneity of integrated Ising machines, which is useful for future advances in neural networks for optimization problems.

Ferroelectric compute-in-memory annealer for combinatorial optimization problems

Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications. Various digital annealers, dynamical Ising machines, and quantum/photonic systems have been developed for solving COPs, but they still suffer from the memory access issue, scalability, restricted applicability to certain types of COPs, and VLSI-incompatibility, respectively. Here we report a ferroelectric field effect transistor (FeFET) based compute-in-memory (CiM) annealer for solving larger-scale COPs efficiently. Our CiM annealer converts COPs into quadratic unconstrained binary optimization (QUBO) formulations, and uniquely accelerates in-situ the core vector-matrix-vector (VMV) multiplication operations of QUBO formulations in a single step. Specifically, the three-terminal FeFET structure allows for lossless compression of the stored QUBO matrix, achieving a remarkably 75% chip size saving when solving Max-Cut problems. A multi-epoch simulated annealing (MESA) algorithm is proposed for efficient annealing, achieving up to 27% better solution and ~ 2X speedup than conventional simulated annealing. Experimental validation is performed using the first integrated FeFET chip on 28nm HKMG CMOS technology, indicating great promise of FeFET CiM array in solving general COPs.

Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar

Combinatorial optimization problems are prevalent in various fields, but obtaining exact solutions remains challenging due to the combinatorial explosion with increasing problem size. Special-purpose hardware such as Ising machines, particularly memristor-based analog Ising machines, have emerged as promising solutions. However, existing simulate-annealing-based implementations have not fully exploited the inherent parallelism and analog storage/processing features of memristor crossbar arrays. This work proposes a quantum-inspired parallel annealing method that enables full parallelism and improves solution quality, resulting in significant speed and energy improvement when implemented in analog memristor crossbars. We experimentally solved tasks, including unweighted and weighted Max-Cut and traveling salesman problem, using our integrated memristor chip. The quantum-inspired parallel annealing method implemented in memristor-based hardware has demonstrated significant improvements in time- and energy-efficiency compared to previously reported simulated annealing and Ising machine implemented on other technologies. This is because our approach effectively exploits the natural parallelism, analog conductance states, and all-to-all connection provided by memristor technology, promising its potential for solving complex optimization problems with greater efficiency.

Artificial neural network model- and response surface methodology-based optimization of Atractylodis Macrocephalae Rhizoma polysaccharide extraction, kinetic modelling and structural characterization

Atractylodis Macrocephalae Rhizoma (AMR) is the dried rhizome of Atractylodes macrocephala Koidz, which is widely used in the development of health products. AMR contains a large number of polysaccharides, but at present there are fewer applications for these polysaccharides. In this study, the effects of different extraction methods on the Atractylodis Macrocephalae Rhizoma polysaccharide (AMRP) yield were investigated, and the conditions for ultrasound-assisted extraction were optimized by response surface methodology (RSM) and three neural network models (BP neural network, GA-BP neural network and ACO-GA-BP neural network). The best conditions were a liquid-to-solid ratio of 17 mL/g, ultrasonic power of 400 W, extraction temperature of 72 °C, and extraction time of 40 min, which yielded 31.31% AMRP. The kinetic equation of AMRP was determined and compared with the results predicted by three neural network models. It was finally determined that the extraction conditions, kinetic processes and kinetic equation predicted by the GA-ACO-BP neural network were optimal. In addition, AMRP was characterized using SEM, FTIR, HPLC, UV, XRD, and NMR, and the structural study revealed that AMRP has a rough exterior and a porous interior; moreover, it contains high levels of glucose (5.07%), arabinose (0.80%), and galactose (0.74%). AMRP has three crystal structures, consisting of two β-type monosaccharides and one α-type monosaccharide. Additionally, the effectiveness of AMRP as an antioxidant was demonstrated in an in vitro experiment.

In-memory factorization of holographic perceptual representations

Disentangling the attributes of a sensory signal is central to sensory perception and cognition and hence is a critical task for future artificial intelligence systems. Here we present a compute engine capable of efficiently factorizing high-dimensional holographic representations of combinations of such attributes, by exploiting the computation-in-superposition capability of brain-inspired hyperdimensional computing, and the intrinsic stochasticity associated with analogue in-memory computing based on nanoscale memristive devices. Such an iterative in-memory factorizer is shown to solve at least five orders of magnitude larger problems that cannot be solved otherwise, as well as substantially lowering the computational time and space complexity. We present a large-scale experimental demonstration of the factorizer by employing two in-memory compute chips based on phase-change memristive devices. The dominant matrix-vector multiplication operations take a constant time, irrespective of the size of the matrix, thus reducing the computational time complexity to merely the number of iterations. Moreover, we experimentally demonstrate the ability to reliably and efficiently factorize visual perceptual representations.

A review of memristor: material and structure design, device performance, applications and prospects

With the booming growth of artificial intelligence (AI), the traditional von Neumann computing architecture based on complementary metal oxide semiconductor devices are facing memory wall and power wall. Memristor based in-memory computing can potentially overcome the current bottleneck of computer and achieve hardware breakthrough. In this review, the recent progress of memory devices in material and structure design, device performance and applications are summarized. Various resistive switching materials, including electrodes, binary oxides, perovskites, organics, and two-dimensional materials, are presented and their role in the memristor are discussed. Subsequently, the construction of shaped electrodes, the design of functional layer and other factors influencing the device performance are analyzed. We focus on the modulation of the resistances and the effective methods to enhance the performance. Furthermore, synaptic plasticity, optical-electrical properties, the fashionable applications in logic operation and analog calculation are introduced. Finally, some critical issues such as the resistive switching mechanism, multi-sensory fusion, system-level optimization are discussed.

Echo state graph neural networks with analogue random resistive memory arrays

Recent years have witnessed a surge of interest in learning representations of graph-structured data, with applications from social networks to drug discovery. However, graph neural networks, the machine learning models for handling graph-structured data, face significant challenges when running on conventional digital hardware, including the slowdown of Moore’s law due to transistor scaling limits and the von Neumann bottleneck incurred by physically separated memory and processing units, as well as a high training cost. Here we present a hardware–software co-design to address these challenges, by designing an echo state graph neural network based on random resistive memory arrays, which are built from low-cost, nanoscale and stackable resistors for efficient in-memory computing. This approach leverages the intrinsic stochasticity of dielectric breakdown in resistive switching to implement random projections in hardware for an echo state network that effectively minimizes the training complexity thanks to its fixed and random weights. The system demonstrates state-of-the-art performance on both graph classification using the MUTAG and COLLAB datasets and node classification using the CORA dataset, achieving 2.16×, 35.42× and 40.37× improvements in energy efficiency for a projected random resistive memory-based hybrid analogue–digital system over a state-of-the-art graphics processing unit and 99.35%, 99.99% and 91.40% reductions of backward pass complexity compared with conventional graph learning. The results point to a promising direction for next-generation artificial intelligence systems for graph learning.

A Ferroelectric Memristor-Based Transient Chaotic Neural Network for Solving Combinatorial Optimization Problems

A transient chaotic neural network (TCNN) is particularly useful for solving combinatorial optimization problems, and its hardware implementation based on memristors has attracted great attention recently. Although previously used filamentary memristors could provide the desired nonlinearity for implementing the annealing function of a TCNN, the controllability of filamentary switching still remains relatively poor, thus limiting the performance of a memristor-based TCNN. Here, we propose to use ferroelectric memristor to implement the annealing function of a TCNN. In the ferroelectric memristor, the conductance can be tuned by switching the lattice non-centrosymmetry-induced polarization, which is a nonlinear switching mechanism with high controllability. We first establish a ferroelectric memristor model based on a ferroelectric tunnel junction (FTJ), which exhibits the polarization-modulated tunnel conductance and the nucleation-limited-switching (NLS) behavior. Then, the conductance of the ferroelectric memristor is used as the self-feedback connection weight that can be dynamically adjusted. Based on this, a ferroelectric memristor-based transient chaotic neural network (FM-TCNN) is further constructed and applied to solve the traveling salesman problem (TSP). In 1000 runs for 10-city TSP, the FM-TCNN achieves a shorter average path distance, a 32.8% faster convergence speed, and a 2.44% higher global optimal rate than the TCNN.

Toward memristive in-memory computing: principles and applications

With the rapid growth of computer science and big data, the traditional von Neumann architecture suffers the aggravating data communication costs due to the separated structure of the processing units and memories. Memristive in-memory computing paradigm is considered as a prominent candidate to address these issues, and plentiful applications have been demonstrated and verified. These applications can be broadly categorized into two major types: soft computing that can tolerant uncertain and imprecise results, and hard computing that emphasizes explicit and precise numerical results for each task, leading to different requirements on the computational accuracies and the corresponding hardware solutions. In this review, we conduct a thorough survey of the recent advances of memristive in-memory computing applications, both on the soft computing type that focuses on artificial neural networks and other machine learning algorithms, and the hard computing type that includes scientific computing and digital image processing. At the end of the review, we discuss the remaining challenges and future opportunities of memristive in-memory computing in the incoming Artificial Intelligence of Things era.

Phase-change memtransistive synapses for mixed-plasticity neural computations

In the mammalian nervous system, various synaptic plasticity rules act, either individually or synergistically, over wide-ranging timescales to enable learning and memory formation. Hence, in neuromorphic computing platforms, there is a significant need for artificial synapses that can faithfully express such multi-timescale plasticity mechanisms. Although some plasticity rules have been emulated with elaborate complementary metal oxide semiconductor and memristive circuitry, device-level hardware realizations of long-term and short-term plasticity with tunable dynamics are lacking. Here we introduce a phase-change memtransistive synapse that leverages both the non-volatility of the phase configurations and the volatility of field-effect modulation for implementing tunable plasticities. We show that these mixed-plasticity synapses can enable plasticity rules such as short-term spike-timing-dependent plasticity that helps with the modelling of dynamic environments. Further, we demonstrate the efficacy of the memtransistive synapses in realizing accelerators for Hopfield neural networks for solving combinatorial optimization problems.

In-Memory Realization of Eligibility Traces Based on Conductance Drift of Phase Change Memory for Energy-Efficient Reinforcement Learning

Reinforcement learning (RL) has shown outstanding performance in handling complex tasks in recent years. Eligibility trace (ET), a fundamental and important mechanism in reinforcement learning, records critical states with attenuation and guides the update of policy, which plays a crucial role in accelerating the convergence of RL training. However, ET implementation on conventional digital computing hardware is energy hungry and restricted by the memory wall due to massive calculation of exponential decay functions. Here, in-memory realization of ET for energy-efficient reinforcement learning with outstanding performance in discrete- and continuous-state RL tasks is demonstrated. For the first time, the inherent conductance drift of phase change memory is exploited as physical decay function to realize in-memory eligibility trace, demonstrating excellent performance during RL training in various tasks. The spontaneous in-memory decay computing and storage of policy in the same phase change memory give rise to significantly enhanced energy efficiency compared with traditional graphics processing unit platforms. This work therefore provides a holistic energy and hardware efficient method for both training and inference of reinforcement learning.

An Annealing Accelerator for Ising Spin Systems Based on In-Memory Complementary 2D FETs

Metaheuristic algorithms such as simulated annealing (SA) are often implemented for optimization in combinatorial problems, especially for discreet problems. SA employs a stochastic search, where high-energy transitions ("hill-climbing") are allowed with a temperature-dependent probability to escape local optima. Ising spin glass systems have properties such as spin disorder and "frustration" and provide a discreet combinatorial problem with a high number of metastable states and ground-state degeneracy. In this work, subthreshold Boltzmann transport is exploited in complementary 2D field-effect transistors (p-type WSe₂ and n-type MoS₂ ) integrated with an analog, nonvolatile, and programmable floating-gate memory stack to develop in-memory computing primitives necessary for energy- and area-efficient hardware acceleration of SA for Ising spin systems. Search acceleration of >800× is demonstrated for 4 × 4 ferromagnetic, antiferromagnetic, and spin glass systems using SA compared to an exhaustive search using a brute force trial at miniscule total energy expenditure of ≈120 nJ. The hardware-realistic numerical simulations further highlight the astounding benefits of SA in accelerating the search for larger spin lattices.

Application of mathematical morphology operation with memristor-based computation-in-memory architecture for detecting manufacturing defects

Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis. These data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units (CPUs) and graphics processing units (GPUs). Computation-in-memory (CIM) provides a possible solution for highly efficient morphology operations. In this study, we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromorphic computation on a multi-array-based memristor system. Pixel-by-pixel logic computations with low parallelism are converted to parallel operations using memristors. Moreover, hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit (IC) manufacturing and medical image analysis. In addition, we developed a new implementation scheme employing a four-layer network to realize small-object detection with high parallelism. The system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed, respectively, exhibiting the advantage of the proposed memristor-based morphology operation.

Global minimization via classical tunneling assisted by collective force field formation

Simple elements interacting in networks can give rise to intricate emergent behaviors. Examples such as synchronization and phase transitions often apply in many contexts, as many different systems may reduce to the same effective model. Here, we demonstrate such a behavior in a model inspired by memristors. When weakly driven, the system is described by movement in an effective potential, but when strongly driven, instabilities cause escapes from local minima, which can be interpreted as an unstable tunneling mechanism. We dub this collective and nonperturbative effect a “Lyapunov force,” which steers the system toward the global minimum of the potential function, even if the full system has a constellation of equilibrium points growing exponentially with the system size. This mechanism is appealing for its physical relevance in nanoscale physics and for its possible applications in optimization, Monte Carlo schemes, and machine learning.

Stochastic Spiking Behavior in Neuromorphic Networks Enables True Random Number Generation

There is currently a great deal of interest in the use of nanoscale devices to emulate the behaviors of neurons and synapses and to facilitate brain-inspired computation. Here, it is shown that percolating networks of nanoparticles exhibit stochastic spiking behavior that is strikingly similar to that observed in biological neurons. The spiking rate can be controlled by the input stimulus, similar to "rate coding" in biology, and the distributions of times between events are log-normal, providing insights into the atomic-scale spiking mechanism. The stochasticity of the spiking behavior is then used for true random number generation, and the high quality of the generated random bit-streams is demonstrated, opening up promising routes toward integration of neuromorphic computing with secure information processing.

Reconfigurable Stochastic neurons based on tin oxide/MoS2 hetero-memristors for simulated annealing and the Boltzmann machine

Neuromorphic hardware implementation of Boltzmann Machine using a network of stochastic neurons can allow non-deterministic polynomial-time (NP) hard combinatorial optimization problems to be efficiently solved. Efficient implementation of such Boltzmann Machine with simulated annealing desires the statistical parameters of the stochastic neurons to be dynamically tunable, however, there has been limited research on stochastic semiconductor devices with controllable statistical distributions. Here, we demonstrate a reconfigurable tin oxide (SnO_x)/molybdenum disulfide (MoS₂) heterogeneous memristive device that can realize tunable stochastic dynamics in its output sampling characteristics. The device can sample exponential-class sigmoidal distributions analogous to the Fermi-Dirac distribution of physical systems with quantitatively defined tunable "temperature" effect. A BM composed of these tunable stochastic neuron devices, which can enable simulated annealing with designed "cooling" strategies, is conducted to solve the MAX-SAT, a representative in NP-hard combinatorial optimization problems. Quantitative insights into the effect of different "cooling" strategies on improving the BM optimization process efficiency are also provided.