Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels

In this study, we investigate the gate-bias stability of triple-gated feedback field-effect transistors (FBFETs) with Si nanosheet channels. The subthreshold swing (SS) of FBFETs increases from 0.3 mV dec-1to 60 and 80 mV dec-1inp- andn-channel modes, respectively, when a positive bias stress (PBS) is applied for 1000 s. In contrast, the SS value does not change even after a negative bias stress (NBS) is applied for 1000 s. The difference in the switching characteristics under PBS and NBS is attributed to the ability of the interface traps to readily gain electrons from the inversion layer. The switching characteristics deteriorated by PBS are completely recovered after annealing at 300 °C for 10 min, and the characteristics remain stable even after PBS is applied again for 1000 s.

Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning

In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current-voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.

Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.