Tunable defect engineering of Mo/TiON electrode in angstrom-laminated HfO2/ZrO2ferroelectric capacitors towards long endurance and high temperature retention

A novel defect control approach based on laminated HfO2/ZrO2with multifunctional TiN/Mo/TiOxNyelectrode is proposed to significantly improve the endurance and data retention in HZO-based ferroelectric capacitor. The O-rich interface reduces leakage current and prolong the endurance up to 1011cycles while retaining a 2Pr value of 34 (μC cm-2) at 3.4 MV cm-1. Using first-principles calculations and experiments, we demonstrate that the enhancement of endurance is ascribed to the higher migration barrier of oxygen vacancies within the laminated HZO film and higher work function of MoOx/TiOxNybetween top electrode and the insulating oxide. This 2.5 nm thick TiOxNybarrier further increase the grain size of HZO, lowering the activation field and thus improving polarization reversal speed. This interfacial layer further decreases the overall capacitance, increases the depolarization field, thereby enhancing the data retention. By fitting the data using the Arrhenius equation, we demonstrate a 10 years data retention is achieved at 109.6 °C, surpassing traditional SS-HZO of 78.2 °C with a 450 °C rapid thermal annealing (required by backend-of-the-line). This work elucidates that interfacial engineering serves as a crucial technology capable of resolving the endurance, storage capability, and high-temperature data retention issues for ferroelectric memory.

Liquid Metal Doping Induced Asymmetry in Two-Dimensional Metal Oxides

The emergence of ferroelectricity in two-dimensional (2D) metal oxides is a topic of significant technological interest; however, many 2D metal oxides lack intrinsic ferroelectric properties. Therefore, introducing asymmetry provides access to a broader range of 2D materials within the ferroelectric family. Here, the generation of asymmetry in 2D SnO by doping the material with Hf0.5 Zr0.5 O2 (HZO) is demonstrated. A liquid metal process as a doping strategy for the preparation of 2D HZO-doped SnO with robust ferroelectric characteristics is implemented. This technology takes advantage of the selective interface enrichment of molten Sn with HZO crystallites. Molecular dynamics simulations indicate a strong tendency of Hf and Zr atoms to migrate toward the surface of liquid metal and embed themselves within the growing oxide layer in the form of HZO. Thus, the liquid metal-based harvesting/doping technique is a feasible approach devised for producing novel 2D metal oxides with induced ferroelectric properties, represents a significant development for the prospects of random-access memories.

Effect of a ZrO2 Seed Layer on an Hf0.5Zr0.5O2 Ferroelectric Device Fabricated via Plasma Enhanced Atomic Layer Deposition

In this study, a ferroelectric layer was formed on a ferroelectric device via plasma enhanced atomic layer deposition. The device used 50 nm thick TiN as upper and lower electrodes, and an Hf_0.5Zr_0.5O₂ (HZO) ferroelectric material was applied to fabricate a metal-ferroelectric-metal-type capacitor. HZO ferroelectric devices were fabricated in accordance with three principles to improve their ferroelectric properties. First, the HZO nanolaminate thickness of the ferroelectric layers was varied. Second, heat treatment was performed at 450, 550, and 650 °C to investigate the changes in the ferroelectric characteristics as a function of the heat-treatment temperature. Finally, ferroelectric thin films were formed with or without seed layers. Electrical characteristics such as the I-E characteristics, P-E hysteresis, and fatigue endurance were analyzed using a semiconductor parameter analyzer. The crystallinity, component ratio, and thickness of the nanolaminates of the ferroelectric thin film were analyzed via X-ray diffraction, X-ray photoelectron spectroscopy, and transmission electron microscopy. The residual polarization of the (20,20)*3 device heat treated at 550 °C was 23.94 μC/cm², whereas that of the D(20,20)*3 device was 28.18 μC/cm², which improved the characteristics. In addition, in the fatigue endurance test, the wake-up effect was observed in specimens with bottom and dual seed layers, which exhibited excellent durability after 10⁸ cycles.

Characteristics of Hf0.5Zr0.5O2 Thin Films Prepared by Direct and Remote Plasma Atomic Layer Deposition for Application to Ferroelectric Memory

Hf_0.5Zr_0.5O₂ (HZO) thin film exhibits ferroelectric properties and is presumed to be suitable for use in next-generation memory devices because of its compatibility with the complementary metal-oxide-semiconductor (CMOS) process. This study examined the physical and electrical properties of HZO thin films deposited by two plasma-enhanced atomic layer deposition (PEALD) methods- direct plasma atomic layer deposition (DPALD) and remote plasma atomic layer deposition (RPALD)-and the effects of plasma application on the properties of HZO thin films. The initial conditions for HZO thin film deposition, depending on the RPALD deposition temperature, were established based on previous research on HZO thin films deposited by the DPALD method. The results show that as the measurement temperature increases, the electric properties of DPALD HZO quickly deteriorate; however, the RPALD HZO thin film exhibited excellent fatigue endurance at a measurement temperature of 60 °C or less. HZO thin films deposited by the DPALD and RPALD methods exhibited relatively good remanent polarization and fatigue endurance, respectively. These results confirm the applicability of the HZO thin films deposited by the RPALD method as ferroelectric memory devices.

Steep-Slope Transistor with an Imprinted Antiferroelectric Film

The effect of negative capacitance (NC), which can internally boost the voltage applied to a transistor, has been considered to overcome the fundamental Boltzmann limit of a transistor. To stabilize the NC effect, the dielectric (DE) must be integrated into a heterostructure with a ferroelectric (FE) film. However, in a multidomain hafnia, the charge boosting effect is reduced owing to a lowering of the depolarization field originating from the stray field at each domain, and simultaneously, the operating voltage increases owing to the voltage division at the DE. Here, we demonstrate core approaches to the gate stack of energy-efficient device technology using a transient NC. Electrical measurements of the transistor with imprinted antiferroelectric and high C_DE/C_FE structures exhibit low subthreshold slopes below 20 mV/dec, a low voltage operation of 0.5 V, a fast operation of 20 ns, hysteresis-free I_d-V_g, and high endurance characteristics of 10¹² cycles. We expect that this will lead to the rapid implementation of the NC effect in high-speed switching device applications with significantly improved energy efficiency.

Evolution of the Interfacial Layer and Its Impact on Electric-Field-Cycling Behaviors in Ferroelectric Hf1-xZrxO2

Doped HfO₂ thin films, which exhibit robust ferroelectricity even with aggressive thickness scaling, could potentially enable ultralow-power logic and memory devices. The ferroelectric properties of such materials are strongly intertwined with the voltage-cycling-induced electrical and structural changes, leading to wake-up and fatigue effects. Such field-cycling-dependent behaviors are crucial to evaluate the reliability of HfO₂-based functional devices; however, its genuine nature remains elusive. Herein, we demonstrate the coupling mechanism between the dynamic change of the interfacial layer and wake-up/fatigue phenomena in ferroelectric Hf_1-xZr_xO₂ (HZO) thin films. Comprehensive atomic-resolution microscopy studies have revealed that the interfacial layer between the HZO and neighboring nonoxide electrode experienced a thickness/composition evolution during electrical cycling. Two theoretical models associated with the depolarization field are adopted, giving consistent results with the thickening of the interfacial layer during electrical cycling. Furthermore, we found that the electrical properties of the HZO devices can be manipulated by controlling the interface properties, e.g., through the choice of electrode match and hybrid cycling process. Our results unambiguously reveal the relationship between the interfacial layer and field-cycling behaviors in HZO, which would further permit the reliability improvement in HZO-based ferroelectric devices through interface engineering.

Flexible Ferroelectric Hafnia-Based Synaptic Transistor by Focused-Microwave Annealing

Hafnia-based ferroelectric memory devices with excellent ferroelectricity, low power consumption, and fast operation speed have attracted considerable interest with the ever-growing desire for nonvolatile memory in flexible electronics. However, hafnia films are required to perform a high temperature (>500 °C) annealing process for crystallization into the ferroelectric orthorhombic phase. It can hinder the integration of hafnia ferroelectric films on flexible substrates including plastic and polymer, which are not endurable at high temperatures above 300 °C. Here, we propose the extremely low-temperature (∼250 °C) process for crystallization of Hf_0.5Zr_0.5O₂ (HZO) thin films by applying a focused-microwave induced annealing method. HZO thin films on a flexible mica substrate exhibits robust remnant polarization (2P_r ∼ 50 μC/cm²), which is negligibly changed under bending tests. In addition, the electrical characteristics of a HZO capacitor on the mica substrate were evaluated, and ferroelectric thin film transistors (Fe-TFTs), using a HZO gate insulator, were fabricated on mica substrates for flexible synapse applications. Symmetric potentiation and depression characteristics are successfully demonstrated in the Fe-TFT memory devices, and the synaptic devices result in high recognition accuracy of 91.44%. The low-temperature annealing method used in this work are promising for forming hafnia-based Fe-TFT memory devices as a building block on a flexible platform.

Selector-less Ferroelectric Tunnel Junctions by Stress Engineering and an Imprinting Effect for High-Density Cross-Point Synapse Arrays

In the quest for highly scalable and three-dimensional (3D) stackable memory components, ferroelectric tunnel junction (FTJ) crossbar architectures are promising technologies for nonvolatile logic and neuromorphic computing. Most FTJs, however, require additional nonlinear devices to suppress sneak-path current, limiting large-scale arrays in practical applications. Moreover, the giant tunneling electroresistance (TER) remains challenging due to their inherent weak polarization. Here, we present that the employment of a diffusion barrier layer as well as a bottom metal electrode having a significantly low thermal expansion coefficient has been identified as an important way to enhance the strain, stabilize the ferroelectricity, and manage the leakage current in ultrathin hafnia film, achieving a high TER of 100, negligible resistance changes even up to 10⁸ cycles, and a high switching speed of a few tens of nanoseconds. Also, we demonstrate that the usage of an imprinting effect in a ferroelectric capacitor induced by an ionized oxygen vacancy near the electrode results in highly asymmetric current-voltage characteristics with a rectifying ratio of 1000. Notably, the proposed FTJ exhibits a high density array size (>4k) with a securing read margin of 10%. These findings provide a guideline for the design of high-performance and selector-free FTJ devices for large-scale crossbar arrays in neuromorphic applications.

Artificial Synapses Based on Ferroelectric Schottky Barrier Field-Effect Transistors for Neuromorphic Applications

Artificial synapses based on ferroelectric Schottky barrier field-effect transistors (FE-SBFETs) are experimentally demonstrated. The FE-SBFETs employ single-crystalline NiSi₂ contacts with an atomically flat interface to Si and Hf_0.5Zr_0.5O₂ ferroelectric layers on silicon-on-insulator substrates. The ferroelectric polarization switching dynamics gradually modulate the NiSi₂/Si Schottky barriers and the potential of the channel, thus programming the device conductance with input voltage pulses. The short-term synaptic plasticity is characterized in terms of excitatory/inhibitory post-synaptic current (EPSC) and paired-pulse facilitation/depression. The EPSC amplitude shows a linear response to the amplitude of the pre-synaptic spike. Very low energy/spike consumption as small as ∼2 fJ is achieved, demonstrating high energy efficiency. Long-term potentiation/depression results show very high endurance and very small cycle-to-cycle variations (∼1%) after 10⁵ pulse measurements. Furthermore, spike-timing-dependent plasticity is also emulated using the gate voltage pulse as the pre-synaptic spike and the drain voltage pulse as the post-synaptic spikes. These findings indicate that FE-SBFET synapses have high potential for future neuromorphic computing applications.

Low Voltage Operating 2D MoS2 Ferroelectric Memory Transistor with Hf1-xZrxO2 Gate Structure

Ferroelectric field effect transistor (FeFET) emerges as an intriguing non-volatile memory technology due to its promising operating speed and endurance. However, flipping the polarization requires a high voltage compared with that of reading, impinging the power consumption of writing a cell. Here, we report a CMOS compatible FeFET cell with low operating voltage. We engineer the ferroelectric Hf_1-xZr_xO₂ (HZO) thin film to form negative capacitance (NC) gate dielectrics, which generates a counterclock hysteresis loop of polarization domain in the few-layered molybdenum disulfide (MoS₂) FeFET. The unstabilized negative capacitor inherently supports subthermionic swing rate and thus enables switching the ferroelectric polarization with the hysteresis window much less than half of the operating voltage. The FeFET shows a high on/off current ratio of more than 10⁷ and a counterclockwise memory window (MW) of 0.1 V at a miminum program (P)/erase (E) voltage of 3 V. Robust endurance (10³ cycles) and retention (10⁴ s) properties are also demonstrated. Our results demonstrate that the HZO/MoS₂ ferroelectric memory transistor can achieve new opportunities in size- and voltage-scalable non-volatile memory applications.

Sustained Sub-60 mV/decade Switching via the Negative Capacitance Effect in MoS2 Transistors

It has been shown that a ferroelectric material integrated into the gate stack of a transistor can create an effective negative capacitance (NC) that allows the device to overcome "Boltzmann tyranny". While this switching below the thermal limit has been observed with Si-based NC field-effect transistors (NC-FETs), the adaptation to 2D materials would enable a device that is scalable in operating voltage as well as size. In this work, we demonstrate sustained sub-60 mV/dec switching, with a minimum subthreshold swing (SS) of 6.07 mV/dec (average of 8.03 mV/dec over 4 orders of magnitude in drain current), by incorporating hafnium zirconium oxide (HfZrO₂ or HZO) ferroelectric into the gate stack of a MoS₂ 2D-FET. By first fabricating and characterizing metal-ferroelectric-metal capacitors, the MoS₂ is able to be transferred directly on top and characterized with both a standard and a negative capacitance gate stack. The 2D NC-FET exhibited marked enhancement in low-voltage switching behavior compared to the 2D-FET on the same MoS₂ channel, reducing the SS by 2 orders of magnitude. A maximum internal voltage gain of ∼28× was realized with ∼12 nm thick HZO. Several unique dependencies were observed, including threshold voltage (V_th) shifts in the 2D NC-FET (compared to the 2D-FET) that correlate with source/drain overlap capacitance and changes in HZO (ferroelectric) and HfO₂ (dielectric) thicknesses. Remarkable sub-60 mV/dec switching was obtained from 2D NC-FETs of various sizes and gate stack thicknesses, demonstrating great potential for enabling size- and voltage-scalable transistors.