Review of Semiconductor Flash Memory Devices for Material and Process Issues

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.

Perspectives of Ferroelectric Wurtzite AlScN: Material Characteristics, Preparation, and Applications in Advanced Memory Devices

Ferroelectric, phase-change, and magnetic materials are considered promising candidates for advanced memory devices. Under the development dilemma of traditional silicon-based memory devices, ferroelectric materials stand out due to their unique polarization properties and diverse manufacturing techniques. On the occasion of the 100th anniversary of the birth of ferroelectricity, scandium-doped aluminum nitride, which is a different wurtzite structure, was reported to be ferroelectric with a larger coercive, remanent polarization, curie temperature, and a more stable ferroelectric phase. The inherent advantages have attracted widespread attention, promising better performance when used as data storage materials and better meeting the needs of the development of the information age. In this paper, we start from the characteristics and development history of ferroelectric materials, mainly focusing on the characteristics, preparation, and applications in memory devices of ferroelectric wurtzite AlScN. It compares and analyzes the unique advantages of AlScN-based memory devices, aiming to lay a theoretical foundation for the development of advanced memory devices in the future.

Chemisorption of silicon tetrachloride on silicon nitride: a density functional theory study

We studied the chemisorption of silicon tetrachloride (SiCl4) on the NH2/NH-terminated silicon nitride slab model using density functional theory (DFT) for atomic layer deposition (ALD) of silicon nitride. Initially, two reaction pathways were compared, forming HCl or NH3+Cl- as a byproduct. The NH3+Cl- complex formation was more exothermic than the HCl formation, with an activation energy of 0.26 eV. The -NH2* reaction sites are restored by desorption of HCl from the NH3+Cl- complexes at elevated temperatures of 205 °C or higher. Next, three sequential ligand exchange reactions forming Si-N bonds were modeled and simulated. The reaction energies became progressively less exothermic as the reaction progressed, from -1.31 eV to -0.30 eV to 0.98 eV, due to the stretching of Si-N bonds and the distortion of the N-Si-N bond angles. Also, the activation energies for the second and third reactions were 2.17 eV and 1.55 eV, respectively, significantly higher than the 0.26 eV of the first reaction, mainly due to the additional dissociation of the N-H bond. The third Si-N bond formation is unfavorable due to the endothermic reaction and higher activation energy. Therefore, the chemisorbed species would be -SiCl2* when the surface is exposed to SiCl4.

Switchable Chemical-Bond Reorganization for the Stable Charge Trapping in Amorphous Silicon Nitride

Despite the widespread use of charge-trap flash (CTF) memory, the atomistic mechanism behind the exceptionally stable charge storage at the localized trap sites is still controversial. Herein, by combining first-principles calculations and orbital interaction analysis, a charge-dependent switchable chemical-bond reorganization is elucidated as the underpinning chemistry in the working mechanism of CTF. Especially, positively charged fourfold-coordinated nitrogen (dubbed N+ center), unappreciated until now, is the decisive component of the entire process; once an electron occupies this site, the N+ center disappears by breaking one N─Si bond, simultaneously forming a new Si─Si bond with a nearby Si atom which, in turn, creates fivefold coordinated Si. As a result, the electron is stored in a multi-center orbital belonging to multiple atoms including the newly formed Si─Si bond. It is also observed that hole trapping accompanies the creation of an N+ center by forming a new N─Si bond, which represents the reverse process. To further support and validate this model by means of core-level calculations, it is also shown that an N+ center's 1s core level is 1.0-2.5 eV deeper in energy than those of the threefold coordinated N atoms, in harmony with experimental X-ray photoelectron spectroscopy data.

Light-Mediated Multilevel Flexible High-Efficiency Perovskite Resistive Switching Memory Based on Mn:CsPbCl3 Nanocrystals

Herein, the electrical characteristics, photoelectric properties, resistive switching (RS) mechanism, and flexible storage application of Ag/PMMA&Mn:CsPbCl3/ITO (PMMA = poly(methyl methacrylate)) devices are studied by using the photoelectric material Mn:CsPbCl3 nanocrystals (NCs) embedded in PMMA as the RS layer. The devices exhibit bipolar RS behavior with low operating voltage, excellent cycling endurance (>1000 times), long retention time (≥104 s), high ON/OFF ratio (≈104), and good environmental stability. The flexible memory devices have demonstrated reliable mechanical stability of consecutive 1000 bending cycles. In addition, multilevel data storage is realized by introducing the UV light, and the adjustive resistive switching characteristics is achieved through photoelectric synergistic work. The resistive switching mechanism under the excitation of light has been studied comprehensively. This work may pave a new way for developing the next generation of high-density data storage and photoelectric memristor.

Holographic Grating Enhancement Induced by a Dual-Photo-Initiator System in PMMA Substrate Polymers

Polymer systems induced by the reaction between monomers and photo-initiators play a crucial role in the formation of volume-phase gratings. In this paper, we fabricated a dual-photo-initiator photopolymer by doping EY (Eosin Yellow) molecules into a TI (Titanocene, Irgacure 784@BASF) dispersed PMMA (poly-[methyl methacrylate]) substrate system, with the aim of promoting the diffusion and polymerization processes in volume holographic storage. The two-wave interference system is adopted to record a permanent grating structure in our materials. The temporal diffraction variations of photopolymerization (during the interference exposure) and dark diffusion (after the interference exposure) processes have been investigated and analyzed. Aiming to analyze the influence of EY doping ratios on holographic performances, some key parameters were examined in the experiment. We first measured the temporal evolution of diffraction efficiency, then an exponential fitting was adopted to obtain the response time. Finally, the angular selectivity was evaluated by the Bragg condition after holographic recording. Also, the temporal evolution of each component is described by the nonlocal polymerization-driven diffusion model with a dual-photo-initiator composition, theoretically. Furthermore, we experimentally achieved the holographic grating enhancement in both the dark diffusion and photopolymerization processes by doping appropriate EY concentrations, respectively. This work provides a foundation for the acceptability of TI&EY/PMMA polymers in further holographic storage research.

Probing Optical Multi-Level Memory Effects in Single Core-Shell Quantum Dots and Application Through 2D-0D Hybrid Inverters

Challenges in the development of a multi-level memory (MM) device for multinary arithmetic computers have posed an obstacle to low-power, ultra-high-speed operation. For the effective transfer of a huge amount of data between arithmetic and storage devices, optical communication technology represents a compelling solution. Here, by replicating a floating gate architecture with CdSe/ZnS type-I core/shell quantum dots (QDs), a 2D-0D hybrid optical multi-level memory (OMM) device operated is demonstrated by laser pulses. In the device, laser pulses create linear optically trapped currents with MM characteristics, while conversely, voltage pulses reset all the trapped currents at once. Assuming electron transfer via the energy band alignment between MoS2 and CdSe, the study also establishes the mechanism of the OMM effect. Analysis of the designed device led to a new hypothesis that charge transfer is difficult for laterally adjacent QDs facing a double ZnS shell, which is tested by separately stimulating different positions on the 2D-0D hybrid structure with finely focused laser pulses. Results indicate that each laser pulse induced independent MM characteristics in the 2D-0D hybrid architecture. Based on this phenomenon, we propose a MM inverter to produce MM effects, such as programming and erasing, solely through the use of laser pulses. Finally, the feasibility of a fully optically-controlled intelligent system based on the proposed OMM inverters is evaluated through a CIFAR-10 pattern recognition task using a convolutional neural network.

Synaptic plasticity and non-volatile memory characteristics in TiN-nanocrystal-embedded 3D vertical memristor-based synapses for neuromorphic systems

Although vertical configurations for high-density storage require challenging process steps, such as etching high aspect ratios and atomic layer deposition (ALD), they are more affordable with a relatively simple lithography process and have been employed in many studies. Herein, the potential of memristors with CMOS-compatible 3D vertical stacked structures of Pt/Ti/HfOx/TiN-NCs/HfOx/TiN is examined for use in neuromorphic systems. The electrical characteristics (including I-V properties, retention, and endurance) were investigated for both planar single cells and vertical resistive random-access memory (VRRAM) cells at each layer, demonstrating their outstanding non-volatile memory capabilities. In addition, various synaptic functions (including potentiation and depression) under different pulse schemes, excitatory postsynaptic current (EPSC), and spike-timing-dependent plasticity (STDP) were investigated. In pattern recognition simulations, an improved recognition rate was achieved by the linearly changing conductance, which was enhanced by the incremental pulse scheme. The achieved results demonstrated the feasibility of employing VRRAM with TiN nanocrystals in neuromorphic systems that resemble the human brain.

Polysilicon-Channel Synaptic Transistors for Implementation of Short- and Long-Term Memory Characteristics

The rapid progress of artificial neural networks (ANN) is largely attributed to the development of the rectified linear unit (ReLU) activation function. However, the implementation of software-based ANNs, such as convolutional neural networks (CNN), within the von Neumann architecture faces limitations due to its sequential processing mechanism. To overcome this challenge, research on hardware neuromorphic systems based on spiking neural networks (SNN) has gained significant interest. Artificial synapse, a crucial building block in these systems, has predominantly utilized resistive memory-based memristors. However, the two-terminal structure of memristors presents difficulties in processing feedback signals from the post-synaptic neuron, and without an additional rectifying device it is challenging to prevent sneak current paths. In this paper, we propose a four-terminal synaptic transistor with an asymmetric dual-gate structure as a solution to the limitations of two-terminal memristors. Similar to biological synapses, the proposed device multiplies the presynaptic input signal with stored synaptic weight information and transmits the result to the postsynaptic neuron. Weight modulation is explored through both hot carrier injection (HCI) and Fowler-Nordheim (FN) tunneling. Moreover, we investigate the incorporation of short-term memory properties by adopting polysilicon grain boundaries as temporary storage. It is anticipated that the devised synaptic devices, possessing both short-term and long-term memory characteristics, will enable the implementation of various novel ANN algorithms.

Solution-processed zirconium acetylacetonate charge-trap layer for multi-bit nonvolatile thin-film memory transistors

The charge trap property of solution-processed zirconium acetylacetonate (ZAA) for solution-processed nonvolatile charge-trap memory (CTM) transistors is demonstrated. Increasing the annealing temperature of the ZAA from room temperature (RT) to 300°C in ambient, the carbon double bonds within the ZAA decreases. The RT-dried ZAA for the p-type organic-based CTM shows the widest threshold voltage shift (∆VTH ≈ 80 V), four distinct VTHs for a multi-bit memory operation and retained memory currents for 103 s with high memory on- and off-current ratio (IM,ON/IM,OFF ≈ 5Ⅹ104). The n-type oxide-based CTM (Ox-CTM) also shows a ∆VTH of 14 V and retained memory currents for 103 s with IM,ON/IM,OFF ≈ 104. The inability of the Ox-CTM to be electrically erasable is well explained with simulated electrical potential contour maps. It is deduced that, irrespective of the varied solution-processed semiconductor used, the RT-dried organic ZAA as CTL shows the best memory functionality in the fabricated CTMs. This implies that the high carbon double bonds in the low-temperature processed ZAA CTL are very useful for low-cost multi-bit CTMs in flexible electronics.

Contribution of Ion Energy and Flux on High-Aspect Ratio SiO2 Etching Characteristics in a Dual-Frequency Capacitively Coupled Ar/C4F8 Plasma: Individual Ion Energy and Flux Controlled

As the process complexity has been increased to overcome challenges in plasma etching, individual control of internal plasma parameters for process optimization has attracted attention. This study investigated the individual contribution of internal parameters, the ion energy and flux, on high-aspect ratio SiO2 etching characteristics for various trench widths in a dual-frequency capacitively coupled plasma system with Ar/C4F8 gases. We established an individual control window of ion flux and energy by adjusting dual-frequency power sources and measuring the electron density and self-bias voltage. We separately varied the ion flux and energy with the same ratio from the reference condition and found that the increase in ion energy shows higher etching rate enhancement than that in the ion flux with the same increase ratio in a 200 nm pattern width. Based on a volume-averaged plasma model analysis, the weak contribution of the ion flux results from the increase in heavy radicals, which is inevitably accompanied with the increase in the ion flux and forms a fluorocarbon film, preventing etching. At the 60 nm pattern width, the etching stops at the reference condition and it remains despite increasing ion energy, which implies the surface charging-induced etching stops. The etching, however, slightly increased with the increasing ion flux from the reference condition, revealing the surface charge removal accompanied with conducting fluorocarbon film formation by heavy radicals. In addition, the entrance width of an amorphous carbon layer (ACL) mask enlarges with increasing ion energy, whereas it relatively remains constant with that of ion energy. These findings can be utilized to optimize the SiO2 etching process in high-aspect ratio etching applications.

Two-Dimensional Layered Materials Meet Perovskite Oxides: A Combination for High-Performance Electronic Devices

As the Si-based transistors scale down to atomic dimensions, the basic principle of current electronics, which heavily relies on the tunable charge degree of freedom, faces increasing challenges to meet the future requirements of speed, switching energy, heat dissipation, and packing density as well as functionalities. Heterogeneous integration, where dissimilar layers of materials and functionalities are unrestrictedly stacked at an atomic scale, is appealing for next-generation electronics, such as multifunctional, neuromorphic, spintronic, and ultralow-power devices, because it unlocks technologically useful interfaces of distinct functionalities. Recently, the combination of functional perovskite oxides and two-dimensional layered materials (2DLMs) led to unexpected functionalities and enhanced device performance. In this paper, we review the recent progress of the heterogeneous integration of perovskite oxides and 2DLMs from the perspectives of fabrication and interfacial properties, electronic applications, and challenges as well as outlooks. In particular, we focus on three types of attractive applications, namely field-effect transistors, memory, and neuromorphic electronics. The van der Waals integration approach is extendible to other oxides and 2DLMs, leading to almost unlimited combinations of oxides and 2DLMs and contributing to future high-performance electronic and spintronic devices.

Combination of Polymer Gate Dielectric and Two-Dimensional Semiconductor for Emerging Field-Effect Transistors

Two-dimensional (2D) materials are considered attractive semiconducting layers for emerging field-effect transistors owing to their unique electronic and optoelectronic properties. Polymers have been utilized in combination with 2D semiconductors as gate dielectric layers in field-effect transistors (FETs). Despite their distinctive advantages, the applicability of polymer gate dielectric materials for 2D semiconductor FETs has rarely been discussed in a comprehensive manner. Therefore, this paper reviews recent progress relating to 2D semiconductor FETs based on a wide range of polymeric gate dielectric materials, including (1) solution-based polymer dielectrics, (2) vacuum-deposited polymer dielectrics, (3) ferroelectric polymers, and (4) ion gels. Exploiting appropriate materials and corresponding processes, polymer gate dielectrics have enhanced the performance of 2D semiconductor FETs and enabled the development of versatile device structures in energy-efficient ways. Furthermore, FET-based functional electronic devices, such as flash memory devices, photodetectors, ferroelectric memory devices, and flexible electronics, are highlighted in this review. This paper also outlines challenges and opportunities in order to help develop high-performance FETs based on 2D semiconductors and polymer gate dielectrics and realize their practical applications.

Analog Resistive Switching and Artificial Synaptic Behavior of ITO/WOX/TaN Memristors

In this work, we fabricated an ITO/WO_X/TaN memristor device by reactive sputtering to investigate resistive switching and conduct analog resistive switching to implement artificial synaptic devices. The device showed good pulse endurance (10⁴ cycles), a high on/off ratio (>10), and long retention (>10⁴ s) at room temperature. The conduction mechanism could be explained by Schottky emission conduction. Further, the resistive switching characteristics were performed by additional pulse-signal-based experiments for more practical operation. Lastly, the potentiation/depression characteristics were examined for 10 cycles. The results thus indicate that the WO_X-based devices are appropriate candidates for synaptic devices as well as next-generation nonvolatile memory.

Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process

The design-rule shrinkage in semiconductor devices is a challenge at every step of the integration process. In the gap-fill process for isolation, the seam and void formation cannot be suppressed by using a deposition process, which even has excellent step coverage. To achieve seamless gap fill in the high-aspect-ratio structure, which has a non-ideal etch profile such as a negative slope, the deposition process should be able to realize the “bottom-up growth” behavior. In this work, the bottom-up growth of a SiO₂ plasma-enhanced atomic layer deposition (PE-ALD) process in a trench structure was investigated by using a growth inhibition process employing plasma treatment. N₂ and NH₃ plasma pre-treatments were employed to suppress the growth of the SiO₂ PE-ALD process without any contamination, and the inhibition mechanism was investigated by performing surface chemistry analyses using X-ray photoelectron spectroscopy. Furthermore, the gap-fill characteristics of the SiO₂ PE-ALD process were examined, depending on the process conditions of NH₃ plasma pre-treatment, by performing cross-sectional field emission scanning electron microscopy measurements. Finally, a seamless gap-fill process in a high-aspect-ratio trench pattern was achieved by the bottom-up growth behavior of SiO₂ PE-ALD using NH₃ plasma pre-treatment.