Ballistic One-Dimensional InAs Nanowire Cross-Junction Interconnects

Gate-tunable subband degeneracy in semiconductor nanowires

Degeneracy and symmetry have a profound relation in quantum systems. Here, we report gate-tunable subband degeneracy in PbTe nanowires with a nearly symmetric cross-sectional shape. The degeneracy is revealed in electron transport by the absence of a quantized plateau. Utilizing a dual gate design, we can apply an electric field to lift the degeneracy, reflected as emergence of the plateau. This degeneracy and its tunable lifting were challenging to observe in previous nanowire experiments, possibly due to disorder. Numerical simulations can qualitatively capture our observation, shedding light on device parameters for future applications.

Electronic Transport and Quantum Phenomena in Nanowires

Nanowires are natural one-dimensional channels and offer new opportunities for advanced electronic quantum transport experiments. We review recent progress on the synthesis of nanowires and methods for the fabrication of hybrid semiconductor/superconductor systems. We discuss methods to characterize their electronic properties in the context of possible future applications such as topological and spin qubits. We focus on group III-V (InAs and InSb) and group IV (Ge/Si) semiconductors, since these are the most developed, and give an outlook on other potential materials.

Cryogenic multiplexing using selective area grown nanowires

Bottom-up grown nanomaterials play an integral role in the development of quantum technologies but are often challenging to characterise on large scales. Here, we harness selective area growth of semiconductor nanowires to demonstrate large-scale integrated circuits and characterisation of large numbers of quantum devices. The circuit consisted of 512 quantum devices embedded within multiplexer/demultiplexer pairs, incorporating thousands of interconnected selective area growth nanowires operating under deep cryogenic conditions. Multiplexers enable a range of new strategies in quantum device research and scaling by increasing the device count while limiting the number of connections between room-temperature control electronics and the cryogenic samples. As an example of this potential we perform a statistical characterization of large arrays of identical quantum dots thus establishing the feasibility of applying cross-bar gating strategies for efficient scaling of future selective area growth quantum circuits. More broadly, the ability to systematically characterise large numbers of devices provides new levels of statistical certainty to materials/device development.

Ballistic PbTe Nanowire Devices

Disorder is the primary obstacle in the current Majorana nanowire experiments. Reducing disorder or achieving ballistic transport is thus of paramount importance. In clean and ballistic nanowire devices, quantized conductance is expected, with plateau quality serving as a benchmark for disorder assessment. Here, we introduce ballistic PbTe nanowire devices grown by using the selective-area-growth (SAG) technique. Quantized conductance plateaus in units of 2e2/h are observed at zero magnetic field. This observation represents an advancement in diminishing disorder within SAG nanowires as most of the previously studied SAG nanowires (InSb or InAs) have not exhibited zero-field ballistic transport. Notably, the plateau values indicate that the ubiquitous valley degeneracy in PbTe is lifted in nanowire devices. This degeneracy lifting addresses an additional concern in the pursuit of Majorana realization. Moreover, these ballistic PbTe nanowires may enable the search for clean signatures of the spin-orbit helical gap in future devices.

Criterion for Selective Area Growth of III-V Nanowires

A model for the nucleation of vertical or planar III-V nanowires (NWs) in selective area growth (SAG) on masked substrates with regular arrays of openings is developed. The optimal SAG zone, with NW nucleation within the openings and the absence of parasitic III-V crystallites or group III droplets on the mask, is established, taking into account the minimum chemical potential of the III-V pairs required for nucleation on different surfaces, and the surface diffusion of the group III adatoms. The SAG maps are plotted in terms of the material fluxes versus the temperature. The non-trivial behavior of the SAG window, with the opening size and pitch, is analyzed, depending on the direction of the diffusion flux of the group III adatoms into or from the openings. A good correlation of the model with the data on the SAG of vertical GaN NWs and planar GaAs and InAs NWs by molecular beam epitaxy (MBE) is demonstrated.

Selective-Area Epitaxy of InGaAsP Buffer Multilayer for In-Plane InAs Nanowire Integration

In order to use III–V compound semiconductors as active channel materials in advanced electronic and quantum devices, it is important to achieve a good epitaxial growth on silicon substrates. As a first step toward this, we report on the selective-area growth of GaP/InGaP/InP/InAsP buffer layer nanotemplates on GaP substrates which are closely lattice-matched to silicon, suitable for the integration of in-plane InAs nanowires. Scanning electron microscopy reveals a perfect surface selectivity and uniform layer growth inside 150 and 200 nm large SiO₂ mask openings. Compositional and structural characterization of the optimized structure performed by transmission electron microscopy shows the evolution of the major facet planes and allows a strain distribution analysis. Chemically uniform layers with well-defined heterointerfaces are obtained, and the topmost InAs layer is free from any dislocation. Our study demonstrates that a growth sequence of thin layers with progressively increasing lattice parameters is effective to efficiently relax the strain and eventually obtain high quality in-plane InAs nanowires on large lattice-mismatched substrates.

Semiconductor Epitaxy in Superconducting Templates

Integration of high-quality semiconductor-superconductor devices into scalable and complementary metal-oxide-semiconductor compatible architectures remains an outstanding challenge, currently hindering their practical implementation. Here, we demonstrate growth of InAs nanowires monolithically integrated on Si inside lateral cavities containing superconducting TiN elements. This technique allows growth of hybrid devices characterized by sharp semiconductor-superconductor interfaces and with alignment along arbitrary crystallographic directions. Electrical characterization at low temperature reveals proximity induced superconductivity in InAs via a transparent interface.

High electron mobility in strained GaAs nanowires

Transistor concepts based on semiconductor nanowires promise high performance, lower energy consumption and better integrability in various platforms in nanoscale dimensions. Concerning the intrinsic transport properties of electrons in nanowires, relatively high mobility values that approach those in bulk crystals have been obtained only in core/shell heterostructures, where electrons are spatially confined inside the core. Here, it is demonstrated that the strain in lattice-mismatched core/shell nanowires can affect the effective mass of electrons in a way that boosts their mobility to distinct levels. Specifically, electrons inside the hydrostatically tensile-strained gallium arsenide core of nanowires with a thick indium aluminium arsenide shell exhibit mobility values 30–50 % higher than in equivalent unstrained nanowires or bulk crystals, as measured at room temperature. With such an enhancement of electron mobility, strained gallium arsenide nanowires emerge as a unique means for the advancement of transistor technology.

Semiconductor nanowires are promising candidates for the realization of novel transistor concepts. Here, the authors demonstrate that electron mobility in strained coaxial nanowire heterostructures can be higher than in the corresponding bulk crystals.

Multiterminal Quantized Conductance in InSb Nanocrosses

By studying the time-dependent axial and radial growth of InSb nanowires (NWs), the conditions for the synthesis of single-crystalline InSb nanocrosses (NCs) by molecular beam epitaxy are mapped. Low-temperature electrical measurements of InSb NC devices with local gate control on individual terminals exhibit quantized conductance and are used to probe the spatial distribution of the conducting channels. Tuning to a situation where the NC junction is connected by few-channel quantum point contacts in the connecting NW terminals, it is shown that transport through the junction is ballistic except close to pinch-off. Combined with a new concept for shadow-epitaxy of patterned superconductors on NCs, the structures reported here show promise for the realization of non-trivial topological states in multi-terminal Josephson junctions.

Postgrowth Shaping and Transport Anisotropy in Two-Dimensional InAs Nanofins

We report on the postgrowth shaping of free-standing two-dimensional (2D) InAs nanofins that are grown by selective-area epitaxy and mechanically transferred to a separate substrate for device fabrication. We use a citric acid-based wet etch that enables complex shapes, for example, van der Pauw cloverleaf structures, with patterning resolution down to 150 nm as well as partial thinning of the nanofin to improve local gate response. We exploit the high sensitivity of the cloverleaf structures to transport anisotropy to address the fundamental question of whether there is a measurable transport anisotropy arising from wurtzite/zincblende polytypism in 2D InAs nanostructures. We demonstrate a mobility anisotropy of order 2-4 at room temperature arising from polytypic stacking faults in our nanofins. Our work highlights a key materials consideration for devices featuring self-assembled 2D III-V nanostructures using advanced epitaxy methods.

Preferred growth direction of III-V nanowires on differently oriented Si substrates

One of the nanowire (NW) characteristics is its preferred elongation direction. Here, we investigated the impact of Si substrate crystal orientation on the growth direction of GaAs NWs. We first studied the self-catalyzed GaAs NW growth on Si (111) and Si (001) substrates. SEM observations show GaAs NWs on Si (001) are grown along four <111> directions without preference on one or some of them. This non-preferential NW growth on Si (001) is morphologically in contrast to the extensively reported vertical <111> preferred GaAs NW growth on Si (111) substrates. We propose a model based on the initial condition of an ideal Ga droplet formation on Si substrates and the surface free energy calculation which takes into account the dangling bond surface density for different facets. This model provides further understanding of the different preferences in the growth of GaAs NWs along selected <111> directions depending on the Si substrate orientation. To verify the prevalence of the model, NWs were grown on Si (311) substrates. The results are in good agreement with the three-dimensional mapping of surface free energy by our model. This general model can also be applied to predictions of NW preferred growth directions by the vapor-liquid-solid growth mode on other group IV and III-V substrates.

Impact of invasive metal probes on Hall measurements in semiconductor nanostructures

Recent advances in bottom-up growth are giving rise to a range of new two-dimensional nanostructures. Hall effect measurements play an important role in their electrical characterization. However, size constraints can lead to device geometries that deviate significantly from the ideal of elongated Hall bars with currentless contacts. Many devices using these new materials have a low aspect ratio and feature metal Hall probes that overlap with the semiconductor channel. This can lead to a significant distortion of the current flow. We present experimental data from InAs 2D nanofin devices with different Hall probe geometries to study the influence of Hall probe length and width. We use finite-element simulations to further understand the implications of these aspects and expand their scope to contact resistance and sample aspect ratio. Our key finding is that invasive probes lead to significant underestimation of measured Hall voltage, typically of the order 40-80%. This in turn leads to a subsequent proportional overestimation of carrier concentration and an underestimation of mobility.

Conductive-bridging random-access memories for emerging neuromorphic computing

With the increasing utilisation of artificial intelligence, there is a renewed demand for the development of novel neuromorphic computing owing to the drawbacks of the existing computing paradigm based on the von Neumann architecture. Extensive studies have been performed on memristors as their electrical nature is similar to those of biological synapses and neurons. However, most hardware-based artificial neural networks (ANNs) have been developed with oxide-based memristors owing to their high compatibility with mature complementary metal-oxide-semiconductor (CMOS) processes. Considering the advantages of conductive-bridging random-access memories (CBRAMs), such as their high scalability, high on-off current with a wide dynamic range, and low off-current, over oxide-based memristors, extensive studies on CBRAMs are required. In this review, the basics of operation of CBRAMs are examined in detail, from the formation of metal nanoclusters to filament bridging. Additionally, state-of-the-art experimental demonstrations of CBRAM-based artificial synapses and neurons are presented. Finally, CBRAM-based ANNs are discussed, including deep neural networks and spiking neural networks, along with other emerging computing applications. This review is expected to pave the way toward further development of large-scale CBRAM array systems.

Highly symmetric and tunable tunnel couplings in InAs/InP nanowire heterostructure quantum dots

We present a comprehensive electrical characterization of an InAs/InP nanowire (NW) heterostructure, comprising of two InP barriers forming a quantum dot (QD), two adjacent lead segments and two metallic contacts. We demonstrate how to extract valuable quantitative information of the QD. The QD shows very regular Coulomb blockade resonances over a large gate voltage range. By analyzing the resonance line shapes, we map the evolution of the tunnel couplings from the few to the many electron regime, with electrically tunable tunnel couplings from <1 μeV to >600 μeV, and a transition from the temperature to the lifetime broadened regime. The InP segments form tunnel barriers with almost fully symmetric tunnel couplings and a barrier height of ∼350 meV. All of these findings can be understood in great detail based on the deterministic material composition and geometry. Our results demonstrate that integrated InAs/InP QDs provide a promising platform for electron tunneling spectroscopy in InAs NWs, which can readily be contacted by a variety of superconducting materials to investigate subgap states in proximitized NW regions, or be used to characterize thermoelectric nanoscale devices in the quantum regime.

Nanowire Electronics: From Nanoscale to Macroscale

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Regaining a Spatial Dimension: Mechanically Transferrable Two-Dimensional InAs Nanofins Grown by Selective Area Epitaxy

We report a method for growing rectangular InAs nanofins with deterministic length, width, and height by dielectric-templated selective-area epitaxy. These freestanding nanofins can be transferred to lay flat on a separate substrate for device fabrication. A key goal was to regain a spatial dimension for device design compared to nanowires, while retaining the benefits of bottom-up epitaxial growth. The transferred nanofins were made into devices featuring multiple contacts for Hall effect and four-terminal resistance studies, as well as a global back-gate and nanoscale local top-gates for density control. Hall studies give a 3D electron density 2.5-5 × 10¹⁷ cm^-3, corresponding to an approximate surface accumulation layer density 3-6 × 10¹² cm^-2 that agrees well with previous studies of InAs nanowires. We obtain Hall mobilities as high as 1200 cm²/(V s), field-effect mobilities as high as 4400 cm²/(V s), and clear quantum interference structure at temperatures as high as 20 K. Our devices show excellent prospects for fabrication into more complicated devices featuring multiple ohmic contacts, local gates, and possibly other functional elements, for example, patterned superconductor contacts, that may make them attractive options for future quantum information applications.

Selectivity Map for Molecular Beam Epitaxy of Advanced III-V Quantum Nanowire Networks

Selective-area growth is a promising technique for enabling of the fabrication of the scalable III-V nanowire networks required to test proposals for Majorana-based quantum computing devices. However, the contours of the growth parameter window resulting in selective growth remain undefined. Herein, we present a set of experimental techniques that unambiguously establish the parameter space window resulting in selective III-V nanowire networks growth by molecular beam epitaxy. Selectivity maps are constructed for both GaAs and InAs compounds based on in situ characterization of growth kinetics on GaAs(001) substrates, where the difference in group III adatom desorption rates between the III-V surface and the amorphous mask area is identified as the primary mechanism governing selectivity. The broad applicability of this method is demonstrated by the successful realization of high-quality InAs and GaAs nanowire networks on GaAs, InP, and InAs substrates of both (001) and (111)B orientations as well as homoepitaxial InSb nanowire networks. Finally, phase coherence in Aharonov-Bohm ring experiments validates the potential of these crystals for nanoelectronics and quantum transport applications. This work should enable faster and better nanoscale crystal engineering over a range of compound semiconductors for improved device performance.

Improving the electrical properties of InAs nanowire field effect transistors by covering them with Y2O3/HfO2 layers

Quasi-one-dimensional semiconducting materials have attracted increasing attention due to their excellent ability to downscale the size of transistors. However, in quasi-one-dimensional nanowire (NW) transistors, their surface and interface properties play a very important role mainly due to the large surface-to-volume ratio of NWs and surface scattering, which degrade their carrier mobility. Herein, we developed a new method to cover the channel surface of InAs NW field effect transistors (FETs) with Y₂O₃/HfO₂ layers to improve their electrical properties. We successfully fabricated nine FETs and measured their electrical properties, which improve after depositing the Y₂O₃/HfO₂ layers, including an increase in on-state current, decrease in off-state current, increase in transconductance, increase in electron mobility and decrease in subthreshold swing. By comparing the properties of Y₂O₃/HfO₂-covered devices with that of the FETs fabricated without the Y₂O₃ covering or without annealing, we prove that it is the combined Y₂O₃/HfO₂ layers instead of only the Y₂O₃ or HfO₂ layer that improve the electrical properties of the FETs. The Cs-corrected high-resolution scanning transmission electron microscopy study demonstrates that Y can actually diffuse through the native oxide layer (confirmed to be InO_x) and reach the surface of the InAs NWs. Our results indicate that the desirable characteristics of Y₂O₃ and the surface passivation by HfO₂ improve the electrical properties of the InAs NW FETs, in which Y₂O₃ plays an important role to modify and stabilize the interface between the InAs NWs and the outside dielectric layer. Furthermore, this method should also be applicable to other III-V materials.

Correlation between Electrical Transport and Nanoscale Strain in InAs/In0.6Ga0.4As Core-Shell Nanowires

Free-standing semiconductor nanowires constitute an ideal material system for the direct manipulation of electrical and optical properties by strain engineering. In this study, we present a direct quantitative correlation between electrical conductivity and nanoscale lattice strain of individual InAs nanowires passivated with a thin epitaxial In_0.6Ga_0.4As shell. With an in situ electron microscopy electromechanical testing technique, we show that the piezoresistive response of the nanowires is greatly enhanced compared to bulk InAs, and that uniaxial elastic strain leads to increased conductivity, which can be explained by a strain-induced reduction in the band gap. In addition, we observe inhomogeneity in strain distribution, which could have a reverse effect on the conductivity by increasing the scattering of charge carriers. These results provide a direct correlation of nanoscale mechanical strain and electrical transport properties in free-standing nanostructures.

Thermoelectric Power Factor Limit of a 1D Nanowire

In the past decade, there has been significant interest in the potentially advantageous thermoelectric properties of one-dimensional (1D) nanowires, but it has been challenging to find high thermoelectric power factors based on 1D effects in practice. Here we point out that there is an upper limit to the thermoelectric power factor of nonballistic 1D nanowires, as a consequence of the recently established quantum bound of thermoelectric power output. We experimentally test this limit in quasiballistic InAs nanowires by extracting the maximum power factor of the first 1D subband through I-V characterization, finding that the measured maximum power factors conform to the theoretical limit. The established limit allows the prediction of the achievable power factor of a specific nanowire material system with 1D electronic transport based on the nanowire dimension and mean free path. The power factor of state-of-the-art semiconductor nanowires with small cross section and high crystal quality can be expected to be highly competitive (on the order of mW/m K^{2}) at low temperatures. However, they have no clear advantage over bulk materials at, or above, room temperature.

Template-Assisted Scalable Nanowire Networks

Topological qubits based on Majorana Fermions have the potential to revolutionize the emerging field of quantum computing by making information processing significantly more robust to decoherence. Nanowires are a promising medium for hosting these kinds of qubits, though branched nanowires are needed to perform qubit manipulations. Here we report a gold-free templated growth of III-V nanowires by molecular beam epitaxy using an approach that enables patternable and highly regular branched nanowire arrays on a far greater scale than what has been reported thus far. Our approach relies on the lattice-mismatched growth of InAs on top of defect-free GaAs nanomembranes yielding laterally oriented, low-defect InAs and InGaAs nanowires whose shapes are determined by surface and strain energy minimization. By controlling nanomembrane width and growth time, we demonstrate the formation of compositionally graded nanowires with cross-sections less than 50 nm. Scaling the nanowires below 20 nm leads to the formation of homogeneous InGaAs nanowires, which exhibit phase-coherent, quasi-1D quantum transport as shown by magnetoconductance measurements. These results are an important advance toward scalable topological quantum computing.

Mapping the Coulomb Environment in Interference-Quenched Ballistic Nanowires

The conductance of semiconductor nanowires is strongly dependent on their electrostatic history because of the overwhelming influence of charged surface and interface states on electron confinement and scattering. We show that InAs nanowire field-effect transistor devices can be conditioned to suppress resonances that obscure quantized conduction thereby revealing as many as six sub-bands in the conductance spectra as the Fermi-level is swept across the sub-band energies. The energy level spectra extracted from conductance, coupled with detailed modeling shows the significance of the interface state charge distribution revealing the Coulomb landscape of the nanowire device. Inclusion of self-consistent Coulomb potentials, the measured geometrical shape of the nanowire, the gate geometry and nonparabolicity of the conduction band provide a quantitative and accurate description of the confinement potential and resulting energy level structure. Surfaces of the nanowire terminated by HfO₂ are shown to have their interface donor density reduced by a factor of 30 signifying the passivating role played by HfO₂.

Observation of Conductance Quantization in InSb Nanowire Networks

Majorana zero modes (MZMs) are prime candidates for robust topological quantum bits, holding a great promise for quantum computing. Semiconducting nanowires with strong spin orbit coupling offer a promising platform to harness one-dimensional electron transport for Majorana physics. Demonstrating the topological nature of MZMs relies on braiding, accomplished by moving MZMs around each other in a certain sequence. Most of the proposed Majorana braiding circuits require nanowire networks with minimal disorder. Here, the electronic transport across a junction between two merged InSb nanowires is studied to investigate how disordered these nanowire networks are. Conductance quantization plateaus are observed in most of the contact pairs of the epitaxial InSb nanowire networks: the hallmark of ballistic transport behavior.

Growth of InAs Wurtzite Nanocrosses from Hexagonal and Cubic Basis

Epitaxially connected nanowires allow for the design of electron transport experiments and applications beyond the standard two terminal device geometries. In this Letter, we present growth methods of three distinct types of wurtzite structured InAs nanocrosses via the vapor-liquid-solid mechanism. Two methods use conventional wurtzite nanowire arrays as a 6-fold hexagonal basis for growing single crystal wurtzite nanocrosses. A third method uses the 2-fold cubic symmetry of (100) substrates to form well-defined coherent inclusions of zinc blende in the center of the nanocrosses. We show that all three types of nanocrosses can be transferred undamaged to arbitrary substrates, which allows for structural, compositional, and electrical characterization. We further demonstrate the potential for synthesis of as-grown nanowire networks and for using nanowires as shadow masks for in situ fabricated junctions in radial nanowire heterostructures.

Quantum Transport and Sub-Band Structure of Modulation-Doped GaAs/AlAs Core-Superlattice Nanowires

Modulation-doped III-V semiconductor nanowire (NW) heterostructures have recently emerged as promising candidates to host high-mobility electron channels for future high-frequency, low-energy transistor technologies. The one-dimensional geometry of NWs also makes them attractive for studying quantum confinement effects. Here, we report correlated investigations into the discrete electronic sub-band structure of confined electrons in the channel of Si δ-doped GaAs-GaAs/AlAs core-superlattice NW heterostructures and the associated signatures in low-temperature transport. On the basis of accurate structural and dopant analysis using scanning transmission electron microscopy and atom probe tomography, we calculated the sub-band structure of electrons confined in the NW core and employ a labeling system inspired by atomic orbital notation. Electron transport measurements on top-gated NW transistors at cryogenic temperatures revealed signatures consistent with the depopulation of the quasi-one-dimensional sub-bands, as well as confinement in zero-dimensional-like states due to an impurity-defined background disorder potential. These findings are instructive toward reaching the ballistic transport regime in GaAs-AlGaAs based NW systems.