Self-Selective Multi-Terminal Memtransistor Crossbar Array for In-Memory Computing

Large-Area Epitaxial Growth of Transition Metal Dichalcogenides

Over the past decade, research on atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) has expanded rapidly due to their unique properties such as high carrier mobility, significant excitonic effects, and strong spin-orbit couplings. Considerable attention from both scientific and industrial communities has fully fueled the exploration of TMDs toward practical applications. Proposed scenarios, such as ultrascaled transistors, on-chip photonics, flexible optoelectronics, and efficient electrocatalysis, critically depend on the scalable production of large-area TMD films. Correspondingly, substantial efforts have been devoted to refining the synthesizing methodology of 2D TMDs, which brought the field to a stage that necessitates a comprehensive summary. In this Review, we give a systematic overview of the basic designs and significant advancements in large-area epitaxial growth of TMDs. We first sketch out their fundamental structures and diverse properties. Subsequent discussion encompasses the state-of-the-art wafer-scale production designs, single-crystal epitaxial strategies, and techniques for structure modification and postprocessing. Additionally, we highlight the future directions for application-driven material fabrication and persistent challenges, aiming to inspire ongoing exploration along a revolution in the modern semiconductor industry.

Compositional effects of hybrid MoS2-GO active layer on the performance of unipolar, low-power and multistate RRAM device

Currently, 2D nanomaterials-based resistive random access memory (RRAMs) are explored on account of their tunable material properties enabling fabrication of low power and flexible RRAM devices. In this work, hybrid MoS2-GO based active layer RRAM devices are investigated. A facile hydrothermal co-synthesis approach is used to obtain the hybrid materials and a cost-effective spin coating method adopted for the fabrication of Ag/MoS2-GO/ITO RRAM devices. The performance of the fabricated hybrid active layer RRAM device is analysed with respect to change in material properties of the synthesized hybrid material. The progressive addition of 0.5, 1.5, 2.5 and 4.5 weight % of GO to MoS2, results in a hybrid active layer with higher intermolecular interaction, in the case of Ag/MoS2-GO4.5/ITO RRAM device, resulting in a unipolar resistive switching RRAM behavior with low SET voltage of 1.37 V and highIon/Ioffof 200 with multilevel resistance states. A space charge limited conduction mechanism is obtained during switching, which may be attributed to the trap states present due to functional groups of GO. The increased number of conduction pathways on account of both Ag+ions and oxygen vacancies (Vo2+), participating in the formation of conducting filament, results in higherIon/Ioff. This is the first report of unipolar Ag/MoS2-GO/ITO RRAM devices, which are particularly important in realizing high density crossbar memories for neuromorphic and in-memory computing as well as enabling flexible 2D nanomaterials-based memristor applications.

2D Memory Selectors with Giant Nonlinearity Enabled by Van der Waals Heterostructures

The integration of one-selector-one-resistor crossbar arrays requires the selectors featured with high nonlinearity and bipolarity to prevent leakage currents and any crosstalk among distinct cells. However, a selector with sufficient nonlinearity especially in the frame of device miniaturization remains scarce, restricting the advance of high-density storage devices. Herein, a high-performance memory selector is reported by constructing a graphene/hBN/WSe2 heterostructure. Within the temperature range of 300-80 K, the nonlinearity of this selector varies from ≈103 - ≈104 under forward bias, and increases from ≈300 - ≈105 under reverse bias, the highest reported nonlinearity among 2D selectors. This improvement is ascribed to direct tunneling at low bias and Fowler-Nordheim tunneling at high bias. The tunneling current versus voltage curves exhibit excellent bipolarity behavior because of the comparable hole and electron tunneling barriers, and the charge transport polarity can be effectively tuned from N-type or P-type to bipolar by simply changing source-drain bias. In addition, the conceptual memory selector exhibits no sign of deterioration after 70 000 switching cycles, paving the way for assembling 2D selectors into modern memory devices.

Integration of MoS2 Memtransistor Devices and Analogue Circuits for Sensor Fusion in Autonomous Vehicle Target Localization

In contemporary autonomous driving systems relying on sensor fusion, traditional digital processors encounter challenges associated with analogue-to-digital conversion and iterative vector-matrix operations, which are encumbered by limitations in terms of response time and energy consumption. In this study, we present an analogue Kalman filter circuit based on molybdenum disulfide (MoS2) memtransistor, designed to accelerate sensor fusion for precise localization in autonomous vehicle applications. The nonvolatile memory characteristics of the memtransistor allow for the storage of a fixed Kalman gain, which eliminates the data convergence and thus accelerates the processing speeds. Additionally, the modulation of multiple conductance states by the gate terminal enables fast adaptability to diverse autonomous driving scenarios by tuning multiple Kalman filter gains. Our proposed analogue Kalman filter circuit accurately estimates the position coordinates of target vehicles by fusing sensor data from light detection and ranging (LiDAR), millimeter-wave radar (Radar), and camera, and it successfully solves real-word problems in a signal-free crossroad intersection. Notably, our system achieves a 1000-fold improvement in energy efficiency compared to that of digital circuits. This work underscores the viability of a memtransistor for achieving fast, energy-efficient real-time sensing, and continuous signal processing in advanced sensor fusion technology.

Physical reservoirs based on MoS2-HZO integrated ferroelectric field-effect transistors for reservoir computing systems

Reservoir computing (RC), a variant of recurrent neural networks (RNNs), is well-known for its reduced energy consumption through exclusive focus on training the output weight and its superior performance in handling spatiotemporal information. Implementing these networks in hardware requires devices with superior fading memory behavior. Unlike filament-based two-terminal devices, those relying on ferroelectric switching demonstrate improved voltage reliability, while three-terminal transistors provide additional active control. HfO2-based ferroelectric materials such as Hf0.5Zr0.5O2 (HZO), have garnered attention for their scalability and seamless integration with CMOS technology. This study implements a RC hardware based on MoS2-HZO integrated device structure with enhanced spontaneous polarization field. By adjusting the oxygen vacancy concentration, the devices exhibit consistent responses to both identical and nonidentical voltages, making them suitable for diverse RC applications. The high accuracy of MNIST handwritten digits recognition highlights the rich reservoir states of the traditional RC architecture. Additionally, the impact of masks on RC implementation is assessed, showcasing the device's capability for spatiotemporal signal analysis. This development paves the way for implementing energy-efficient and high-performance computing solutions.

Versatile Nanoscale Three-Terminal Memristive Switch Enabled by Gating

A three-terminal memristor with an ultrasmall footprint of only 0.07 μm2 and critical dimensions of 70 nm × 10 nm × 6 nm is introduced. The device's feature is the presence of a gate contact, which enables two operation modes: either tuning the set voltage or directly inducing a resistance change. In I-V mode, we demonstrate that by changing the gate voltages between ±1 V one can shift the set voltage by 69%. In pulsing mode, we show that resistance change can be triggered by a gate pulse. Furthermore, we tested the device endurance under a 1 kHz operation. In an experiment with 2.6 million voltage pulses, we found two distinct resistance states. The device response to a pseudorandom bit sequence displays an open eye diagram and a success ratio of 97%. Our results suggest that this device concept is a promising candidate for a variety of applications ranging from Internet-of-Things to neuromorphic computing.

Hardware implementation of memristor-based artificial neural networks

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Quantum Conductance in Vertical Hexagonal Boron Nitride Memristors with Graphene-Edge Contacts

Two-dimensional materials (2DMs) have gained significant interest for resistive-switching memory toward neuromorphic and in-memory computing (IMC). To achieve atomic-level miniaturization, we introduce vertical hexagonal boron nitride (h-BN) memristors with graphene edge contacts. In addition to enabling three-dimensional (3D) integration (i.e., vertical stacking) for ultimate scalability, the proposed structure delivers ultralow power by isolating single conductive nanofilaments (CNFs) in ultrasmall active areas with negligible leakage thanks to atomically thin (∼0.3 nm) graphene edge contacts. Moreover, it facilitates studying fundamental resistive-switching behavior of single CNFs in CVD-grown 2DMs that was previously unattainable with planar devices. This way, we studied their programming characteristics and observed a consistent single quantum step in conductance attributed to unique atomically constrained nanofilament behavior in CVD-grown 2DMs. This resistive-switching property was previously suggested for h-BN memristors and linked to potential improvements in stability (robustness of CNFs), and now we show experimental evidence including superior retention of quantized conductance.

Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials

The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.

The Roadmap of 2D Materials and Devices Toward Chips

Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked.

Monolithically Integrated Complementary Ferroelectric FET XNOR Synapse for the Binary Neural Network

Neuromorphic computing, which mimics the structure and principles of the human brain, has the potential to facilitate the hardware implementation of next-generation artificial intelligence systems and process large amounts of data with very low power consumption. Among them, the XNOR synapse-based Binary Neural Network (BNN) has been attracting attention due to its compact neural network parameter size and low hardware cost. The previous XNOR synapse has drawbacks, such as a trade-off between cell density and accuracy. In this work, we show nonvolatile XNOR synapses with high density and accuracy using a monolithically stacked complementary ferroelectric field-effect transistor (C-FeFET) composed of a p-type Si MFMIS-FeFET at the bottom and a 3D stackable n-type Al:IZTO MFS-FeTFT, achieving 60F2 per cell (2C-FeFET). For adjusting the threshold voltage and improving the switching speed (100 ns) of n-type ferroelectric TFT, we employed a dual-gate configuration and a unique operation scheme, making it comparable to those of Si-based FeFETs. We performed array-level simulation with a 512 × 512 subarray size and a 3-bit flash ADC, demonstrating that the image recognition accuracies using the MNIST and CIFAR-10 data sets were increased by 3.17 and 14.07%, respectively, in comparison to other nonvolatile XNOR synapses. In addition, we performed system-level analysis on a 512 × 512 XNOR C-FeFET, exhibiting an outstanding throughput of 717.37 GOPS and an energy efficiency of 196.7 TOPS/W. We expect that our approach would contribute to the high-density memory systems, logic-in-memory technology, and hardware implementation of neural networks.

Self-Rectifying Memristors for Three-Dimensional In-Memory Computing

Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence. In-memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor is developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large-scale and high-density crossbar arrays, particularly in three-dimensional (3D) integration. As a perfect solution to the sneak-path issue, a self-rectifying memristor (SRM) is proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (aJ level) and scalability (>102  Mbit). Moreover, SRM-configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed.

High-Density Artificial Synapse Array Consisting of Homogeneous Electrolyte-Gated Transistors

The artificial synapse array with an electrolyte-gated transistor (EGT) as an array unit presents considerable potential for neuromorphic computation. However, the integration of EGTs faces the drawback of the conflict between the polymer electrolytes and photo-lithography. This study presents a scheme based on a lateral-gate structure to realize high-density integration of EGTs and proposes the integration of 100 × 100 EGTs into a 2.5 × 2.5 cm2 glass, with a unit density of up to 1600 devices cm-2 . Furthermore, an electrolyte framework is developed to enhance the array performance, with ionic conductivity of up to 2.87 × 10-3  S cm-1 owing to the porosity of zeolitic imidazolate frameworks-67. The artificial synapse array realizes image processing functions, and exhibits high performance and homogeneity. The handwriting recognition accuracy of a representative device reaches 92.80%, with the standard deviation of all the devices being limited to 9.69%. The integrated array and its high performance demonstrate the feasibility of the scheme and provide a solid reference for the integration of EGTs.

In-Sensor Computing Realization Using Fully CMOS-Compatible TiN/HfOx-Based Neuristor Array

With the evolution of artificial intelligence, the explosive growth of data from sensory terminals gives rise to severe energy-efficiency bottleneck issues due to cumbersome data interactions among sensory, memory, and computing modules. Heterogeneous integration methods such as chiplet technology can significantly reduce unnecessary data movement; however, they fail to address the fundamental issue of the substantial time and energy overheads resulting from the physical separation of computing and sensory components. Brain-inspired in-sensor neuromorphic computing (ISNC) has plenty of room for such data-intensive applications. However, one key obstacle in developing ISNC systems is the lack of compatibility between material systems and manufacturing processes deployed in sensors and computing units. This study successfully addresses this challenge by implementing fully CMOS-compatible TiN/HfOx-based neuristor array. The developed ISNC system demonstrates several advantageous features, including multilevel analogue modulation, minimal dispersion, and no significant degradation in conductance (@125 °C). These characteristics enable stable and reproducible neuromorphic computing. Additionally, the device exhibits modulatable sensory and multi-store memory processes. Furthermore, the system achieves information recognition with a high accuracy rate of 93%, along with frequency selectivity and notable activity-dependent plasticity. This work provides a promising route to affordable and highly efficient sensory neuromorphic systems.

Breaking the Trade-Off Between Polymer Dielectric Constant and Loss via Aluminum Oxo Macrocycle Dopants for High-Performance Neuromorphic Electronics

The dielectric layer is crucial in regulating the overall performance of field-effect transistors (FETs), the key component in central processing units, sensors, and displays. Despite considerable efforts being devoted to developing high-permittivity (k) dielectrics, limited progress is made due to the inherent trade-off between dielectric constant and loss. Here, a solution is presented by designing a monodispersed disk-shaped Ce-Al-O-macrocycle as a dopant in polymer dielectrics. The molecule features a central Ce(III) core connected with eight Al atoms through sixteen bridging hydroxyls and eight 3-aminophenyl peripheries. The incorporation of this macrocycle in polymer dielectrics results in an up to sevenfold increase in dielectric constants and up to 89% reduction in dielectric loss at low frequencies. Moreover, the leakage-current densities decrease, and the breakdown strengths are improved by 63%. Relying on the above merits, FETs bearing cluster-doped polymer dielectrics give near three-orders source-drain current increments while maintaining low-level leakage/off currents, resulting in much higher charge-carrier mobilities (up to 2.45 cm2  V-1  s-1 ) and on/off ratios. This cluster-doping strategy is generalizable and shows great promise for ultralow-power photoelectric synapses and neuromorphic retinas. This work successfully breaks the trade-off between dielectric constant and loss and offers a unique design for polymer composite dielectrics.

A self-tuning PID controller based on analog-digital hybrid computing with a double-gate SnS2 memtransistor

Most commercial drones utilize a traditional proportional-integral-derivative (PID) controller because of its design simplicity. However, the traditional PID controller has certain limitations in terms of optimality and robustness; it is difficult to actively adjust the PID gains under some disturbances. In this study, we demonstrated an analog-digital hybrid computing platform based on double-gate SnS2 memtransistors to implement a self-tuning/energy-efficient PID controller in drones. The customized analog circuit with memtransistors executes the PID control algorithm with low power consumption; we experimentally verified that the energy consumption of the proposed hybrid computing-based PID controller is only 63% of that of the traditional PID controller. In addition, the precise tunability of analog conductance states in the memtransistor proved to be capable of reconfiguring the performance of the PID controller, where the developed self-tuning algorithm can automatically find the optimal PID control performance.

Two-Terminal MoS2 Memristor and the Homogeneous Integration with a MoS2 Transistor for Neural Networks

Memristors are promising candidates for constructing neural networks. However, their dissimilar working mechanism to that of the addressing transistors can result in a scaling mismatch, which may hinder efficient integration. Here, we demonstrate two-terminal MoS₂ memristors that work with a charge-based mechanism similar to that in transistors, which enables the homogeneous integration with MoS₂ transistors to realize one-transistor-one-memristor addressable cells for assembling programmable networks. The homogenously integrated cells are implemented in a 2 × 2 network array to demonstrate the enabled addressability and programmability. The potential for assembling a scalable network is evaluated in a simulated neural network using obtained realistic device parameters, which achieves over 91% pattern recognition accuracy. This study also reveals a generic mechanism and strategy that can be applied to other semiconducting devices for the engineering and homogeneous integration of memristive systems.

Heterosynaptic MoS2 Memtransistors Emulating Biological Neuromodulation for Energy-Efficient Neuromorphic Electronics

Heterosynaptic neuromodulation is a key enabler for energy-efficient and high-level biological neural processing. However, such manifold synaptic modulation cannot be emulated using conventional memristors and synaptic transistors. Thus, reported herein is a three-terminal heterosynaptic memtransistor using an intentional-defect-generated molybdenum disulfide channel. Particularly, the defect-mediated space-charge-limited conduction in the ultrathin channel results in memristive switching characteristics between the source and drain terminals, which are further modulated using a gate terminal according to the gate-tuned filling of trap states. The device acts as an artificial synapse controlled by sub-femtojoule impulses from both the source and gate terminals, consuming lower energy than its biological counterpart. In particular, electrostatic gate modulation, corresponding to biological neuromodulation, additionally regulates the dynamic range and tuning rate of the synaptic weight, independent of the programming (source) impulses. Notably, this heterosynaptic modulation not only improves the learning accuracy and efficiency but also reduces energy consumption in the pattern recognition. Thus, the study presents a new route leading toward the realization of highly networked and energy-efficient neuromorphic electronics.

Van der Waals Layer Transfer of 2D Materials for Monolithic 3D Electronic System Integration: Review and Outlook

Two-dimensional materials (2DMs) have attracted a great deal of interest due to their immense potential for scientific breakthroughs and technological innovations. While some 2D transition metal dichalcogenides (TMDC) such as MoS₂ and WS₂ are considered as the ultimate channel materials in unltrascaled transistors as replacements for Si, there has also been increasing interest in the monolithic 3D integration of 2DMs on the Si CMOS platform or in flexible electronics as back-end-of-line transistors, memory devices/selectors, and sensors, taking advantage of 2DM properties such as a high current driving capability with low leakage current, nonvolatile switching characteristics, a large surface-to-volume ratio, and a tunable bandgap. However, the realization of both of these scenarios critically depends on the development of manufacturing-viable high-yield 2DM layers transfer from the growth substrate to the Si, since the growth of high-quality 2DM layers often requires a high-temperature growth process on template substrates. Motivated by this, extensive efforts have been made by the 2DM research community to develop various 2DM layer transfer methods, leveraging the van der Waals transfer capability of the layer-structured 2DMs. These efforts have led to a number of successful demonstrations of wafer-scale 2D TMDC layer transfer, while 2DM-enabled template growth/transfer of some functional bulk materials such as III-V, Ge, and AlN has also been demonstrated. This review surveys and compares different 2DM transfer methods developed recently, with a focus on large-area 2D TMDC film transfer along with an introduction of 2DM template-assisted van der Waals growth/transfer of non-2D thin films. We will also briefly present an outlook of our envisioned multifunctionalities in 3D integrated electronic systems enabled by monolithic 3D integration of 2DMs and III-V via van der Waals transfer and discuss possible technology options for overcoming remaining challenges.

Wearable in-sensor reservoir computing using optoelectronic polymers with through-space charge-transport characteristics for multi-task learning

In-sensor multi-task learning is not only the key merit of biological visions but also a primary goal of artificial-general-intelligence. However, traditional silicon-vision-chips suffer from large time/energy overheads. Further, training conventional deep-learning models is neither scalable nor affordable on edge-devices. Here, a material-algorithm co-design is proposed to emulate human retina and the affordable learning paradigm. Relying on a bottle-brush-shaped semiconducting p-NDI with efficient exciton-dissociations and through-space charge-transport characteristics, a wearable transistor-based dynamic in-sensor Reservoir-Computing system manifesting excellent separability, fading memory, and echo state property on different tasks is developed. Paired with a 'readout function' on memristive organic diodes, the RC recognizes handwritten letters and numbers, and classifies diverse costumes with accuracies of 98.04%, 88.18%, and 91.76%, respectively (higher than all reported organic semiconductors). In addition to 2D images, the spatiotemporal dynamics of RC naturally extract features of event-based videos, classifying 3 types of hand gestures at an accuracy of 98.62%. Further, the computing cost is significantly lower than that of the conventional artificial-neural-networks. This work provides a promising material-algorithm co-design for affordable and highly efficient photonic neuromorphic systems.

A MoS2 Hafnium Oxide Based Ferroelectric Encoder for Temporal-Efficient Spiking Neural Network

Spiking neural network (SNN), where the information is evaluated recurrently through spikes, has manifested significant promises to minimize the energy expenditure in data-intensive machine learning and artificial intelligence. Among these applications, the artificial neural encoders are essential to convert the external stimuli to a spiking format that can be subsequently fed to the neural network. Here, a molybdenum disulfide (MoS₂ ) hafnium oxide-based ferroelectric encoder is demonstrated for temporal-efficient information processing in SNN. The fast domain switching attribute associated with the polycrystalline nature of hafnium oxide-based ferroelectric material is exploited for spike encoding, rendering it suitable for realizing biomimetic encoders. Accordingly, a high-performance ferroelectric encoder is achieved, featuring a superior switching efficiency, negligible charge trapping effect, and robust ferroelectric response, which successfully enable a broad dynamic range. Furthermore, an SNN is simulated to verify the precision of the encoded information, in which an average inference accuracy of 95.14% can be achieved, using the Modified National Insitute of Standards and Technology (MNIST) dataset for digit classification. Moreover, this ferroelectric encoder manifests prominent resilience against noise injection with an overall prediction accuracy of 94.73% under various Gaussian noise levels, showing practical promises to reduce the computational load for the neural network.

Nanopatterning Technologies of 2D Materials for Integrated Electronic and Optoelectronic Devices

With the reduction of feature size and increase of integration density, traditional 3D semiconductors are unable to meet the future requirements of chip integration. The current semiconductor fabrication technologies are approaching their physical limits based on Moore's law. 2D materials such as graphene, transitional metal dichalcogenides, etc., are of great promise for future memory, logic, and photonic devices due to their unique and excellent properties. To prompt 2D materials and devices from the laboratory research stage to the industrial integrated circuit-level, it is necessary to develop advanced nanopatterning methods to obtain high-quality, wafer-scale, and patterned 2D products. Herein, the recent development of nanopatterning technologies, particularly toward realizing large-scale practical application of 2D materials is reviewed. Based on the technological progress, the unique requirement and advances of the 2D integration process for logic, memory, and optoelectronic devices are further summarized. Finally, the opportunities and challenges of nanopatterning technologies of 2D materials for future integrated chip devices are prospected.

The Trend of 2D Transistors toward Integrated Circuits: Scaling Down and New Mechanisms

2D transition metal chalcogenide (TMDC) materials, such as MoS₂ , have recently attracted considerable research interest in the context of their use in ultrascaled devices owing to their excellent electronic properties. Microprocessors and neural network circuits based on MoS₂ have been developed at a large scale but still do not have an advantage over silicon in terms of their integrated density. In this study, the current structures, contact engineering, and doping methods for 2D TMDC materials for the scaling-down process and performance optimization are reviewed. Devices are introduced according to a new mechanism to provide the comprehensive prospects for the use of MoS₂ beyond the traditional complementary-metal-oxide semiconductor in order to summarize obstacles to the goal of developing high-density and low-power integrated circuits (ICs). Finally, prospects for the use of MoS₂ in large-scale ICs from the perspectives of the material, system performance, and application to nonlogic functionalities such as sensor circuits and analogous circuits, are briefly analyzed. The latter issue is along the direction of "more than Moore" research.

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. The different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

Integrated Memory Devices Based on 2D Materials

With the advent of the Internet of Things and big data, massive data must be rapidly processed and stored within a short timeframe. This imposes stringent requirements on memory hardware implementation in terms of operation speed, energy consumption, and integration density. To fulfill these demands, 2D materials, which are excellent electronic building blocks, provide numerous possibilities for developing advanced memory device arrays with high performance, smart computing architectures, and desirable downscaling. Over the past few years, 2D-material-based memory-device arrays with different working mechanisms, including defects, filaments, charges, ferroelectricity, and spins, have been increasingly developed. These arrays can be used to implement brain-inspired computing or sensing with extraordinary performance, architectures, and functionalities. Here, recent research into integrated, state-of-the-art memory devices made from 2D materials, as well as their implications for brain-inspired computing are surveyed. The existing challenges at the array level are discussed, and the scope for future research is presented.

Highly Reproducible Heterosynaptic Plasticity Enabled by MoS2/ZrO2-x Heterostructure Memtransistor

Electrically tunable resistive switching of a polycrystalline MoS₂-based memtransistor has attracted a great deal of attention as an essential synaptic component of neuromorphic circuitry because its switching characteristics from the field-induced migration of sulfur defects in the MoS₂ grain boundaries can realize multilevel conductance tunability and heterosynaptic functionality. However, reproducible switching properties in the memtransistor are usually disturbed by the considerable difficulty in controlling the concentration and distribution of the intrinsically existing sulfur defects. Herein, we demonstrate reliable heterosynaptic characteristics using a memtransistor device with a MoS₂/ZrO_2-x heterostructure. Compared to the control device with the MoS₂ semiconducting channel, the Schottky barrier height was more effectively modulated by the insertion of the insulating ZrO_2-x layer below the MoS₂, confirmed by an ultraviolet photoelectron spectroscopy analysis and the corresponding energy-band structures. The MoS₂/ZrO_2-x memtransistor accomplishes dual-terminal (drain and gate electrode) stimulated multilevel conductance owing to the tunable resistive switching behavior under varying gate voltages. Furthermore, the memtransistor exhibits long-term potentiation/depression endurance cycling over 7000 pulses and stable pulse cycling behavior by the pulse stimulus from different terminal regions. The promising candidate as an essential synaptic component of the MoS₂/ZrO_2-x memtransistors for neuromorphic systems results from the high recognition accuracy (∼92%) of the deep neural network simulation test, based on the training and inference of handwritten numbers (0-9). The simple memtransistor structure facilitates the implementation of complex neural circuitry.

Two-dimensional devices and integration towards the silicon lines

Despite technical efforts and upgrades, advances in complementary metal-oxide-semiconductor circuits have become unsustainable in the face of inherent silicon limits. New materials are being sought to compensate for silicon deficiencies, and two-dimensional materials are considered promising candidates due to their atomically thin structures and exotic physical properties. However, a potentially applicable method for incorporating two-dimensional materials into silicon platforms remains to be illustrated. Here we try to bridge two-dimensional materials and silicon technology, from integrated devices to monolithic 'on-silicon' (silicon as the substrate) and 'with-silicon' (silicon as a functional component) circuits, and discuss the corresponding requirements for material synthesis, device design and circuitry integration. Finally, we summarize the role played by two-dimensional materials in the silicon-dominated semiconductor industry and suggest the way forward, as well as the technologies that are expected to become mainstream in the near future.

Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications

Circuit or electronic components are useful elements allowing the realization of different circuit functionalities. The resistor, capacitor and inductor represent the three commonly known basic passive circuit elements owing to their fundamental nature relating them to the four circuit variables, namely voltage, magnetic flux, current and electric charge. The memory resistor (or memristor) was claimed to be the fourth basic passive circuit element, complementing the resistor, capacitor and inductor. This paper presents a review on the four basic passive circuit elements. After a brief recall on the first three known basic passive circuit elements, a thorough description of the memristor follows. Memristor sparks interest in the scientific community due to its interesting features, for example nano-scalability, memory capability, conductance modulation, connection flexibility and compatibility with CMOS technology, etc. These features among many others are currently in high demand on an industrial scale. For this reason, thousands of memristor-based applications are reported. Hence, the paper presents an in-depth overview of the philosophical argumentations of memristor, technologies and applications.

Interface-Modulated Resistive Switching in Mo-Irradiated ReS2 for Neuromorphic Computing

Coupling charge impurity scattering effects and charge-carrier modulation by doping can offer intriguing opportunities for atomic-level control of resistive switching (RS). Nonetheless, such effects have remained unexplored for memristive applications based on 2D materials. Here a facile approach is reported to transform an RS-inactive rhenium disulfide (ReS₂ ) into an effective switching material through interfacial modulation induced by molybdenum-irradiation (Mo-i) doping. Using ReS₂ as a model system, this study unveils a unique RS mechanism based on the formation/dissolution of metallic β-ReO₂ filament across the defective ReS₂ interface during the set/reset process. Through simple interfacial modulation, ReS₂ of various thicknesses are switchable by modulating the Mo-irradiation period. Besides, the Mo-irradiated ReS₂ (Mo-ReS₂ ) memristor further exhibits a bipolar non-volatile switching ratio of nearly two orders of magnitude, programmable multilevel resistance states, and long-term synaptic plasticity. Additionally, the fabricated device can achieve a high MNIST learning accuracy of 91% under a non-identical pulse train. The study's findings demonstrate the potential for modulating RS in RS-inactive 2D materials via the unique doping-induced charged impurity scattering property.

Wafer-Scale 2D Hafnium Diselenide Based Memristor Crossbar Array for Energy-Efficient Neural Network Hardware

Memristor crossbar with programmable conductance could overcome the energy consumption and speed limitations of neural networks when executing core computing tasks in image processing. However, the implementation of crossbar array (CBA) based on ultrathin 2D materials is hindered by challenges associated with large-scale material synthesis and device integration. Here, a memristor CBA is demonstrated using wafer-scale (2-inch) polycrystalline hafnium diselenide (HfSe₂ ) grown by molecular beam epitaxy, and a metal-assisted van der Waals transfer technique. The memristor exhibits small switching voltage (0.6 V), low switching energy (0.82 pJ), and simultaneously achieves emulation of synaptic weight plasticity. Furthermore, the CBA enables artificial neural network with a high recognition accuracy of 93.34%. Hardware multiply-and-accumulate (MAC) operation with a narrow error distribution of 0.29% is also demonstrated, and a high power efficiency of greater than 8-trillion operations per second per Watt is achieved. Based on the MAC results, hardware convolution image processing can be performed using programmable kernels (i.e., soft, horizontal, and vertical edge enhancement), which constitutes a vital function for neural network hardware.

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS₂. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

In-depth analysis on electrical parameters of floating gate IGZO synaptic transistor affecting pattern recognition accuracy

The reliable conductance modulation of synaptic devices is key when implementing high-performance neuromorphic systems. Herein, we propose a floating gate indium gallium zinc oxide (IGZO) synaptic device with an aluminum trapping layer to investigate the correlation between its diverse electrical parameters and pattern recognition accuracy. Basic synaptic properties such as excitatory postsynaptic current, paired pulse facilitation, long/short term memory, and long-term potentiation/depression are demonstrated in the IGZO synaptic transistor. The effects of pulse tuning conditions associated with the pulse voltage magnitude, interval, duration, and cycling number of the applied pulses on the conductance update are systematically investigated. It is discovered that both the nonlinearity of the conductance update and cycle-to-cycle variation should be critically considered using an artificial neural network simulator to ensure the high pattern recognition accuracy of Modified National Institute of Standards and Technology (MNIST) handwritten digit images. The highest recognition rate of the MNIST handwritten dataset is 94.06% for the most optimized pulse condition. Finally, a systematic study regarding the synaptic parameters must be performed to optimize the developed synapse device.

Anisotropic Carrier Mobility from 2H WSe2

Transition metal dichalcogenides (TMDCs) with 2H phase are expected to be building blocks in next-generation electronics; however, they suffer from electrical anisotropy, which is the basics for multi-terminal artificial synaptic devices, digital inverters, and anisotropic memtransistors, which are highly desired in neuromorphic computing. Herein, the anisotropic carrier mobility from 2H WSe₂ is reported, where the anisotropic degree of carrier mobility spans from 0.16 to 0.95 for various WSe₂ field-effect transistors under a gate voltage of -60 V. Phonon scattering, impurity ions scattering, and defect scattering are excluded for anisotropic mobility. An intrinsic screening layer is proposed and confirmed by Z-contrast scanning transmission electron microscopy (STEM) imaging to respond to the electrical anisotropy. Seven types of intrinsic screening layers are created and calculated by density functional theory to evaluate the modulated electronic structures, effective masses, and scattering intensities, resulting in anisotropic mobility. The discovery of anisotropic carrier mobility from 2H WSe₂ provides a degree of freedom for adjusting the physical properties of 2H TMDCs and fertile ground for exploring and integrating TMDC electronic transistors with better performance along the direction of high mobility.

Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates

We present an array of 225 field-effect transistors (FETs), where each of them has a graphene monolayer channel grown on a 3-layer deposited stack of 22 nm control HfO₂/5 nm Ge-HfO₂ intermediate layer/8 nm tunnel HfO₂/p-Si substrate. The intermediate layer is ferroelectric and acts as a floating gate. All transistors have two top gates, while the p-Si substrate is acting as a back gate. We show that these FETs are acting memtransistors, working as two-input reconfigurable logic gates with memory, the type of the logic gate depending only on the values of the applied gate voltages and the choice of a threshold current.

Reconfigurable 2D WSe2 -Based Memtransistor for Mimicking Homosynaptic and Heterosynaptic Plasticity

The mimicking of both homosynaptic and heterosynaptic plasticity using a high-performance synaptic device is important for developing human-brain-like neuromorphic computing systems to overcome the ever-increasing challenges caused by the conventional von Neumann architecture. However, the commonly used synaptic devices (e.g., memristors and transistors) require an extra modulate terminal to mimic heterosynaptic plasticity, and their capability of synaptic plasticity simulation is limited by the low weight adjustability. In this study, a WSe₂ -based memtransistor for mimicking both homosynaptic and heterosynaptic plasticity is fabricated. By applying spikes on either the drain or gate terminal, the memtransistor can mimic common homosynaptic plasticity, including spiking rate dependent plasticity, paired pulse facilitation/depression, synaptic potentiation/depression, and filtering. Benefitting from the multi-terminal input and high adjustability, the resistance state number and linearity of the memtransistor can be improved by optimizing the conditions of the two inputs. Moreover, the device can successfully mimic heterosynaptic plasticity without introducing an extra terminal and can simultaneously offer versatile reconfigurability of excitatory and inhibitory plasticity. These highly adjustable and reconfigurable characteristics offer memtransistors more freedom of choice for tuning synaptic weight, optimizing circuit design, and building artificial neuromorphic computing systems.

Reconfigurable MoS2 Memtransistors for Continuous Learning in Spiking Neural Networks

Artificial intelligence and machine learning are growing computing paradigms, but current algorithms incur undesirable energy costs on conventional hardware platforms, thus motivating the exploration of more efficient neuromorphic architectures. Toward this end, we introduce here a memtransistor with gate-tunable dynamic learning behavior. By fabricating memtransistors from monolayer MoS₂ grown on sapphire, the relative importance of the vertical field effect from the gate is enhanced, thereby heightening reconfigurability of the device response. Inspired by biological systems, gate pulses are used to modulate potentiation and depression, resulting in diverse learning curves and simplified spike-timing-dependent plasticity that facilitate unsupervised learning in simulated spiking neural networks. This capability also enables continuous learning, which is a previously underexplored cognitive concept in neuromorphic computing. Overall, this work demonstrates that the reconfigurability of memtransistors provides unique hardware accelerator opportunities for energy efficient artificial intelligence and machine learning.

Ultralow-power flexible transparent carbon nanotube synaptic transistors for emotional memory

Emulating the biological behavior of the human brain with artificial neuromorphic devices is essential for the future development of human-machine interactive systems, bionic sensing systems and intelligent robotic systems. In this paper, artificial flexible transparent carbon nanotube synaptic transistors (F-CNT-STs) with signal transmission and emotional learning functions are realized by adopting the poly(vinyl alcohol) (PVA)/SiO2 proton-conducting electrolyte. Synaptic functions of biological synapses including excitatory and inhibitory behaviors are successfully emulated in the F-CNT-STs. Besides, synaptic plasticity such as spike-duration-dependent plasticity, spike-number-dependent plasticity, spike-amplitude-dependent plasticity, paired-pulse facilitation, short-term plasticity, and long-term plasticity have all been systematically characterized. Moreover, the F-CNT-STs also closely imitate the behavior of human brain learning and emotional memory functions. After 1000 bending cycles at a radius of 3 mm, both the transistor characteristics and the synaptic functions can still be implemented correctly, showing outstanding mechanical capability. The realized F-CNT-STs possess low operating voltage, quick response, and ultra-low power consumption, indicating their high potential to work in low-power biological systems and artificial intelligence systems. The flexible artificial synaptic transistor enables its potential to be generally applicable to various flexible wearable biological and intelligent applications.