Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2

Electronics and Optoelectronics Based on Tellurium

As a true 1D system, group-VIA tellurium (Te) is composed of van der Waals bonded molecular chains within a triangular crystal lattice. This unique crystal structure endows Te with many intriguing properties, including electronic, optoelectronic, thermoelectric, piezoelectric, chirality, and topological properties. In addition, the bandgap of Te exhibits thickness dependence, ranging from 0.31 eV in bulk to 1.04 eV in the monolayer limit. These diverse properties make Te suitable for a wide range of applications, addressing both established and emerging challenges. This review begins with an elaboration of the crystal structures and fundamental properties of Te, followed by a detailed discussion of its various synthesis methods, which primarily include solution phase, and chemical and physical vapor deposition technologies. These methods form the foundation for designing Te-centered devices. Then the device applications enabled by Te nanostructures are introduced, with an emphasis on electronics, optoelectronics, sensors, and large-scale circuits. Additionally, performance optimization strategies are discussed for Te-based field-effect transistors. Finally, insights into future research directions and the challenges that lie ahead in this field are shared.

Understanding the Impact of Contact-Induced Strain on the Electrical Performance of Monolayer WS2 Transistors

Two-dimensional (2D) electronics require low contact resistance (RC) to approach their fundamental limits. WS2 is a promising 2D semiconductor that is often paired with Ni contacts, but their operation is not well understood considering the nonideal alignment between the Ni work function and the WS2 conduction band. Here, we investigate the effects of contact size on nanoscale monolayer WS2 transistors and uncover that Ni contacts impart stress, which affects the WS2 device performance. The strain applied to the WS2 depends on contact size, where long (1 μm) contacts (RC ≈ 1.7 kΩ·μm) show a 78% reduction in RC compared to shorter (0.1 μm) contacts (RC ≈ 7.8 kΩ·μm). We also find that thermal annealing can relax the WS2 strain in long-contact devices, increasing RC to 8.5 kΩ·μm. These results reveal that thermo-mechanical phenomena can significantly influence 2D semiconductor-metal contacts, presenting opportunities to optimize device performance through nanofabrication and thermal budget.

Low Contact Resistance on Monolayer MoS2 Field-Effect Transistors Achieved by CMOS-Compatible Metal Contacts

Contact engineering on monolayer layer (ML) semiconducting transition metal dichalcogenides (TMDs) is considered the most challenging problem toward using these materials as a transistor channel in future advanced technology nodes. The typically observed strong Fermi-level pinning induced in part by the reaction of the source/drain contact metal and the ML TMD frequently results in a large Schottky barrier height, which limits the electrical performance of ML TMD field-effect transistors (FETs). However, at a microscopic level, little is known about how interface defects or reaction sites impact the electrical performance of ML TMD FETs. In this work, we have performed statistically meaningful electrical measurements on at least 120 FETs combined with careful surface analysis to unveil contact resistance dependence on interface chemistry. In particular, we achieved a low contact resistance for ML MoS2 FETs with ultrahigh-vacuum (UHV, 3 × 10-11 mbar) deposited Ni contacts, ∼500 Ω·μm, which is 5 times lower than the contact resistance achieved when deposited under high-vacuum (HV, 3 × 10-6 mbar) conditions. These electrical results strongly correlate with our surface analysis observations. X-ray photoelectron spectroscopy (XPS) revealed significant bonding species between Ni and MoS2 under UHV conditions compared to that under HV. We also studied the Bi/MoS2 interface under UHV and HV deposition conditions. Different from the case of Ni, we do not observe a difference in contact resistance or interface chemistry between contacts deposited under UHV and HV. Finally, this article also explores the thermal stability and reliability of the two contact metals employed here.

Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor

Two-dimensional (2D) transition metal dichalcogenides (TMDs) allow for atomic-scale manipulation, challenging the conventional limitations of semiconductor materials. This capability may overcome the short-channel effect, sparking significant advancements in electronic devices that utilize 2D TMDs. Exploring the dimension and performance limits of transistors based on 2D TMDs has gained substantial importance. This review provides a comprehensive investigation into these limits of the single 2D-TMD transistor. It delves into the impacts of miniaturization, including the reduction of channel length, gate length, source/drain contact length, and dielectric thickness on transistor operation and performance. In addition, this review provides a detailed analysis of performance parameters such as source/drain contact resistance, subthreshold swing, hysteresis loop, carrier mobility, on/off ratio, and the development of p-type and single logic transistors. This review details the two logical expressions of the single 2D-TMD logic transistor, including current and voltage. It also emphasizes the role of 2D TMD-based transistors as memory devices, focusing on enhancing memory operation speed, endurance, data retention, and extinction ratio, as well as reducing energy consumption in memory devices functioning as artificial synapses. This review demonstrates the two calculating methods for dynamic energy consumption of 2D synaptic devices. This review not only summarizes the current state of the art in this field but also highlights potential future research directions and applications. It underscores the anticipated challenges, opportunities, and potential solutions in navigating the dimension and performance boundaries of 2D transistors.

High-Performance WS2 MOSFETs with Bilayer WS2 Contacts

WS2 is a promising transition-metal dichalcogenide (TMDC) for use as a channel material in extreme-scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its monolayer thickness, high carrier mobility, and its potential for symmetric n-type and p-type MOSFET performance. However, the formation of stable, low-barrier-height contacts to monolayer TMDCs continues to be a challenge. This study introduces an innovative approach to realize high-performance WS2 MOSFETs by utilizing bilayer WS2 (2L-WS2) in the contact region grown through a two-step chemical vapor deposition process. The 2L-WS2 devices demonstrate a high I ON/I OFF ratio of 108 and a saturated drain current, I D(SAT), of 280 μA/μm (386 μA/μm) at room temperature (78 K), even while still using conventional metal (Pd or Ni) contacts. Devices featuring a 1L-WS2 channel and 2L-WS2 in the contact regions were also fabricated, and they exhibited performance comparable to that of 2L-WS2 devices. The devices also exhibit good stability with nearly identical performance after storage over a 13 month period. The study highlights the benefits of a hybrid channel thickness approach for TMDC transistors.

Machine Learning to Promote Efficient Screening of Low-Contact Electrode for 2D Semiconductor Transistor Under Limited Data

Low-barrier and high-injection electrodes are crucial for high-performance (HP) 2D semiconductor devices. Conventional trial-and-error methodologies for electrode material screening are impractical because of their low efficiency and arbitrary specificity. Although machine learning has emerged as a promising alternative to tackle this problem, its practical application in semiconductor devices is hindered by its substantial data requirements. In this paper, a comprehensive scheme combining an autoencoding regularized adversarial neural network and a feature-adaptive variational active learning algorithm for screening low-contact electrode materials for 2D semiconductor transistors with limited data is proposed. The proposed scheme exhibits exceptional performance by training with only 15% of the total data points, where the mean square errors are 0.17 and 0.27 eV for the vertical and lateral Schottky barrier, respectively, and 2.88% for tunneling probability. Further, it exhibits an optimal predictive performance for 100 randomly sampled training datasets, reveals the underlying physical insight based on the identified features, and realizes continual improvement by employing detailed density-of-states descriptors. Finally, the empirical evaluations of the transport characteristics are conducted and verified by constructing MOSFET devices. These findings demonstrate the considerable potential of machine-learning techniques for screening high-efficiency electrode materials and constructing HP 2D semiconductor devices.

Tailoring amorphous boron nitride for high-performance two-dimensional electronics

Two-dimensional (2D) materials have garnered significant attention in recent years due to their atomically thin structure and unique electronic and optoelectronic properties. To harness their full potential for applications in next-generation electronics and photonics, precise control over the dielectric environment surrounding the 2D material is critical. The lack of nucleation sites on 2D surfaces to form thin, uniform dielectric layers often leads to interfacial defects that degrade the device performance, posing a major roadblock in the realization of 2D-based devices. Here, we demonstrate a wafer-scale, low-temperature process (<250 °C) using atomic layer deposition (ALD) for the synthesis of uniform, conformal amorphous boron nitride (aBN) thin films. ALD deposition temperatures between 125 and 250 °C result in stoichiometric films with high oxidative stability, yielding a dielectric strength of 8.2 MV/cm. Utilizing a seed-free ALD approach, we form uniform aBN dielectric layers on 2D surfaces and fabricate multiple quantum well structures of aBN/MoS2 and aBN-encapsulated double-gated monolayer (ML) MoS2 field-effect transistors to evaluate the impact of aBN dielectric environment on MoS2 optoelectronic and electronic properties. Our work in scalable aBN dielectric integration paves a way towards realizing the theoretical performance of 2D materials for next-generation electronics.

Mechanism of Fermi Level Pinning for Metal Contacts on Molybdenum Dichalcogenide

The high contact resistance of transition metal dichalcogenide (TMD)-based devices is receiving considerable attention due to its limitation on electronic performance. The mechanism of Fermi level (EF) pinning, which causes the high contact resistance, is not thoroughly understood to date. In this study, the metal (Ni and Ag)/Mo-TMD surfaces and interfaces are characterized by X-ray photoelectron spectroscopy, atomic force microscopy, scanning tunneling microscopy and spectroscopy, and density functional theory systematically. Ni and Ag form covalent and van der Waals (vdW) interfaces on Mo-TMDs, respectively. Imperfections are detected on Mo-TMDs, which lead to electronic and spatial variations. Gap states appear after the adsorption of single and two metal atoms on Mo-TMDs. The combination of the interface reaction type (covalent or vdW), the imperfection variability of the TMD materials, and the gap states induced by contact metals with different weights are concluded to be the origins of EF pinning.

Review-Extremely Thin Amorphous Indium Oxide Transistors

Amorphous oxide semiconductor transistors have been a mature technology in display panels for upward of a decade, and have recently been considered as promising back-end-of-line compatible channel materials for monolithic 3D applications. However, achieving high-mobility amorphous semiconductor materials with comparable performance to traditional crystalline semiconductors has been a long-standing problem. Recently it has been found that greatly reducing the thickness of indium oxide, enabled by an atomic layer deposition (ALD) process, can tune its material properties to achieve high mobility, high drive current, high on/off ratio, and enhancement-mode operation at the same time, beyond the capabilities of conventional oxide semiconductor materials. In this work, the history leading to the re-emergence of indium oxide, its fundamental material properties, growth techniques with a focus on ALD, state-of-the-art indium oxide device research, and the bias stability of the devices are reviewed.

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping

The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks in which desired junction is formed by van der Waals (vdW) integration and selective oxygen plasma-doping into spacer regions. The exceptional electrostatic controllability with a high on/off current ratio and small subthreshold swing (SS) of plasma doped p-FETs is achieved with the self-aligned metal/hBN gate stacks. To demonstrate the effectiveness of our approach, we construct a PMOS inverter using this device architecture, which exhibits a remarkably low power consumption of approximately 4.5 nW.

Modulation of Contact Resistance of Dual-Gated MoS2 FETs Using Fermi-Level Pinning-Free Antimony Semi-Metal Contacts

Achieving low contact resistance (R_C ) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS₂ devices are systematically analyzed as a function of top and bottom gate-voltages (V_TG and V_BG ). The semimetal contacts not only significantly reduce R_C but also induce a strong dependence of R_C on V_TG , in sharp contrast to Ti contacts that only modulate R_C by varying V_BG . The anomalous behavior is attributed to the strongly modulated pseudo-junction resistance (R_jun ) by V_TG , resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by V_TG as metal screens the electric field from the applied V_TG . Technology computer aided design simulations further confirm the contribution of V_TG to R_jun , which improves overall R_C of Sb-contacted MoS₂ devices. Consequently, the Sb contact has a distinctive merit in dual-gated (DG) device structure, as it greatly reduces R_C and enables effective gate control by both V_BG and V_TG . The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals.

Ballistic two-dimensional InSe transistors

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm-1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V-1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.