Fringing-field dielectrophoretic assembly of ultrahigh-density semiconducting nanotube arrays with a self-limited pitch

Tether-scanning the kinesin motor domain reveals a core mechanical action

Natural kinesin motors are tethered to their cargoes via short C-terminal or N-terminal linkers, whose docking against the core motor domain generates directional force. It remains unclear whether linker docking is the only process contributing directional force or whether linker docking is coupled to and amplifies an underlying, more fundamental force-generating mechanical cycle of the kinesin motor domain. Here, we show that kinesin motor domains tethered via double-stranded DNAs (dsDNAs) attached to surface loops drive robust microtubule (MT) gliding. Tethering using dsDNA attached to surface loops disconnects the C-terminal neck-linker and the N-terminal cover strand so that their dock-undock cycle cannot exert force. The most effective attachment positions for the dsDNA tether are loop 2 or loop 10, which lie closest to the MT plus and minus ends, respectively. In three cases, we observed minus-end-directed motility. Our findings demonstrate an underlying, potentially ancient, force-generating core mechanical action of the kinesin motor domain, which drives, and is amplified by, linker docking.

On-Demand Tunable Electrical Conductance Anisotropy in a MOF-Polymer Composite

Property optimization through orientation control of metal-organic framework (MOF) crystals that exhibit anisotropic crystal structures continues to garner tremendous interest. Herein, an electric field is utilized to post-synthetically control the orientation of conductive layered Cu3(HHTP)2 (HHTP = 2,3,6,7,10,11-hexahydroxytriphenylene) crystals dispersed in an electronically insulating poly(ethylene glycol) diacrylate (PEGDA) oligomer matrix. Optical and electrical measurements are performed to investigate the impact of the electric field on the alignment of Cu3(HHTP)2 crystals and the formation of aggregated microstructures, which leads to an ≈5000-fold increase in the conductivity of the composite. Notably, the composite thin-films containing aligned Cu3(HHTP)2 crystals exhibit significant conductivity of ≈10-3 S cm-1 despite the low concentration (≈1 wt.%) of conductive Cu3(HHTP)2. The use of an electric field to align Cu3(HHTP)2 crystals can rapidly generate various desired patterns that exhibit on-demand tunable collective charge transport anisotropy. The findings provide valuable insights toward the manipulation and utilization of conductive MOFs with anisotropic crystal structures for various applications such as adhesive electrical interconnects and microelectronics.

Biotemplated precise assembly approach toward ultra-scaled high-performance electronics

Structural DNA nanotechnology can be programmed into complex designer structures with molecular precision for directing a wide range of inorganic and biological materials. However, the use of DNA-templated approaches for the fabrication and performance requirements of ultra-scaled semiconductor electronics is limited by its assembly disorder and destructive interface composition. In this protocol, using carbon nanotubes (CNTs) as model semiconductors, we provide a stepwise process to build ultra-scaled, high-performance field-effect transistors (FETs) from micron-scale three-dimensional DNA templates. We apply the approach to assemble CNT arrays with uniform pitches scaled between 24.1 and 10.4 nm with yields of more than 95%, which exceeds the resolution limits of conventional lithography. To achieve highly clean CNT interfaces, we detail a rinsing-after-fixing step to remove residual DNA template and salt contaminations present around the contact and the channel regions, without modifying the alignment of the CNT arrays. The DNA-templated CNT FETs display both high on-state current (4-15 μA per CNT) and small subthreshold swing (60-100 mV per decade), which are superior to previous examples of biotemplated electronics and match the performance metrics of high-performance, silicon-based electronics. The scalable assembly of defect-free three-dimensional DNA templates requires 1 week and the CNT arrays can be synthesized within half a day. The interface engineering requires 1-2 d, while the fabrication of high-performance FET and logic gate circuits requires 2-4 d. The structural and performance characterizations of molecular-precise DNA self-assembly and high-performance electronics requires 1-2 d. The protocol is suited for users with expertise in DNA nanotechnology and semiconductor electronics.

The future transistors

The metal-oxide-semiconductor field-effect transistor (MOSFET), a core element of complementary metal-oxide-semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

Dielectrophoretic alignment of carbon nanotubes: theory, applications, and future

Carbon nanotubes (CNTs) are nominated to be the successor of several semiconductors and metals due to their unique physical and chemical properties. It has been concerning that the anisotropic and low controllability of CNTs impedes their adoption in commercial applications. Dielectrophoresis (DEP) is known as the electrokinetics motion of polarizable nanoparticles under the influence of nonuniform electric fields. The uniqueness of this phenomenon allows DEP to be employed as a novel method to align, assemble, separate, and manipulate CNTs suspended in liquid mediums. This article begins with a brief overview of CNT structure and production, with the emphasize on their electrical properties and response to electric fields. The DEP phenomenon as a CNT alignment method is demonstrated and graphically discussed, along with its theory, procedure, and parameters. We also discussed the side forces that arise in DEP systems and how they negatively or positively affect the CNT alignment. The article concludes with a brief review of CNT-based devices fabricated using DEP, as well as the method's limitations and future prospects.

Controlled Preparation of Single-Walled Carbon Nanotubes as Materials for Electronics

Single-walled carbon nanotubes (SWCNTs) are of particular interest as channel materials for field-effect transistors due to their unique structure and excellent properties. The controlled preparation of SWCNTs that meet the requirement of semiconducting and chiral purity, high density, and good alignment for high-performance electronics has become a key challenge in this field. In this Outlook, we outline the efforts in the preparation of SWCNTs for electronics from three main aspects, structure-controlled growth, selective sorting, and solution assembly, and discuss the remaining challenges and opportunities. We expect that this Outlook can provide some ideas for addressing the existing challenges and inspire the development of SWCNT-based high-performance electronics.

Directed Assembly of Nanomaterials for Making Nanoscale Devices and Structures: Mechanisms and Applications

Nanofabrication has been utilized to manufacture one-, two-, and three-dimensional functional nanostructures for applications such as electronics, sensors, and photonic devices. Although conventional silicon-based nanofabrication (top-down approach) has developed into a technique with extremely high precision and integration density, nanofabrication based on directed assembly (bottom-up approach) is attracting more interest recently owing to its low cost and the advantages of additive manufacturing. Directed assembly is a process that utilizes external fields to directly interact with nanoelements (nanoparticles, 2D nanomaterials, nanotubes, nanowires, etc.) and drive the nanoelements to site-selectively assemble in patterned areas on substrates to form functional structures. Directed assembly processes can be divided into four different categories depending on the external fields: electric field-directed assembly, fluidic flow-directed assembly, magnetic field-directed assembly, and optical field-directed assembly. In this review, we summarize recent progress utilizing these four processes and address how these directed assembly processes harness the external fields, the underlying mechanism of how the external fields interact with the nanoelements, and the advantages and drawbacks of utilizing each method. Finally, we discuss applications made using directed assembly and provide a perspective on the future developments and challenges.

Carbon nanotube transistors: Making electronics from molecules

Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementation to devices that work in conjunction with silicon electronics, and can potentially be used as a platform for high-performance digital electronics as well as radio-frequency and sensing applications. Recent progress in the materials, devices, and technologies related to carbon nanotube transistors is briefly reviewed. Emphasis is placed on the most broadly impactful advancements that have evolved from single-nanotube devices to implementations with aligned nanotubes and even nanotube thin films. There are obstacles that remain to be addressed, including material synthesis and processing control, device structure design and transport considerations, and further integration demonstrations with improved reproducibility and reliability; however, the integration of more than 10,000 devices in single functional chips has already been realized.

Scalable Self-Limiting Dielectrophoretic Trapping for Site-Selective Assembly of Nanoparticles

The absence of a versatile, scalable, and defect-free bottom-up assembly of nanoparticles with high precision has been a longstanding roadblock facing the large-scale integration of diverse nanoparticle-based devices. To circumvent this roadblock, we present a self-limiting dielectrophoretic approach to precisely align nanoparticles onto an array of electrodes over a large area, assisted by lithographically defined capacitors in series with the electrodes. We have experimentally verified that the on-chip capacitor can reduce the probability of trapping multiple particles at a given site, as the electric field is greatly weakened after the first nanoparticle bridges the electrodes. A 70% yield of single-nanowire assembly has been achieved, and key factors limiting the current yield are discussed. The yield is expected to further increase by improving the nanoparticle-electrode contact and reducing the capillary force during the drying process. We also demonstrate the versatility of this approach for scalable and site-selective alignment of various nanoparticles.

Confined Fe Catalysts for High-Density SWNT Arrays Growth: a New Territory for Catalyst-Substrate Interaction Engineering

Great efforts have been devoted to searching for efficient catalytic systems to produce ultra-high density single-walled carbon nanotube (SWNT) arrays, which lay the foundation for future electronic devices. However, one major obstacle for realizing high-density surface-aligned SWNT arrays is the poor stability of metal nanoparticles in chemical vapor deposition catalytic processes. Recently, Trojan catalyst has been reported to yield unprecedented high-density SWNT arrays with 130 SWNTs per µm on the a-plane (11-20) of the sapphire substrate. Herein, a concept of catalyst confinement effect is put forward to revealing the secret of remarkable growth efficiency of SWNT arrays by Trojan catalyst. Combined experimental and theoretical studies indicate that confinement of catalyst nanoparticles on discrete a-plane strips plays a key role in stabilizing the small nanoparticles. The highly dispersive and active states of catalysts are maintained, which promote the growth of super-dense SWNT arrays. By rationally designing the substrate reconstruction process, large areas of dense SWNT arrays (130 SWNTs per µm) covering the entire substrate are obtained. This approach may provide novel ideas for the synthesis of various high-density 1D nanomaterials.

Chirality-Enriched Carbon Nanotubes for Next-Generation Computing

For the past half century, silicon has served as the primary material platform for integrated circuit technology. However, the recent proliferation of nontraditional electronics, such as wearables, embedded systems, and low-power portable devices, has led to increasingly complex mechanical and electrical performance requirements. Among emerging electronic materials, single-walled carbon nanotubes (SWCNTs) are promising candidates for next-generation computing as a result of their superlative electrical, optical, and mechanical properties. Moreover, their chirality-dependent properties enable a wide range of emerging electronic applications including sub-10 nm complementary field-effect transistors, optoelectronic integrated circuits, and enantiomer-recognition sensors. Here, recent progress in SWCNT-based computing devices is reviewed, with an emphasis on the relationship between chirality enrichment and electronic functionality. In particular, after highlighting chirality-dependent SWCNT properties and chirality enrichment methods, the range of computing applications that have been demonstrated using chirality-enriched SWCNTs are summarized. By identifying remaining challenges and opportunities, this work provides a roadmap for next-generation SWCNT-based computing.

Precise pitch-scaling of carbon nanotube arrays within three-dimensional DNA nanotrenches

Precise fabrication of semiconducting carbon nanotubes (CNTs) into densely aligned evenly spaced arrays is required for ultrascaled technology nodes. We report the precise scaling of inter-CNT pitch using a supramolecular assembly method called spatially hindered integration of nanotube electronics. Specifically, by using DNA brick crystal-based nanotrenches to align DNA-wrapped CNTs through DNA hybridization, we constructed parallel CNT arrays with a uniform pitch as small as 10.4 nanometers, at an angular deviation <2° and an assembly yield >95%.

Nanoscale Patterning of Carbon Nanotubes: Techniques, Applications, and Future

Carbon nanotube (CNT) devices and electronics are achieving maturity and directly competing or surpassing devices that use conventional materials. CNTs have demonstrated ballistic conduction, minimal scaling effects, high current capacity, low power requirements, and excellent optical/photonic properties; making them the ideal candidate for a new material to replace conventional materials in next-generation electronic and photonic systems. CNTs also demonstrate high stability and flexibility, allowing them to be used in flexible, printable, and/or biocompatible electronics. However, a major challenge to fully commercialize these devices is the scalable placement of CNTs into desired micro/nanopatterns and architectures to translate the superior properties of CNTs into macroscale devices. Precise and high throughput patterning becomes increasingly difficult at nanoscale resolution, but it is essential to fully realize the benefits of CNTs. The relatively long, high aspect ratio structures of CNTs must be preserved to maintain their functionalities, consequently making them more difficult to pattern than conventional materials like metals and polymers. This review comprehensively explores the recent development of innovative CNT patterning techniques with nanoscale lateral resolution. Each technique is critically analyzed and applications for the nanoscale-resolution approaches are demonstrated. Promising techniques and the challenges ahead for future devices and applications are discussed.

Solution-Processing of High-Purity Semiconducting Single-Walled Carbon Nanotubes for Electronics Devices

High-purity semiconducting single-walled carbon nanotubes (s-SWCNTs) are of paramount significance for the construction of next-generation electronics. Until now, a number of elaborate sorting and purification techniques for s-SWCNTs have been developed, among which solution-based sorting methods show unique merits in the scale production, high purity, and large-area film formation. Here, the recent progress in the solution processing of s-SWCNTs and their application in electronic devices is systematically reviewed. First, the solution-based sorting and purification of s-SWCNTs are described, and particular attention is paid to the recent advance in the conjugated polymer-based sorting strategy. Subsequently, the solution-based deposition and morphology control of a s-SWCNT thin film on a surface are introduced, which focus on the strategies for network formation and alignment of SWCNTs. Then, the recent advances in electronic devices based on s-SWCNTs are reviewed with emphasis on nanoscale s-SWCNTs' high-performance integrated circuits and s-SWCNT-based thin-film transistors (TFT) array and circuits. Lastly, the existing challenges and development trends for the s-SWCNTs and electronic devices are briefly discussed. The aim is to provide some useful information and inspiration for the sorting and purification of s-SWCNTs, as well as the construction of electronic devices with s-SWCNTs.

A review of polystyrene bead manipulation by dielectrophoresis

Exploitation of the intrinsic electrical properties of particles has recently emerged as an appealing approach for trapping and separating various scaled particles. Initiative particle manipulation by dielectrophoresis (DEP) showed remarkable advantages including high speed, ease of handling, high precision and being label-free. Herein, we provide a general overview of the manipulation of polystyrene (PS) beads and related particles via DEP; especially, the wide applications of these manipulated PS beads in the quantitative evaluation of device performance for model validation and standardization have been discussed. The motion and polarizability of the PS beads induced by DEP were analyzed and classified into two categories as positive and negative DEP within the time and space domains. The DEP techniques used for bioparticle manipulation were demonstrated, and their applications were conducted in four fields: trapping of single-sized PS beads, separation of multiple-sized PS beads by size, separation of PS beads and non-bioparticles, and separation of PS beads and bioparticles. Finally, future perspectives on DEP-on-a-chip have been proposed to discriminate bio-targets in the network of microfluidic channels.

A 3D nanoelectrokinetic model for predictive assembly of nanowire arrays using floating electrode dielectrophoresis

Floating electrode dielectrophoresis (FE-DEP) presents a promising avenue for scalable assembly of nanowire (NW) arrays on silicon chips and offers better control in limiting the number of deposited NWs when compared with the conventional, two-electrode DEP process. This article presents a 3D nanoelectrokinetic model, which calculates the imposed electric field and its resultant NW force/velocity maps within the region of influence of an electrode array operating in the FE-DEP configuration. This enables the calculation of NW trajectories and their eventual localization sites on the target electrodes as a function of parameters such as NW starting position, NW size, the applied electric field, suspension concentration, and deposition time. The accuracy of this model has been established through a direct quantitative comparison with the assembly of manganese dioxide NW arrays. Further analysis of the computed data reveals interesting insights into the following aspects: (a) asymmetry in NW localization at electrode sites, and (b) the workspace regions from which NWs are drawn to assemble such that their center-of-mass is located either in the inter-electrode gap region (desired) or on top of one of the assembly electrodes (undesired). This analysis is leveraged to outline a strategy, which involves a physical confinement of the NW suspension within lithographically patterned reservoirs during assembly, for single NW deposition across large arrays with high estimated assembly yields on the order of 87%.

Assembly of Highly Aligned Carbon Nanotubes Using an Electro-Fluidic Assembly Process

Carbon nanotubes (CNTs) are promising building blocks for emerging wearable electronics and sensors due to their outstanding electrical and mechanical properties. However, the practical applications of the CNTs face challenges of efficiently and precisely placing them at the desired location with controlled orientation and density. Here, we introduce an electro-fluidic assembly process to assemble highly aligned and densely packed CNTs selectively on a substrate with patterned wetted areas at a high rate. An electric field is applied during the electro-fluidic assembly process, which drives the CNTs close to the patterned regions and shortens the assembly time. Meanwhile, the electric field orientates the CNTs perpendicular to the substrate and anchors one end of the CNTs onto the substrate. When pulling the substrate out of the CNT suspension, the capillary force at the air-water-substrate interface stretches the free end of the CNTs and aligns the CNTs along the pulling direction. By adjusting two governing parameters, the direct current voltage and the pulling speed, we have demonstrated well aligned CNTs assembled in patterns with widths from 1 to 100 μm and lengths from 20 to 120 μm at a rate 20 times higher than a fluidic assembly process. The aligned CNTs show improved electrical conductivity compared with the random networks and prove possibility for strain detection. Precise and reproducible control of the orientation and the placement of the CNTs opens up their practical application in the next-generation electronics and sensors.

Carbon-nanotube-on-waveguide thermo-optic tuners

We demonstrate on-waveguide thermo-optic tuners based on solution-processed metallic carbon nanotubes (CNTs) on silicon-on-insulator (SOI) and silicon nitride (SiN) microring resonators operating around 1550 nm. On SOI microring resonators using planarized wire waveguides, a thermo-optic power efficiency of 29 mW/FSR and a thermal transient of 1.3 μs are achieved. The heater is shown to be more power-efficient than conventional metal heaters and has lower thermal transient than both metal heaters and graphene-based heaters. On SiN microring resonators using rib waveguides, improvement in power efficiency with an increase in coverage of CNTs is demonstrated, indicating localized heating using the CNTs; this is favorable for low thermal cross-talk. An optimal power efficiency of 142 mW/FSR and a thermal transient of 5.8 μs are achieved.

Microwave-Assisted Regeneration of Single-Walled Carbon Nanotubes from Carbon Fragments

Direct growth of chirality-controlled single-walled carbon nanotubes (SWNTs) with metal catalyst free strategy, like cloning or epitaxial growth, has suffered from the low efficiency. The underlying problem is the activation of seed edge. Here an unexpectedly efficient microwave-assisted pathway to regenerate SWNTs from carbon fragments on SiO₂ /Si substrate is demonstrated via Raman spectroscopy and atomic force microscope (AFM) characterization. In this attempt, microwave irradiation provides fast heating to remove polar groups bonded to carbon nanotubes and reduce the spontaneous closure of tubes' open ends. The survived SWNT and carbon fragments connected to it after plasma treatment are simply microwaved and then they serve as the template for regeneration. Scanning electron microscope and AFM characterizations indicate that the efficiency of the regeneration can reach 100%. And the regenerated SWNT has been proved without any change in chirality compared to the original SWNT. Electrical measurements on regenerated carbon nanotube films indicate 1 and 2 times increase in on/off ratio and on-state current respectively than original carbon nanotube films obtained from solution-phase separation, confirming the improvement of SWNT's quality. The microwave-assisted regeneration is found to be highly effective and would be applied to improve the cloning efficiency of carbon nanotubes potentially.

Scalable Preparation of High-Density Semiconducting Carbon Nanotube Arrays for High-Performance Field-Effect Transistors

Although chemical vapor deposition (CVD)-grown carbon nanotube (CNT) arrays are considered ideal materials for constructing high-performance field-effect transistors (FETs) and integrated circuits (ICs), a significant gap remains between the required and achieved densities and purities of CNT arrays. Here, we develop a directional shrinking transfer method to realize up to 10-fold density amplification of CNT array films without introducing detectable damage or defects. In addition, the method improves the film uniformity while retaining the perfect alignment and high carrier mobility of 1600 cm² V^-1 s^-1 of CVD-grown CNT arrays. By combining the density amplification method with the thermocapillary flow method developed by Rogers et al., semiconducting CNT arrays with high densities and high qualities are obtained. High-performance FETs with a channel length of 200 nm are demonstrated using these high-density semiconducting CNT arrays, yielding a record-high on-state current density of 150 μA/μm, a peak transconductance of 80 μS/μm, and a current on/off ratio of more than 10⁴ among the CVD-grown CNT-based FETs.

Carbon nanotube radio-frequency electronics

Carbon nanotube (CNT) is considered a promising material for radio-frequency (RF) applications, owing to its high carrier mobility and saturated drift velocity, as well as ultra-small intrinsic gate capacitance. Here, we review progress on CNT-based devices and integrated circuits for RF applications, including theoretical projection of RF performance of CNT-based devices, preparation of CNT materials, fabrication, optimization of RF field-effect transistors (FETs) structures, and ambipolar FET-based RF applications, and we outline challenges and prospects of CNT-based RF applications.

Assembly and Electronic Applications of Colloidal Nanomaterials

Artificial solids and thin films assembled from colloidal nanomaterials give rise to versatile properties that can be exploited in a range of technologies. In particular, solution-based processes allow for the large-scale and low-cost production of nanoelectronics on rigid or mechanically flexible substrates. To achieve this goal, several processing steps require careful consideration, including nanomaterial synthesis or exfoliation, purification, separation, assembly, hybrid integration, and device testing. Using a ubiquitous electronic device - the field-effect transistor - as a platform, colloidal nanomaterials in three electronic material categories are reviewed systematically: semiconductors, conductors, and dielectrics. The resulting comparative analysis reveals promising opportunities and remaining challenges for colloidal nanomaterials in electronic applications, thereby providing a roadmap for future research and development.

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (V_TH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs.

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

Length-Sorted, Large-Diameter, Polyfluorene-Wrapped Semiconducting Single-Walled Carbon Nanotubes for High-Density, Short-Channel Transistors

Samples of highly enriched semiconducting SWCNTs with average diameters of 1.35 nm have been prepared by combining PODOF polymer wrapping with size-exclusion chromatography. The purity of the material was determined to be >99.7% from the transfer characteristics of short-channel transistors comprising densely aligned sc-SWCNTs. The transistors have a hole mobility of up to 297 cm(2)V(-1) s(-1) and an On/Off ratio as high as 2 × 10(8).

Recent Progress in Obtaining Semiconducting Single-Walled Carbon Nanotubes for Transistor Applications

High purity semiconducting single-walled carbon nanotubes (s-SWCNTs) with a narrow diameter distribution are required for high-performance transistors. Achieving this goal is extremely challenging because the as-grown material contains mixtures of s-SWCNTs and metallic- (m-) SWCNTs with wide diameter distributions, typically inadequate for integrated circuits. Since 2000, numerous ex situ methods have been proposed to improve the purity of the s-SWCNTs. The majority of these techniques fail to maintain the quality and integrity of the s-SWCNTs with a few notable exceptions. Here, the progress in realizing high purity s-SWCNTs in as-grown and post-processed materials is highlighted. A comparison of transistor parameters (such as on/off ratio and field-effect mobility) obtained from test structures establishes the effectiveness of various methods and suggests opportunities for future improvements.

Directed Assembly of Ultrathin Gold Nanowires over Large Area by Dielectrophoresis

Ultrathin Au nanowires (∼2 nm diameter) are interesting from a fundamental point of view to study structure and electronic transport and also hold promise in the field of nanoelectronics, particularly for sensing applications. Device fabrication by direct growth on various substrates has been useful in demonstrating some of the potential applications. However, the realization of practical devices requires device fabrication strategies that are fast, inexpensive, and efficient. Herein, we demonstrate directed assembly of ultrathin Au nanowires over large areas across electrodes using ac dielectrophoresis with a mechanistic understanding of the process. On the basis of the voltage and frequency, the wires either align in between or across the contact pads. We exploit this assembly to produce an array of contacting wires for statistical estimation of electrical transport with important implications for future nanoelectronic/sensor applications.

High mobility flexible graphene field-effect transistors and ambipolar radio-frequency circuits

Field-effect transistors (GFETs) were fabricated on mechanically flexible substrates using chemical vapor deposition grown graphene. High current density (nearly 200 μA μm(-1)) with saturation, almost perfect ambipolar electron-hole behavior, high transconductance (120 μS μm(-1)) and good stability over 381 days were obtained. The average carrier mobility for holes (electrons) is 13,540 cm(2) V(-1) s(-1) (12,300 cm(2) V(-1) s(-1)) with the highest value over 24,000 cm(2) V(-1) s(-1) (20,000 cm(2) V(-1) s(-1)) obtained in flexible GFETs. Ambipolar radio-frequency circuits, frequency doubler, were constructed based on the high performed flexible GFET, which show record high output power spectra purity (∼97%) and high conversion gain of -13.6 dB. Bending measurements show the flexible GFETs are able to work under modest strain. These results show that flexible GFETs are a very promising option for future flexible radio-frequency electronics.

Large-area assembly of densely aligned single-walled carbon nanotubes using solution shearing and their application to field-effect transistors

Dense alignment of single-walled carbon nanotubes over a large area is demonstrated using a novel solution-shearing technique. A density of 150-200 single-walled carbon nanotubes per micro-meter is achieved with a current density of 10.08 μA μm(-1) at VDS = -1 V. The on-current density is improved by a factor of 45 over that of random-network single-walled carbon nanotubes.

Origins and characteristics of the threshold voltage variability of quasiballistic single-walled carbon nanotube field-effect transistors

Ultrascaled transistors based on single-walled carbon nanotubes are identified as one of the top candidates for future microprocessor chips as they provide significantly better device performance and scaling properties than conventional silicon technologies. From the perspective of the chip performance, the device variability is as important as the device performance for practical applications. This paper presents a systematic investigation on the origins and characteristics of the threshold voltage (VT) variability of scaled quasiballistic nanotube transistors. Analysis of experimental results from variable-temperature measurement as well as gate oxide thickness scaling studies shows that the random variation from fixed charges present on the oxide surface close to nanotubes dominates the VT variability of nanotube transistors. The VT variability of single-tube transistors has a figure of merit that is quantitatively comparable with that of current silicon devices; and it could be reduced with the adoption of improved device passivation schemes, which might be necessary for practical devices incorporating multiple nanotubes, whose area normalized VT variability becomes worse due to the synergic effects from the limited surface coverage of nanotubes and the nonlinearity of the device off-state leakage current, as predicted by the Monte Carlo simulation.

Laser-induced nanoscale thermocapillary flow for purification of aligned arrays of single-walled carbon nanotubes

Although aligned arrays of single-walled carbon nanotubes (SWNTs) have outstanding potential for use in broad classes of advanced semiconductor devices, the relatively large population of metallic SWNTs (m-SWNTs) that results from conventional growth techniques leads to significantly degraded performance. Recently reported methods based on thermocapillary effects that enable removal of m-SWNTs from such arrays offer exceptional levels of efficiency, but the procedures are cumbersome and require multiple processing steps. Here we present a simple, robust alternative that yields pristine arrays of purely semiconducting SWNTs (s-SWNTs) by use of irradiation with an infrared laser. Selective absorption by m-SWNTs coated with a thin organic film initiates nanoscale thermocapillary flows that lead to exposure only of the m-SWNTs. Reactive ion etching eliminates the m-SWNTs without damaging the s-SWNTs; removal of the film completes the purification. Systematic experimental studies and computational modeling of the thermal physics illuminates the essential aspects of this process. Demonstrations include use of arrays of s-SWNTs formed in this manner as semiconducting channel materials in statistically relevant numbers of transistors to achieve both high mobilities (>900 cm2 V(-1) s(-1)) and switching ratios (>10(4)). Statistical analysis indicates that the arrays contain at least 99.8% s-SWNTs and likely significantly higher.