Memory devices and applications for in-memory computing

SSTE: Syllable-Specific Temporal Encoding to FORCE-learn audio sequences with an associative memory approach

The circuitry and pathways in the brains of humans and other species have long inspired researchers and system designers to develop accurate and efficient systems capable of solving real-world problems and responding in real-time. We propose the Syllable-Specific Temporal Encoding (SSTE) to learn vocal sequences in a reservoir of Izhikevich neurons, by forming associations between exclusive input activities and their corresponding syllables in the sequence. Our model converts the audio signals to cochleograms using the CAR-FAC model to simulate a brain-like auditory learning and memorization process. The reservoir is trained using a hardware-friendly approach to FORCE learning. Reservoir computing could yield associative memory dynamics with far less computational complexity compared to RNNs. The SSTE-based learning enables competent accuracy and stable recall of spatiotemporal sequences with fewer reservoir inputs compared with existing encodings in the literature for similar purpose, offering resource savings. The encoding points to syllable onsets and allows recalling from a desired point in the sequence, making it particularly suitable for recalling subsets of long vocal sequences. The SSTE demonstrates the capability of learning new signals without forgetting previously memorized sequences and displays robustness against occasional noise, a characteristic of real-world scenarios. The components of this model are configured to improve resource consumption and computational intensity, addressing some of the cost-efficiency issues that might arise in future implementations aiming for compactness and real-time, low-power operation. Overall, this model proposes a brain-inspired pattern generation network for vocal sequences that can be extended with other bio-inspired computations to explore their potentials for brain-like auditory perception. Future designs could inspire from this model to implement embedded devices that learn vocal sequences and recall them as needed in real-time. Such systems could acquire language and speech, operate as artificial assistants, and transcribe text to speech, in the presence of natural noise and corruption on audio data.

Voltage control of multiferroic magnon torque for reconfigurable logic-in-memory

Magnons, bosonic quasiparticles carrying angular momentum, can flow through insulators for information transmission with minimal power dissipation. However, it remains challenging to develop a magnon-based logic due to the lack of efficient electrical manipulation of magnon transport. Here we show the electric excitation and control of multiferroic magnon modes in a spin-source/multiferroic/ferromagnet structure. We demonstrate that the ferroelectric polarization can electrically modulate the magnon-mediated spin-orbit torque by controlling the non-collinear antiferromagnetic structure in multiferroic bismuth ferrite thin films with coupled antiferromagnetic and ferroelectric orders. In this multiferroic magnon torque device, magnon information is encoded to ferromagnetic bits by the magnon-mediated spin torque. By manipulating the two coupled non-volatile state variables-ferroelectric polarization and magnetization-we further present reconfigurable logic operations in a single device. Our findings highlight the potential of multiferroics for controlling magnon information transport and offer a pathway towards room-temperature voltage-controlled, low-power, scalable magnonics for in-memory computing.

2D Reconfigurable Memory Device Enabled by Defect Engineering for Multifunctional Neuromorphic Computing

In this era of artificial intelligence and Internet of Things, emerging new computing paradigms such as in-sensor and in-memory computing call for both structurally simple and multifunctional memory devices. Although emerging two-dimensional (2D) memory devices provide promising solutions, the most reported devices either suffer from single functionalities or structural complexity. Here, this work reports a reconfigurable memory device (RMD) based on MoS2/CuInP2S6 heterostructure, which integrates the defect engineering-enabled interlayer defects and the ferroelectric polarization in CuInP2S6, to realize a simplified structure device for all-in-one sensing, memory and computing. The plasma treatment-induced defect engineering of the CuInP2S6 nanosheet effectively increases the interlayer defect density, which significantly enhances the charge-trapping ability in synergy with ferroelectric properties. The reported device not only can serve as a non-volatile electronic memory device, but also can be reconfigured into optoelectronic memory mode or synaptic mode after controlling the ferroelectric polarization states in CuInP2S6. When operated in optoelectronic memory mode, the all-in-one RMD could diagnose ophthalmic disease by segmenting vasculature within biological retinas. On the other hand, operating as an optoelectronic synapse, this work showcases in-sensor reservoir computing for gesture recognition with high energy efficiency.

Hardware implementation of backpropagation using progressive gradient descent for in situ training of multilayer neural networks

Neural network training can be slow and energy-expensive due to the frequent transfer of weight data between digital memory and processing units. Neuromorphic systems can accelerate neural networks by performing multiply-accumulate operations in parallel using nonvolatile analog memory. However, executing the widely used backpropagation training algorithm in multilayer neural networks requires information-and therefore storage-of the partial derivatives of the weight values preventing suitable and scalable implementation in hardware. Here, we propose a hardware implementation of the backpropagation algorithm that progressively updates each layer using in situ stochastic gradient descent, avoiding this storage requirement. We experimentally demonstrate the in situ error calculation and the proposed progressive backpropagation method in a multilayer hardware-implemented neural network. We confirm identical learning characteristics and classification performance compared to conventional backpropagation in software. We show that our approach can be scaled to large and deep neural networks, enabling highly efficient training of advanced artificial intelligence computing systems.

Multifunctional In-Memory Logics Based on a Dual-Gate Antiambipolar Transistor toward Non-von Neumann Computing Architecture

In-memory computing may make it possible to realize non-von Neumann computing because the logic circuits are unified in the memory units. We investigated two types of in-memory logic operations, namely, two-input logic circuits and multifunctional artificial synapses. These were realized in a dual-gate antiambipolar transistor (AAT) with a ReS2/WSe2 heterojunction, in which polystyrene with a zinc phthalocyanine core (ZnPc-PS4) was incorporated as a memory layer. Here, reconfigurability is a key concept for both types of device operations and was achieved by merging the Λ-shaped transfer curve of the AAT and the nonvolatile memory effect of ZnPc-PS4. First, we achieved electrically reconfigurable two-input logic circuits. Versatile logic circuits such as AND, OR, NAND, NOR, and XOR circuits were demonstrated by taking advantage of the Λ-shaped transfer curve of the dual-gate AAT. Importantly, the nonvolatile memory function provided the electrical switching of the individual circuits between AND/OR, NAND/NOR, and XOR/NAND circuits with constant input signals. Second, the memory effect was applied to multifunctional artificial synapses. The inhibitory/excitatory and long-term potentiation/depression synaptic operations were electrically reconfigured simply by controlling one parameter (readout voltage), making three distinct responses possible even with the same presynaptic signals. These findings provide hints that may lead to the realization of new in-memory computing architectures beyond the current von Neumann computers.

High-Performance 2D Ambipolar MoTe2 Lateral Memristors by Mild Oxidation

2D transition metal dichalcogenides (TMDCs) have been intensively explored in memristors for brain-inspired computing. Oxidation, which is usually unavoidable and harmful in 2D TMDCs, could also be used to enhance their memristive performances. However, it is still unclear how oxidation affects the resistive switching behaviors of 2D ambipolar TMDCs. In this work, a mild oxidation strategy is developed to greatly enhance the resistive switching ratio of ambipolar 2H-MoTe2 lateral memristors by more than 10 times. Such an enhancement results from the amplified doping due to O2 and H2O adsorption and the optimization of effective gate voltage distribution by mild oxidation. Moreover, the ambipolarity of 2H-MoTe2 also enables a change of resistive switching direction, which is uncommon in 2D memristors. Consequently, as an artificial synapse, the MoTe2 device exhibits a large dynamic range (≈200) and a good linearity (1.01) in long-term potentiation and depression, as well as a high-accuracy handwritten digit recognition (>96%). This work not only provides a feasible and effective way to enhance the memristive performance of 2D ambipolar materials, but also deepens the understanding of hidden mechanisms for RS behaviors in oxidized 2D materials.

Capacitive and Inductive Characteristics of Volatile Perovskite Resistive Switching Devices with Analog Memory

With the increasing demands and complexity of the neuromorphic computing schemes utilizing highly efficient analog resistive switching devices, understanding the apparent capacitive and inductive effects in device operation is of paramount importance. Here, we present a systematic array of characterization methods that unravel two distinct voltage-dependent regimes demonstrating the complex interplay between the dynamic capacitive and inductive effects in volatile perovskite-based memristors: (1) a low voltage capacitance-dominant and (2) an inductance-dominant regime evidenced by the highly correlated hysteresis type with nonzero crossing, the impedance responses, and the transient current characteristics. These dynamic capacitance- and inductance-dominant regimes provide fundamental insight into the resistive switching of memristors governing the synaptic depression and potentiation functions, respectively. More importantly, the pulse width-dependent and long-term transient current measurements further demonstrate a dynamic transition from a fast capacitive to a slow inductive response, allowing for the tailored stimulus programming of memristor devices to mimic synaptic functionality.

Reconfigurable spintronic logic gate utilizing precessional magnetization switching

In traditional von Neumann computing architecture, the efficiency of the system is often hindered by the data transmission bottleneck between the processor and memory. A prevalent approach to mitigate this limitation is the use of non-volatile memory for in-memory computing, with spin-orbit torque (SOT) magnetic random-access memory (MRAM) being a leading area of research. In this study, we numerically demonstrate that a precise combination of damping-like and field-like spin-orbit torques can facilitate precessional magnetization switching. This mechanism enables the binary memristivity of magnetic tunnel junctions (MTJs) through the modulation of the amplitude and width of input current pulses. Building on this foundation, we have developed a scheme for a reconfigurable spintronic logic gate capable of directly implementing Boolean functions such as AND, OR, and XOR. This work is anticipated to leverage the sub-nanosecond dynamics of SOT-MRAM cells, potentially catalyzing further experimental developments in spintronic devices for in-memory computing.

New-Generation Ferroelectric AlScN Materials

Ferroelectrics have great potential in the field of nonvolatile memory due to programmable polarization states by external electric field in nonvolatile manner. However, complementary metal oxide semiconductor compatibility and uniformity of ferroelectric performance after size scaling have always been two thorny issues hindering practical application of ferroelectric memory devices. The emerging ferroelectricity of wurtzite structure nitride offers opportunities to circumvent the dilemma. This review covers the mechanism of ferroelectricity and domain dynamics in ferroelectric AlScN films. The performance optimization of AlScN films grown by different techniques is summarized and their applications for memories and emerging in-memory computing are illustrated. Finally, the challenges and perspectives regarding the commercial avenue of ferroelectric AlScN are discussed.

Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator

We present the fabrication of 4 K-scale electrochemical random-access memory (ECRAM) cross-point arrays for analog neural network training accelerator and an electrical characteristic of an 8 × 8 ECRAM array with a 100% yield, showing excellent switching characteristics, low cycle-to-cycle, and device-to-device variations. Leveraging the advances of the ECRAM array, we showcase its efficacy in neural network training using the Tiki-Taka version 2 algorithm (TTv2) tailored for non-ideal analog memory devices. Through an experimental study using ECRAM devices, we investigate the influence of retention characteristics on the training performance of TTv2, revealing that the relative location of the retention convergence point critically determines the available weight range and, consequently, affects the training accuracy. We propose a retention-aware zero-shifting technique designed to optimize neural network training performance, particularly in scenarios involving cross-point devices with limited retention times. This technique ensures robust and efficient analog neural network training despite the practical constraints posed by analog cross-point devices.

Electrical switching of Ising-superconducting nonreciprocity for quantum neuronal transistor

Nonreciprocal quantum transport effect is mainly governed by the symmetry breaking of the material systems and is gaining extensive attention in condensed matter physics. Realizing electrical switching of the polarity of the nonreciprocal transport without external magnetic field is essential to the development of nonreciprocal quantum devices. However, electrical switching of superconducting nonreciprocity remains yet to be achieved. Here, we report the observation of field-free electrical switching of nonreciprocal Ising superconductivity in Fe3GeTe2/NbSe2 van der Waals (vdW) heterostructure. By taking advantage of this electrically switchable superconducting nonreciprocity, we demonstrate a proof-of-concept nonreciprocal quantum neuronal transistor, which allows for implementing the XOR logic gate and faithfully emulating biological functionality of a cortical neuron in the brain. Our work provides a promising pathway to realize field-free and electrically switchable nonreciprocity of quantum transport and demonstrate its potential in exploring neuromorphic quantum devices with both functionality and performance beyond the traditional devices.

Tunable ion energy barrier modulation through aliovalent halide doping for reliable and dynamic memristive neuromorphic systems

Memristive neuromorphic computing has emerged as a promising computing paradigm for the upcoming artificial intelligence era, offering low power consumption and high speed. However, its commercialization remains challenging due to reliability issues from stochastic ion movements. Here, we propose an innovative method to enhance the memristive uniformity and performance through aliovalent halide doping. By introducing fluorine concentration into dynamic TiO2-x memristors, we experimentally demonstrate reduced device variations, improved switching speeds, and enhanced switching windows. Atomistic simulations of amorphous TiO2-x reveal that fluoride ions attract oxygen vacancies, improving the reversible redistribution and uniformity. A number of migration barrier calculations statistically show that fluoride ions also reduce the migration energies of nearby oxygen vacancies, facilitating ionic diffusion and high-speed switching. The detailed Voronoi volume analysis further suggests design principles in terms of the migrating species' electrostatic repulsion and migration barriers. This work presents an innovative methodology for the fabrication of reliable memristor devices, contributing to the realization of hardware-based neuromorphic systems.

Variability in HfO2-based memristors described with a new bidimensional statistical technique

A new statistical analysis is presented to assess cycle-to-cycle variability in resistive memories. This method employs two-dimensional (2D) distributions of parameters to analyse both set and reset voltages and currents, coupled with a 2D coefficient of variation (CV). This 2D methodology significantly enhances the analysis, providing a more thorough and comprehensive understanding of the data compared to conventional one-dimensional methods. Resistive switching (RS) data from two different technologies based on hafnium oxide are used in the variability study. The 2D CV allows a more compact assessment of technology suitability for applications such as non-volatile memories, neuromorphic computing and random number generation circuits.

2D Halide Perovskites for High-Performance Resistive Switching Memory and Artificial Synapse Applications

Metal halide perovskites (MHPs) are considered as promising candidates in the application of nonvolatile high-density, low-cost resistive switching (RS) memories and artificial synapses, resulting from their excellent electronic and optoelectronic properties including large light absorption coefficient, fast ion migration, long carrier diffusion length, low trap density, high defect tolerance. Among MHPs, 2D halide perovskites have exotic layered structure and great environment stability as compared with 3D counterparts. Herein, recent advances of 2D MHPs for the RS memories and artificial synapses realms are comprehensively summarized and discussed, as well as the layered structure properties and the related physical mechanisms are presented. Furthermore, the current issues and developing roadmap for the next-generation 2D MHPs RS memories and artificial synapse are elucidated.

Ab Initio Study of Novel Phase-Change Heterostructures

Neuromorphic devices constitute a novel approach to computing that takes inspiration from the brain to unify the processing and storage units. Memories based on phase-change materials (PCMs) are potential candidates for such devices due to their non-volatility and excellent scalability, however their use is hindered by their conductance variability and temporal drift in resistance. Recently, it has been shown that the utilization of phase-change heterostructures consisting of nanolayers of the Sb2Te3 PCM interleaved with a transition-metal dichalcogenide, acting as a confinement material, strongly mitigates these problems. In this work, superlattice heterostructures made of TiTe2 and two prototypical PCMs, respectively GeTe and Ge2Sb2Te5 are considered. By performing ab initio molecular dynamics simulations, it is shown that it is possible to switch the PCMs without destroying the superlattice structure and without diffusion of the atoms of the PCM across the TiTe2 nanolayers. In particular, the model containing Ge2Sb2Te5 shows weak coupling between the two materials during the switching process, which, combined with the high stability of the amorphous state of Ge2Sb2Te5, makes it a very promising candidate for neuromorphic computing applications.

Solution-Processed Ultralow Voltage Organic Transistors With Sharp Switching for Adaptive Visual Perception

Neuromorphic visual systems can emulate biological retinal systems to perceive visual information under different levels of illumination, making them have considerable potential for future intelligent vehicles and vision automation. However, the complex circuits and high operating voltages of conventional artificial vision systems present great challenges for device integration and power consumption. Here, bioinspired synaptic transistors based on organic single crystal phototransistors are reported, which exhibit excitation and inhibition synaptic plasticity with time-varying. By manipulating the charge dynamics of the trapping centers of organic crystal-electret vertical stacks, organic transistors can operate below 1 V with record high on/off ratios close to 108 and sharp switching with a subthreshold swing of 59.8 mV dec-1. Moreover, the approach offers visual adaptation with highly localized modulation and over 98.2% recognition accuracy under different illumination levels. These bioinspired visual adaptation transistors offer great potential for simplifying the circuitry of artificial vision systems and will contribute to the development of machine vision applications.

Progress in Spin Logic Devices Based on Domain-Wall Motion

Spintronics, utilizing both the charge and spin of electrons, benefits from the nonvolatility, low switching energy, and collective behavior of magnetization. These properties allow the development of magnetoresistive random access memories, with magnetic tunnel junctions (MTJs) playing a central role. Various spin logic concepts are also extensively explored. Among these, spin logic devices based on the motion of magnetic domain walls (DWs) enable the implementation of compact and energy-efficient logic circuits. In these devices, DW motion within a magnetic track enables spin information processing, while MTJs at the input and output serve as electrical writing and reading elements. DW logic holds promise for simplifying logic circuit complexity by performing multiple functions within a single device. Nevertheless, the demonstration of DW logic circuits with electrical writing and reading at the nanoscale is still needed to unveil their practical application potential. In this review, we discuss material advancements for high-speed DW motion, progress in DW logic devices, groundbreaking demonstrations of current-driven DW logic, and its potential for practical applications. Additionally, we discuss alternative approaches for current-free information propagation, along with challenges and prospects for the development of DW logic.

Measuring Electrical Resistivity at the Nanoscale in Phase-Change Materials

Electrical resistivity is the key parameter in the active regions of many current nanoscale devices, from memristors to resistive random-access memory and phase-change memories. The local resistivity of the materials is engineered on the nanoscale to fit the performance requirements. Phase-change memories, for example, rely on materials whose electrical resistance increases dramatically with a change from a crystalline to an amorphous phase. Electrical characterization methods have been developed to measure the response of individual devices, but they cannot map the local resistance across the active area. Here, we propose a method based on operando electron holography to determine the local resistance within working devices. Upon switching the device, we show that electrical resistance is inhomogeneous on the scale of only a few nanometers.

Memristive Switching Mechanism in Colloidal InP/ZnSe/ZnS Quantum Dot-Based Synaptic Devices for Neuromorphic Computing

Quantum dots (QDs) have garnered a significant amount of attention as promising memristive materials owing to their size-dependent tunable bandgap, structural stability, and high level of applicability for neuromorphic computing. Despite these advantageous properties, the development of QD-based memristors has been hindered by challenges in understanding and adjusting the resistive switching (RS) behavior of QDs. Herein, we propose three types of InP/ZnSe/ZnS QD-based memristors to elucidate the RS mechanism, employing a thin poly(methyl methacrylate) layer. This approach not only allows us to identify which carriers (electron or hole) are trapped within the QD layer but also successfully demonstrates QD-based synaptic devices. Furthermore, to utilize the QD memristor as a synapse, long-term potentiation/depression (LTP/LTD) characteristics are measured, resulting in a low nonlinearity of LTP/LTD at 0.1/1. On the basis of the LTP/LTD characteristics, single-layer perceptron simulations were performed using the Extended Modified National Institute of Standards and Technology, verifying a maximum recognition rate of 91.46%.

Low power nanoscale S-FED based single ended sense amplifier applied in integrate and fire neuron circuit

Current advancements in neuromorphic computing systems are focused on decreasing power consumption and enriching computational functions. Correspondingly, state-of-the-art system-on-chip developers are encouraged to design nanoscale devices with minimum power dissipation and high-speed operation. This paper deals with designing a sense amplifier based on side-contacted field-effect diodes to reduce the power-delay product (PDP) and the noise susceptibility, as critical factors in neuron circuits. Our findings reveal that both static and dynamic power consumption of the S-FED-based sense amplifier, equal to 1.86 μW and 1.92 fW/GHz, are × 243.03 and × 332.83 lower than those of the conventional CMOS counterpart, respectively. While the sense-amplifier circuit based on CMOS technology undergoes an output voltage deviation of 170.97 mV, the proposed S-FED-based one enjoys a minor output deviation of 27.31 mV. Meanwhile, the superior HIGH-level and LOW-level noise margins of the S-FED-based sense amplifier to the CMOS counterparts (∆NMH = 70 mV and ∆NML = 120 mV), respectively, can ensure the system-level operation stability of the former one. Subsequent to the attainment of an area-efficient, low-power, and high-speed S-FED-based sense amplifier (PDP = 187.75 × 10-18 W s) as a fundamental building block, devising an innovative integrate-and-fire neuron circuit based on S-FED paves the way to realize a new generation of neuromorphic architectures. To shed light on this context, an S-FED-based integrate-and-fire neuron circuit is designed and analyzed utilizing a sense amplifier and feedback loop to enhance spiking voltage and subsequent noise immunity in addition to an about fourfold increase in firing frequency compared to CMOS-based ones.

Restricted Boltzmann Machines Implemented by Spin-Orbit Torque Magnetic Tunnel Junctions

Artificial intelligence has surged forward with the advent of generative models, which rely heavily on stochastic computing architectures enhanced by true random number generators with adjustable sampling probabilities. In this study, we develop spin-orbit torque magnetic tunnel junctions (SOT-MTJs), investigating their sigmoid-style switching probability as a function of the driving voltage. This feature proves to be ideally suited for stochastic computing algorithms such as the restricted Boltzmann machines (RBM) prevalent in pretraining processes. We exploit SOT-MTJs as both stochastic samplers and network nodes for RBMs, enabling the implementation of RBM-based neural networks to achieve recognition tasks for both handwritten and spoken digits. Moreover, we further harness the weights derived from the preceding image and speech training processes to facilitate cross-modal learning from speech to image generation. Our results clearly demonstrate that these SOT-MTJs are promising candidates for the development of hardware accelerators tailored for Boltzmann neural networks and other stochastic computing architectures.

Spacer Engineering Enables Fine-Tuned Thin Film Microstructure and Efficient Charge Transport for Ultrasensitive 2D Perovskite-Based Heterojunction Phototransistors and Optoelectronic Synapses

2D Ruddlesden-Popper phase layered perovskites (RPLPs) hold great promise for optoelectronic applications. In this study, a series of high-performance heterojunction phototransistors (HPTs) based on RPLPs with different organic spacer cations (namely butylammonium (BA+), cyclohexylammonium (CyHA+), phenethylammonium (PEA+), p-fluorophenylethylammonium (p-F-PEA+), and 2-thiophenethylammonium (2-ThEA+)) are fabricated successfully, in which high-mobility organic semiconductor 2,7-dioctyl[1]benzothieno[3,2-b]benzothiophene is adopted to form type II heterojunction channels with RPLPs. The 2-ThEA+-RPLP-based HPTs show the highest photosensitivity of 3.18 × 107 and the best detectivity of 9.00 × 1018 Jones, while the p-F-PEA+-RPLP-based ones exhibit the highest photoresponsivity of 5.51 × 106 A W-1 and external quantum efficiency of 1.32 × 109%, all of which are among the highest reported values to date. These heterojunction systems also mimicked several optically controllable fundamental characteristics of biological synapses, including excitatory postsynaptic current, paired-pulse facilitation, and the transition from short-term memory to long-term memory states. The device based on 2-ThEA+-RPLP film shows an ultra-high PPF index of 234%. Moreover, spacer engineering brought fine-tuned thin film microstructures and efficient charge transport/transfer, which contributes to the superior photodetection performance and synaptic functions of these RPLP-based HPTs. In-depth structure-property correlations between the organic spacer cations/RPLPs and thin film microstructure/device performance are systematically investigated.

Enhancing the Uniformity of a Memristor Using a Bilayer Dielectric Structure

Resistive random access memory (RRAM) holds great promise for in-memory computing, which is considered the most promising strategy for solving the von Neumann bottleneck. However, there are still significant problems in its application due to the non-uniform performance of RRAM devices. In this work, a bilayer dielectric layer memristor was designed based on the difference in the Gibbs free energy of the oxide. We fabricated Au/Ta2O5/HfO2/Ta/Pt (S3) devices with excellent uniformity. Compared with Au/HfO2/Pt (S1) and Au/Ta2O5/Pt (S2) devices, the S3 device has a low reset voltage fluctuation of 2.44%, and the resistive coefficients of variation are 13.12% and 3.84% in HRS and LRS, respectively, over 200 cycles. Otherwise, the bilayer device has better linearity and more conductance states in multi-state regulation. At the same time, we analyze the physical mechanism of the bilayer device and provide a physical model of ion migration. This work provides a new idea for designing and fabricating resistive devices with stable performance.

Reliability effects of lateral filament confinement by nano-scaling the oxide in memristive devices

Write-variability and resistance instability are major reliability concerns impeding implementation of oxide-based memristive devices in neuromorphic systems. The root cause of the reliability issues is the stochastic nature of conductive filament formation and dissolution, whose impact is particularly critical in the high resistive state (HRS). Optimizing the filament stability requires mitigating diffusive processes within the oxide, but these are unaffected by conventional electrode scaling. Here we propose a device design that laterally confines the switching oxide volume and thus the filament to 10 nm, which yields reliability improvements in our measurements and simulations. We demonstrate a 50% decrease in HRS write-variability for an oxide nano-fin device in our full factorial analysis of modulated current-voltage sweeps. Furthermore, we use ionic noise measurements to quantify the HRS filament stability against diffusive processes. The laterally confined filaments exhibit a change in the signal-to-noise ratio distribution with a shift to higher values. Our complementing kinetic Monte Carlo simulation of oxygen vacancy (re-)distribution for confined filaments shows improved noise behavior and elucidates the underlying physical mechanisms. While lateral oxide volume scaling down to filament sizes is challenging, our efforts motivate further examination and awareness of filament confinement effects in regards to reliability.

Unraveling the origins of the coexisting localized-interfacial mechanism in oxide-based memristors in CMOS-integrated synaptic device implementations

The forefront of neuromorphic research strives to develop devices with specific properties, i.e., linear and symmetrical conductance changes under external stimuli. This is paramount for neural network accuracy when emulating a biological synapse. A parallel exploration of resistive memory as a replacement for conventional computing memory ensues. In search of a holistic solution, the proposed memristive device in this work is uniquely poised to address this elusive gap as a unified memory solution. Opposite biasing operations are leveraged to achieve stable abrupt and gradual switching characteristics within a single device, addressing the demands for lower latency and energy consumption for binary switching applications, and graduality for neuromorphic computing applications. We evaluated the underlying principles of both switching modes, attributing the anomalous gradual switching to the modulation of oxygen-deficient layers formed between the active electrode and oxide switching layer. The memristive cell (1R) was integrated with 40 nm transistor technology (1T) to form a 1T-1R memory cell, demonstrating a switching speed of 50 ns with a pulse amplitude of ±2.5 V in its forward-biased mode. Applying pulse trains of 20 ns to 490 ns in the reverse-biased mode exhibited synaptic weight properties, obtaining a nonlinearity (NL) factor of <0.5 for both potentiation and depression. The devices in both modes also demonstrated an endurance of >106 cycles, and their conductance states were also stable under temperature stress at 85 °C for 104 s. With the duality of the two switching modes, our device can be used for both memory and synaptic weight-storing applications.

Analytical modelling of the transport in analog filamentary conductive-metal-oxide/HfOx ReRAM devices

The recent co-optimization of memristive technologies and programming algorithms enabled neural networks training with in-memory computing systems. In this context, novel analog filamentary conductive-metal-oxide (CMO)/HfOx redox-based resistive switching memory (ReRAM) represents a key technology. Despite device performance enhancements reported in literature, the underlying mechanism behind resistive switching is not fully understood. This work presents the first physics-based analytical model of the current transport and of the resistive switching in these devices. As a case study, analog TaOx/HfOx ReRAM devices are considered. The current transport is explained by a trap-to-trap tunneling process, and the resistive switching by a modulation of the defect density within the sub-band of the TaOx that behaves as electric field and temperature confinement layer. The local temperature and electric field distributions are derived from the solution of the electric and heat transport equations in a 3D finite element ReRAM model. The intermediate resistive states are described as a gradual modulation of the TaOx defect density, which results in a variation of its electrical conductivity. The drift-dynamics of ions during the resistive switching is analytically described, allowing the estimation of defect migration energies in the TaOx layer. Moreover, the role of the electro-thermal properties of the CMO layer is unveiled. The proposed analytical model accurately describes the experimental switching characteristic of analog TaOx/HfOx ReRAM devices, increasing the physical understanding and providing the equations necessary for circuit simulations incorporating this technology.

Versatile Nanoscale Three-Terminal Memristive Switch Enabled by Gating

A three-terminal memristor with an ultrasmall footprint of only 0.07 μm2 and critical dimensions of 70 nm × 10 nm × 6 nm is introduced. The device's feature is the presence of a gate contact, which enables two operation modes: either tuning the set voltage or directly inducing a resistance change. In I-V mode, we demonstrate that by changing the gate voltages between ±1 V one can shift the set voltage by 69%. In pulsing mode, we show that resistance change can be triggered by a gate pulse. Furthermore, we tested the device endurance under a 1 kHz operation. In an experiment with 2.6 million voltage pulses, we found two distinct resistance states. The device response to a pseudorandom bit sequence displays an open eye diagram and a success ratio of 97%. Our results suggest that this device concept is a promising candidate for a variety of applications ranging from Internet-of-Things to neuromorphic computing.

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

Oxovanadium electronics for in-memory, neuromorphic, and quantum computing applications

Vanadium is a critical raw material. In the nearby future, it may, however, become one of the key elements of computer devices based on two-dimensional arrays of spin qubits for quantum information processing or charge- and resistance-based data memory cells for non-volatile in-memory and neuromorphic computing. The research and development (R&D) of vanadium-containing electronic materials and methods for their responsible fabrication underpins the transition to innovative hybrid semiconductors for energy- and resource-efficient memory and information processing technologies. The combination of standard and emerging solid-state semiconductors with stimuli-responsive oxo complexes of vanadium(IV,V) is envisioned to result in electronics with a new room-temperature device nanophysics, and the ability to modulate and control it at the sub-nanometer level. The development of exponential (Boolean) logics based on the oxovanadium-comprising circuitry and crossbar arrays of individual memristive cells for in-memory computing, the implementation of basic synaptic functions via dynamic electrical pulses for neuromorphic computing, and the readout and control of spin networks and interfaces for quantum computing are strategically important future areas of molecular chemistry and applied physics of vanadium.

CMOS-Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin

The development of data-intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory-centric paradigm. Within this context, ternary content-addressable memory (TCAM) can become an essential platform for high-speed in-memory matching applications of large data vectors. Compared to traditional static random-access memory (SRAM) designs, TCAM technology using non-volatile resistive memories (RRAMs) in two-transistor-two-resistor (2T2R) configurations presents a cost-efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory-based TCAMs for large-scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive-bridge memories (CBRAMs) integrated with existing complementary metal-oxide-semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity-enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM-based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.

1-Selector 1-Memristor Configuration with Multifunctional a-IGZO Memristive Devices Fabricated at Room Temperature

Serving as neuromorphic hardware accelerators, memristors play a crucial role in large-scale neuromorphic computing. Herein, two-terminal memristors utilizing amorphous indium-gallium-zinc oxide (a-IGZO) are fabricated through room-temperature sputtering. The electrical characteristics of these memristors are effectively modulated by varying the oxygen flow during the deposition process. The optimized a-IGZO memristor, fabricated under 3 sccm oxygen flow, presents a 5 × 103 ratio between its high- and low-resistance states, which can be maintained over 1 × 104 s with minimal degradation. Meanwhile, desirable properties such as electroforming-free and self-compliance, crucial for low-energy consumption, are also obtained in the a-IGZO memristor. Moreover, analog conductance switching is observed, demonstrating an interface-type behavior, as evidenced by its device-size-dependent performance. The coexistence of negative differential resistance with analog switching is attributed to the migration of oxygen vacancies and the trapping/detrapping of charges. Furthermore, the device demonstrates optical storage capabilities by exploiting the optical properties of a-IGZO, which can stably operate for up to 50 sweep cycles. Various synaptic functions have been demonstrated, including paired-pulse facilitation and spike-timing-dependent plasticity. These functionalities contribute to a simulated recognition accuracy of 90% for handwritten digits. Importantly, a one-selector one-memristor (1S1M) architecture is successfully constructed at room temperature by integrating a-IGZO memristor on a TaOx-based selector. This architecture exhibits a 107 on/off ratio, demonstrating its potential to suppress sneak currents among adjacent units in a memristor crossbar.

Multiphase Reset Induced Reliable Dual-Mode Resistance Switching of the Ta/HfO2/RuO2 Memristor

Higher functionality should be achieved within the device-level switching characteristics to secure the operational possibility of mixed-signal data processing within a memristive crossbar array. This work investigated electroforming-free Ta/HfO2/RuO2 resistive switching devices for digital- and analog-type applications through various structural and electrical analyses. The multiphase reset behavior, induced by the conducting filament modulation and oxygen vacancy generation (annihilation) in the HfO2 layer by interacting with the Ta (RuO2) electrode, was utilized for the switching mode change. Therefore, a single device can manifest stable binary switching between low and high resistance states for the digital mode and the precise 8-bit conductance modulation (256 resistance values) via an optimized pulse application for the analog mode. An in-depth analysis of the operation in different modes and comparing memristors with different electrode structures validate the proposed mechanism. The Ta/HfO2/RuO2 resistive switching device is feasible for a mixed-signal processable memristive array.

Ferroelectric 2D SnS2 Analog Synaptic FET

In this study, the development and characterization of 2D ferroelectric field-effect transistor (2D FeFET) devices are presented, utilizing nanoscale ferroelectric HfZrO2 (HZO) and 2D semiconductors. The fabricated device demonstrated multi-level data storage capabilities. It successfully emulated essential biological characteristics, including excitatory/inhibitory postsynaptic currents (EPSC/IPSC), Pair-Pulse Facilitation (PPF), and Spike-Timing Dependent Plasticity (STDP). Extensive endurance tests ensured robust stability (107 switching cycles, 105 s (extrapolated to 10 years)), excellent linearity, and high Gmax/Gmin ratio (>105), all of which are essential for realizing multi-level data states (>7-bit operation). Beyond mimicking synaptic functionalities, the device achieved a pattern recognition accuracy of ≈94% on the Modified National Institute of Standards and Technology (MNIST) handwritten dataset when incorporated into a neural network, demonstrating its potential as an effective component in neuromorphic systems. The successful implementation of the 2D FeFET device paves the way for the development of high-efficiency, ultralow-power neuromorphic hardware which is in sub-femtojoule (48 aJ/spike) and fast response (1 µs), which is 104 folds faster than human synapse (≈10 ms). The results of the research underline the potential of nanoscale ferroelectric and 2D materials in building the next generation of artificial intelligence technologies.

Silicon-Compatible Ferroelectric Tunnel Junctions with a SiO2/Hf0.5Zr0.5O2 Composite Barrier as Low-Voltage and Ultra-High-Speed Memristors

The big data era requires ultrafast, low-power, and silicon-compatible materials and devices for information storage and processing. Here, ferroelectric tunnel junctions (FTJs) based on SiO2/Hf0.5Zr0.5O2 composite barrier and both conducting electrodes are designed and fabricated on Si substrates. The FTJ achieves the fastest write speed of 500 ps under 5 V (2 orders of magnitude faster than reported silicon-compatible FTJs) or 10 ns speed at a low voltage of 1.5 V (the lowest voltage among FTJs at similar speeds), low write current density of 1.3 × 104 A cm-2, 8 discrete states, good retention > 105 s at 85 °C, and endurance > 107. In addition, it provides a large read current (88 A cm-2) at 0.1 V, 2 orders of magnitude larger than reported FTJs. Interestingly, in FTJ-based synapses, gradually tunable conductance states (128 states) with high linearity (<1) are obtained by 10 ns pulses of <1.2 V, and a high accuracy of 91.8% in recognizing fashion product images is achieved by online neural network simulations. These results highlight that silicon-compatible HfO2-based FTJs are promising for high-performance nonvolatile memories and electrical synapses.

Programmable Threshold Logic Implementations in a Memristor Crossbar Array

In this study, we demonstrate the implementation of programmable threshold logics using a 32 × 32 memristor crossbar array. Thanks to forming-free characteristics obtained by the annealing process, its accurate programming characteristics are presented by a 256-level grayscale image. By simultaneous subtraction between weighted sum and threshold values with a differential pair in an opposite way, 3-input and 4-input Boolean logics are implemented in the crossbar without additional reference bias. Also, we verify a full-adder circuit and analyze its fidelity, depending on the device programming accuracy. Lastly, we successfully implement a 4-bit ripple carry adder in the crossbar and achieve reliable operations by read-based logic operations. Compared to stateful logic driven by device switching, a 4-bit ripple carry adder on a memristor crossbar array can perform more reliably in fewer steps thanks to its read-based parallel logic operation.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Realization of sextuple polarization states and interstate switching in antiferroelectric CuInP2S6

Realization of higher-order multistates with mutual interstate switching in ferroelectric materials is a perpetual drive for high-density storage devices and beyond-Moore technologies. Here we demonstrate experimentally that antiferroelectric van der Waals CuInP2S6 films can be controllably stabilized into double, quadruple, and sextuple polarization states, and a system harboring polarization order of six is also reversibly tunable into order of four or two. Furthermore, for a given polarization order, mutual interstate switching can be achieved via moderate electric field modulation. First-principles studies of CuInP2S6 multilayers help to reveal that the double, quadruple, and sextuple states are attributable to the existence of respective single, double, and triple ferroelectric domains with antiferroelectric interdomain coupling and Cu ion migration. These findings offer appealing platforms for developing multistate ferroelectric devices, while the underlining mechanism is transformative to other non-volatile material systems.

Magnon-Assisted Magnetization Reversal of Ni81Fe19 Nanostripes on Y3Fe5O12 with Different Interfaces

Magnetic bit writing by short-wave magnons without conversion to the electrical domain is expected to be a game-changer for in-memory computing architectures. Recently, the reversal of nanomagnets by propagating magnons was demonstrated. However, experiments have not yet explored different wavelengths and the nonlinear excitation regime of magnons required for computational tasks. We report on the magnetization reversal of individual 20 nm thick Ni81Fe19 (Py) nanostripes integrated onto 113 nm thick yttrium iron garnet (YIG). We suppress direct interlayer exchange coupling by an intermediate layer, such as Cu and SiO2. By exciting magnons in YIG with wavelengths λ down to 148 nm we observe the reversal of the integrated ferromagnets in a small external field of 14 mT. Magnons with a small wavelength of λ = 195 nm, i.e., twice the width of the Py nanostripes, induced the reversal at a spin-precessional power of only about 1 nW after propagating over 15 μm in YIG. Such small power value has not been reported so far. Considerations based on dynamic dipolar coupling explain the observed wavelength dependence of the magnon-induced reversal efficiency. For an increased power, the stripes reversed in an external field of only about 1 mT. Our findings are important for the practical implementation of nonvolatile storage of broadband magnon signals in YIG by means of bistable nanomagnets without the need of an appreciable global magnetic field.

Multi-channel broadband nonvolatile programmable modal switch

Mode-division multiplexing (MDM) in chip-scale photonics is paramount to sustain data capacity growth and reduce power consumption. However, its scalability hinges on developing efficient and dynamic modal switches. Existing active modal switches suffer from substantial static power consumption, large footprints, and narrow bandwidth. Here, we present, for the first time, to the best of our knowledge, a novel multiport, broadband, non-volatile, and programmable modal switch designed for on-chip MDM systems. Our design leverages the unique properties of integrating nanoscale phase-change materials (PCM) within a silicon photonic architecture. This enables independent manipulation of spatial modes, allowing for dynamic, non-volatile, and selective routing to six distinct output ports. Crucially, our switch outperforms current dynamic modal switches by offering non-volatile, energy-efficient multiport functionality and excels in performance metrics. Our switch exhibits exceptional broadband operating bandwidth exceeding 70 nm, with low loss (< 1 dB), and a high extinction ratio (> 10 dB). Our framework provides a step forward in chip-scale MDM, paving the way for future green and scalable data centers and high-performance computers.

Ferroelectric compute-in-memory annealer for combinatorial optimization problems

Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications. Various digital annealers, dynamical Ising machines, and quantum/photonic systems have been developed for solving COPs, but they still suffer from the memory access issue, scalability, restricted applicability to certain types of COPs, and VLSI-incompatibility, respectively. Here we report a ferroelectric field effect transistor (FeFET) based compute-in-memory (CiM) annealer for solving larger-scale COPs efficiently. Our CiM annealer converts COPs into quadratic unconstrained binary optimization (QUBO) formulations, and uniquely accelerates in-situ the core vector-matrix-vector (VMV) multiplication operations of QUBO formulations in a single step. Specifically, the three-terminal FeFET structure allows for lossless compression of the stored QUBO matrix, achieving a remarkably 75% chip size saving when solving Max-Cut problems. A multi-epoch simulated annealing (MESA) algorithm is proposed for efficient annealing, achieving up to 27% better solution and ~ 2X speedup than conventional simulated annealing. Experimental validation is performed using the first integrated FeFET chip on 28nm HKMG CMOS technology, indicating great promise of FeFET CiM array in solving general COPs.

A von-Neumann-like photonic processor and its application in studying quantum signature of chaos

Photonic quantum computation plays an important role and offers unique advantages. Two decades after the milestone work of Knill-Laflamme-Milburn, various architectures of photonic processors have been proposed, and quantum advantage over classical computers has also been demonstrated. It is now the opportune time to apply this technology to real-world applications. However, at current technology level, this aim is restricted by either programmability in bulk optics or loss in integrated optics for the existing architectures of processors, for which the resource cost is also a problem. Here we present a von-Neumann-like architecture based on temporal-mode encoding and looped structure on table, which is capable of multimode-universal programmability, resource-efficiency, phase-stability and software-scalability. In order to illustrate these merits, we execute two different programs with varying resource requirements on the same processor, to investigate quantum signature of chaos from two aspects: the signature behaviors exhibited in phase space (13 modes), and the Fermi golden rule which has not been experimentally studied in quantitative way before (26 modes). The maximal program contains an optical interferometer network with 1694 freely-adjustable phases. Considering current state-of-the-art, our architecture stands as the most promising candidate for real-world applications.

Binarized neural network of diode array with high concordance to vector-matrix multiplication

In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector-matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p+-n-p-n+ device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 108). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN.

Hardware implementation of memristor-based artificial neural networks

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Multistate Compound Magnetic Tunnel Junction Synapses for Digital Recognition

The quest to mimic the multistate synapses for bioinspired computing has triggered nascent research that leverages the well-established magnetic tunnel junction (MTJ) technology. Early works on the spin transfer torque MTJ-based artificial neural network (ANN) are susceptible to poor thermal reliability, high latency, and high critical current densities. Meanwhile, work on spin-orbit torque (SOT) MTJ-based ANN mainly utilized domain wall motion, which yields negligibly small readout signals differentiating consecutive states and has designs that are incompatible with technological scale-up. Here, we propose a multistate device concept built upon a compound MTJ consisting of multiple SOT-MTJs (number of MTJs, n = 1-4) on a shared write channel, mimicking the spin-based ANN. The n + 1 resistance states representing varying synaptic weights can be tuned by varying the voltage pulses (±1.5-1.8 V), pulse duration (100-300 ns), and applied in-plane fields (5.5-10.5 mT). A large TMR difference of more than 13.6% is observed between two consecutive states for the 4-cell compound MTJ, a 4-fold improvement from reported state-of-the-art spin-based synaptic devices. The ANN built upon the compound MTJ shows high learning accuracy for digital recognition tasks with incremental states and retraining, achieving test accuracy as high as 95.75% in the 4-cell compound MTJ. These results provide an industry-compatible platform to integrate these multistate SOT-MTJ synapses directly into neuromorphic architecture for in-memory and unconventional computing applications.

Electrochemical random-access memory: recent advances in materials, devices, and systems towards neuromorphic computing

Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems.

Thermal Compact Modeling and Resistive Switching Analysis in Titanium Oxide-Based Memristors

Resistive switching devices based on the Au/Ti/TiO2/Au stack were developed. In addition to standard electrical characterization by means of I-V curves, scanning thermal microscopy was employed to localize the hot spots on the top device surface (linked to conductive nanofilaments, CNFs) and perform in-operando tracking of temperature in such spots. In this way, electrical and thermal responses can be simultaneously recorded and related to each other. In a complementary way, a model for device simulation (based on COMSOL Multiphysics) was implemented in order to link the measured temperature to simulated device temperature maps. The data obtained were employed to calculate the thermal resistance to be used in compact models, such as the Stanford model, for circuit simulation. The thermal resistance extraction technique presented in this work is based on electrical and thermal measurements instead of being indirectly supported by a single fitting of the electrical response (using just I-V curves), as usual. Besides, the set and reset voltages were calculated from the complete I-V curve resistive switching series through different automatic numerical methods to assess the device variability. The series resistance was also obtained from experimental measurements, whose value is also incorporated into a compact model enhanced version.

Hierarchical processing enabled by 2D ferroelectric semiconductor transistor for low-power and high-efficiency AI vision system

The growth of data and Internet of Things challenges traditional hardware, which encounters efficiency and power issues owing to separate functional units for sensors, memory, and computation. In this study, we designed an α-phase indium selenide (α-In2Se3) transistor, which is a two-dimensional ferroelectric semiconductor as the channel material, to create artificial optic-neural and electro-neural synapses, enabling cutting-edge processing-in-sensor (PIS) and computing-in-memory (CIM) functionalities. As an optic-neural synapse for low-level sensory processing, the α-In2Se3 transistor exhibits a high photoresponsivity (2855 A/W) and detectivity (2.91 × 1014 Jones), facilitating efficient feature extraction. For high-level processing tasks as an electro-neural synapse, it offers a fast program/erase speed of 40 ns/50 µs and ultralow energy consumption of 0.37 aJ/spike. An AI vision system using α-In2Se3 transistors has been demonstrated. It achieved an impressive recognition accuracy of 92.63% within 12 epochs owing to the synergistic combination of the PIS and CIM functionalities. This study demonstrates the potential of the α-In2Se3 transistor in future vision hardware, enhancing processing, power efficiency, and AI applications.

Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials

The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.

An in-sensor humidity computing system for contactless human-computer interaction

Being capable of processing large amounts of redundant data and decreasing power consumption, in-sensor computing approaches play significant roles in neuromorphic computing and are attracting increasing interest in perceptual information processing. Herein, we proposed a high performance humidity-sensitive memristor based on a Ti/graphene oxide (GO)/HfOx/Pt structure and verified its potential for application in remote health management and contactless human-machine interfaces. Since GO possesses abundant hydrophilic groups (carbonyl, epoxide, and hydroxyl), the memristor shows a high humidity sensitivity, fast response, and wide response range. By utilizing the proton-modulated redox reaction, humidity exposure to the memristor induces a dynamic change in the switching between high and low resistance states, ensuring essential synaptic learning functions, such as paired-pulse facilitation, spike number-dependent plasticity, and spike amplitude-dependent plasticity. More importantly, based on the humidity-induced salient features originating from the abundant hydrophilic functional groups in GO, we have implemented a noncontact human-machine interface utilizing the respiratory mode in humans, demonstrating the potential of promoting health monitoring applications and effectively blocking virus transmission. In addition, the high recognition accuracy of contactless handwriting in a 5 × 5 array artificial neural network was successfully achieved, which is attributed to the excellent emulated synaptic behaviors. This study provides a feasible method to develop an excellent humidity-sensitive memristor for constructing efficient in-sensor computing for application in health management and contactless human-computer interaction.

3D simulation of conductive nanofilaments in multilayer h-BN memristors via a circuit breaker approach

A 3D simulation of conductive nanofilaments (CNFs) in multilayer hexagonal-BN memristors is performed. To do so, a simulation tool based on circuit breakers is developed including for the first time a 3D resistive network. The circuit breakers employed can be modeled with two, three and four resistance states; in addition, a series resistance and a module to account for quantum effects, by means of the quantum point contact model, are also included. Finally, to describe real dielectric situations, regions with a high defect density are modeled with a great variety of geometrical shapes to consider their influence in the resistive switching (RS) process. The simulator has been tuned with measurements of h-BN memristive devices, fabricated with chemical-vapour-deposition grown h-BN layers, which were electrically and physically characterized. We show the formation of CNFs that produce filamentary charge conduction in our devices. Moreover, the simulation tool is employed to describe partial filament rupture in reset processes and show the low dependence of the set voltage on the device area, which is seen experimentally.