2D fin field-effect transistors integrated with epitaxial high-k gate oxide

High-Yield Production of High-κ/Metal Gate Nanopattern Array for 2D Devices via Oxidation-Assisted Etching Approach

2D materials with atomically thin nature are promising to develop scaled transistors and enable the extreme miniaturization of electronic components. However, batch manufacturing of top-gate 2D transistors remains a challenge since gate dielectrics or gate electrodes transferred from 2D material easily peel away as gate pitch decreases to the nanometer scale during lift-off processes. In this study, an oxidation-assisted etching technique is developed for batch manufacturing of nanopatterned high-κ/metal gate (HKMG) stacks on 2D materials. This strategy produces nano-pitch self-oxidized Al2O3/Al patterns with a resolution of 150 nm on 2D channel material, including graphene, MoS2, and WS2 without introducing any additional damage. Through a gate-first technology in which the Al2O3/Al gate stacks are used as a mask for the formation of source and drain, a short-channel HKMG MoS2 transistor with a nearly ideal subthreshold swing (SS) of 61 mV dec-1, and HKMG graphene transistor with a cut-off frequency of 150 GHz are achieved. Moreover, both graphene and MoS2 HKMG transistor arrays exhibit high uniformity. The study may bring the potential for the massive production of large-scale integrated circuits using 2D materials.

Simulations of Anisotropic Monolayer GaSCl for p-Type Sub-10 nm High-Performance and Low-Power FETs

Two-dimensional materials have been extensively studied in field-effect transistors (FETs). However, the performance of p-type FETs has lagged behind that of n-type, which limits the development of complementary logical circuits. Here, we investigate the electronic properties and transport performance of anisotropic monolayer GaSCl for p-type FETs through first-principles calculations. The anisotropic electronic properties of monolayer GaSCl result in excellent device performance. The p-type GaSCl FETs with 10 nm channel length have an on-state current of 2351 μA/μm for high-performance (HP) devices along the y direction and an on-state current of 992 μA/μm with an on/off ratio exceeding 107 for low-power (LP) applications along the x direction. In addition, the delay-time (τ) and power dissipation product of GaSCl FETs can fully meet the International Technology Roadmap for Semiconductors standards for HP and LP applications. Our work illustrates that monolayer GaSCl is a competitive p-type channel for next-generation devices.

Even-integer quantum Hall effect in an oxide caused by a hidden Rashba effect

In the presence of a high magnetic field, quantum Hall systems usually host both even- and odd-integer quantized states because of lifted band degeneracies. Selective control of these quantized states is challenging but essential to understand the exotic ground states and manipulate the spin textures. Here we demonstrate the quantum Hall effect in Bi2O2Se thin films. In magnetic fields as high as 50 T, we observe only even-integer quantum Hall states, but there is no sign of odd-integer states. However, when reducing the thickness of the epitaxial Bi2O2Se film to one unit cell, we observe both odd- and even-integer states in this Janus (asymmetric) film grown on SrTiO3. By means of a Rashba bilayer model based on the ab initio band structures of Bi2O2Se thin films, we can ascribe the only even-integer states in thicker films to the hidden Rasbha effect, where the local inversion-symmetry breaking in two sectors of the [Bi2O2]2+ layer yields opposite Rashba spin polarizations, which compensate with each other. In the one-unit-cell Bi2O2Se film grown on SrTiO3, the asymmetry introduced by the top surface and bottom interface induces a net polar field. The resulting global Rashba effect lifts the band degeneracies present in the symmetric case of thicker films.

Epitaxial Integration of Transferable High-κ Dielectric and 2D Semiconductor

The synthesis of high-dielectric-constant (high-κ) dielectric materials and their integration with channel materials have been the key challenges in the state-of-the-art transistor architecture, as they can provide strong gate control and low operating voltage. For next-generation electronics, high-mobility two-dimensional (2D) layered semiconductors with dangling-bond-free surfaces and an atomic-thick thickness are being explored as channel materials to achieve shorter channel lengths and less interfacial scattering. Nowadays, the integration of high-κ dielectrics with high-mobility 2D semiconductors mainly relies on atomic layer deposition or transfer stacking, which may cause several undesirable problems, such as channel damage and interface traps. Here, we demonstrate the integration of high-mobility 2D semiconducting Bi2O2Se with transferable high-κ SrTiO3 as a 2D field-effect transistor by direct epitaxial growth. Remarkably, such 2D heterostructures can be efficiently transferred from the water-soluble Sr3Al2O6 sacrificial layer onto arbitrary substrates. The as-fabricated 2D Bi2O2Se/SrTiO3 transistors exhibit an on/off ratio over 104 and a subthreshold swing down to 90 mV/dec. Furthermore, the 2D Bi2O2Se/SrTiO3 heterostructures can be easily transferred onto flexible polyethylene terephthalate (PET) substrates, and the as-fabricated transistors exhibit good potential in flexible electronics. Our study opens up a new avenue for the integration of high-κ dielectrics with high-mobility 2D semiconductors and paves the way for the exploration of multifunctional electronic devices.

Mixed-Dimensional Integration of 3D-on-2D Heterostructures for Advanced Electronics

Two-dimensional (2D) materials have garnered significant attention due to their exceptional properties requisite for next-generation electronics, including ultrahigh carrier mobility, superior mechanical flexibility, and unusual optical characteristics. Despite their great potential, one of the major technical difficulties toward lab-to-fab transition exists in the seamless integration of 2D materials with classic material systems, typically composed of three-dimensional (3D) materials. Owing to the self-passivated nature of 2D surfaces, it is particularly challenging to achieve well-defined interfaces when forming 3D materials on 2D materials (3D-on-2D) heterostructures. Here, we comprehensively review recent progress in 3D-on-2D incorporation strategies, ranging from direct-growth- to layer-transfer-based approaches and from non-epitaxial to epitaxial integration methods. Their technological advances and obstacles are rigorously discussed to explore optimal, yet viable, integration strategies of 3D-on-2D heterostructures. We conclude with an outlook on mixed-dimensional integration processes, identifying key challenges in state-of-the-art technology and suggesting potential opportunities for future innovation.

Programmable Interfacial Band Configuration in WS2/Bi2O2Se Heterojunctions

van der Waals heterojunctions based on transition-metal dichalcogenides (TMDs) offer advanced strategies for manipulating light-emitting and light-harvesting behaviors. A crucial factor determining the light-material interaction is in the band alignment at the heterojunction interface, particularly the distinctions between type-I and type-II alignments. However, altering the band alignment from one type to another without changing the constituent materials is exceptionally difficult. Here, utilizing Bi2O2Se with a thickness-dependent band gap as a bottom layer, we present an innovative strategy for engineering interfacial band configurations in WS2/Bi2O2Se heterojunctions. In particular, we achieve tuning of the band alignment from type-I (Bi2O2Se straddling WS2) to type-II and finally to type-I (WS2 straddling Bi2O2Se) by increasing the thickness of the Bi2O2Se bottom layer from monolayer to multilayer. We verified this band architecture conversion using steady-state and transient spectroscopy as well as density functional theory calculations. Using this material combination, we further design a sophisticated band architecture incorporating both type-I (WS2 straddles Bi2O2Se, fluorescence-quenched) and type-I (Bi2SeO5 straddles WS2, fluorescence-recovered) alignments in one sample through focused laser beam (FLB). By programming the FLB trajectory, we achieve a predesigned localized fluorescence micropattern on WS2 without changing its intrinsic atomic structure. This effective band architecture design strategy represents a significant leap forward in harnessing the potential of TMD heterojunctions for multifunctional photonic applications.

Inner Doping of Carbon Nanotubes with Perovskites for Ultralow Power Transistors

Semiconducting carbon nanotubes (CNTs) are considered as the most promising channel material to construct ultrascaled field-effect transistors, but the perfect sp2 C─C structure makes stable doping difficult, which limits the electrical designability of CNT devices. Here, an inner doping method is developed by filling CNTs with 1D halide perovskites to form a coaxial heterojunction, which enables a stable n-type field-effect transistor for constructing complementary metal-oxide-semiconductor electronics. Most importantly, a quasi-broken-gap (BG) heterojunction tunnel field-effect transistor (TFET) is first demonstrated based on an individual partial-filling CsPbBr3/CNT and exhibits a subthreshold swing of 35 mV dec-1 with a high on-state current of up to 4.9 µA per tube and an on/off current ratio of up to 105 at room temperature. The quasi-BG TFET based on the CsPbBr3/CNT coaxial heterojunction paves the way for constructing high-performance and ultralow power consumption integrated circuits.

Strong Covalent Coupling in Vertically Layered SnSe2/PTAA Heterojunctions Enabled High Performance Inorganic-Organic Hybrid Photodetectors

Controllable large-scale integration of two-dimensional (2D) materials with organic semiconductors and the realization of strong coupling between them still remain challenging. Herein, we demonstrate a wafer-scale, vertically layered SnSe2/PTAA heterojunction array with high light-trapping ability via a low-temperature molecular beam epitaxy method and a facile spin-coating process. Conductive probe atomic force microscopy (CP-AFM) measurements reveal strong rectification and photoresponse behavior in the individual SnSe2 nanosheet/PTAA heterojunction. Theoretical analysis demonstrates that vertically layered SnSe2/PTAA heterojunctions exhibit stronger C-Se covalent coupling than that of the conventional tiled type, which could facilitate more efficient charge transfer. Benefiting from these advantages, the SnSe2/PTAA heterojunction photodetectors with an optimized PTAA concentration show high performance, including a responsivity of 41.02 A/W, an external quantum efficiency of 1.31 × 104%, and high uniformity. The proposed approach for constructing large-scale 2D inorganic-organic heterostructures represents an effective route to fabricate high-performance broadband photodetectors for integrated optoelectronic systems.

High-κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low-Power Steep-Switching Computing Devices

Herein, a high-quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm-2 eV-1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10-3 A cm-2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec-1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field-effect transistor is fabricated that exhibits n-type steep-switching characteristics with a SS value of 3.43 mV dec-1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.

Tailoring Broadband Nonlinear Optical Characteristics and Ultrafast Photocarrier Dynamics of Bi2O2S Nanosheets by Defect Engineering

Low-dimensional bismuth oxychalcogenides have shown promising potential in optoelectronics due to their high stability, photoresponse, and carrier mobility. However, the relevant studies on deep understanding for Bi2O2S is quite limited. Here, comprehensive experimental and computational investigations are conducted in the regulated band structure, nonlinear optical (NLO) characteristics, and carrier dynamics of Bi2O2S nanosheets via defect engineering, taking O vacancy (OV) and substitutional Se doping as examples. As the OV continuously increased to ≈35%, the optical bandgaps progressively narrow from ≈1.21 to ≈0.81 eV and NLO wavelengths are extended to near-infrared regions with enhanced saturable absorption. Simultaneously, the relaxation processes are effectively accelerated from tens of picoseconds to several picoseconds, as the generated defect energy levels can serve as both additional absorption cross-sections and fast relaxation channels supported by theoretical calculations. Furthermore, substitutional Se doping in Bi2O2S nanosheets also modulate their optical properties with the similar trends. As a proof-of-concept, passively mode-locked pulsed lasers in the ≈1.0 µm based on the defect-rich samples (≈35% OV and ≈50% Se-doping) exhibit excellent performance. This work deepens the insight of defect functions on optical properties of Bi2O2S nanosheets and provides new avenues for designing advanced photonic devices based on low-dimensional bismuth oxychalcogenides.

Nonvolatile Modulation of Bi2O2Se/Pb(Zr,Ti)O3 Heteroepitaxy

The pursuit of high-performance electronic devices has driven the research focus toward 2D semiconductors with high electron mobility and suitable band gaps. Previous studies have demonstrated that quasi-2D Bi2O2Se (BOSe) has remarkable physical properties and is a promising candidate for further exploration. Building upon this foundation, the present work introduces a novel concept for achieving nonvolatile and reversible control of BOSe's electronic properties. The approach involves the epitaxial integration of a ferroelectric PbZr0.2Ti0.8O3 (PZT) layer to modify BOSe's band alignment. Within the BOSe/PZT heteroepitaxy, through two opposite ferroelectric polarization states of the PZT layer, we can tune the Fermi level in the BOSe layer. Consequently, this controlled modulation of the electronic structure provides a pathway to manipulate the electrical properties of the BOSe layer and the corresponding devices.

Dimension-Confined Growth of a Crack-Free PbS Microplate Array for Infrared Image Sensing

Epitaxy of semiconductors is a necessary step toward the development of electronic devices such as lasers, detectors, transistors, and solar cells. However, the lattice ordering of semiconductor functional films is inevitably disrupted by excessive concentrated stress due to the mismatch of the thermal expansion coefficient. Herein, combined with the first-principles calculation, we find that a rigid film/substrate bilayer heterostructure with a large thermal expansion mismatch upon cooling to room temperature from growth is free of surface cracks when the rigid film exhibits a dimension smaller than the critical condition for the breaking energy. The principle has been verified in a PbS/SrTiO3 bilayer system that is crack free on PbS single-crystalline microplate arrays through the designing of a dimension-confined growth (DCG) method. Interestingly, this crack-free, large-scale PbS microplate array exhibits exceptional uniformity in morphology, dimensions, thickness, and photodetection properties, enabling a broad-band infrared image sensing. This work provides a new perspective to design materials and arrays that demand smooth and continuous surfaces, which are not limited only to semiconductor electronics but also include mechanical structures, optical materials, biomedical materials, and others.

Integrated 2D multi-fin field-effect transistors

Vertical semiconducting fins integrated with high-κ oxide dielectrics have been at the centre of the key device architecture that has promoted advanced transistor scaling during the last decades. Single-fin channels based on two-dimensional (2D) semiconductors are expected to offer unique advantages in achieving sub-1 nm fin-width and atomically flat interfaces, resulting in superior performance and potentially high-density integration. However, multi-fin structures integrated with high-κ dielectrics are commonly required to achieve higher electrical performance and integration density. Here we report a ledge-guided epitaxy strategy for growing high-density, mono-oriented 2D Bi2O2Se fin arrays that can be used to fabricate integrated 2D multi-fin field-effect transistors. Aligned substrate steps enabled precise control of both nucleation sites and orientation of 2D fin arrays. Multi-channel 2D fin field-effect transistors based on epitaxially integrated 2D Bi2O2Se/Bi2SeO5 fin-oxide heterostructures were fabricated, exhibiting an on/off current ratio greater than 106, high on-state current, low off-state current, and high durability. 2D multi-fin channel arrays integrated with high-κ oxide dielectrics offer a strategy to improve the device performance and integration density in ultrascaled 2D electronics.

Controllable Synthesis of Transferable Ultrathin Bi2Ge(Si)O5 Dielectric Alloys with Composition-Tunable High-κ Properties

Two-dimensional (2D) alloys hold great promise to serve as important components of 2D transistors, since their properties allow continuous regulation by varying their compositions. However, previous studies are mainly limited to the metallic/semiconducting ones as contact/channel materials, but very few are related to the insulating dielectrics. Here, we use a facile one-step chemical vapor deposition (CVD) method to synthesize ultrathin Bi2SixGe1-xO5 dielectric alloys, whose composition is tunable over the full range of x just by changing the relative ratios of the GeO2/SiO2 precursors. Moreover, their dielectric properties are highly composition-tunable, showing a record-high dielectric constant of >40 among CVD-grown 2D insulators. The vertically grown nature of Bi2GeO5 and Bi2SixGe1-xO5 enables polymer-free transfer and subsequent clean van der Waals integration as the high-κ encapsulation layer to enhance the mobility of 2D semiconductors. Besides, the MoS2 transistors using Bi2SixGe1-xO5 alloy as gate dielectrics exhibit a large Ion/Ioff (>108), ideal subthreshold swing of ∼61 mV/decade, and a small gate hysteresis (∼5 mV). Our work not only gives very few examples on controlled CVD growth of insulating dielectric alloys but also expands the family of 2D single-crystalline high-κ dielectrics.

The growth mechanism of PtS2 single crystal

PtS2, a member of the group 10 transition metal dichalcogenides (TMDs), has received extensive attention because of its excellent electrical properties and air stability. However, there are few reports on the preparation of single-crystal PtS2 in the literature, and the growth mechanism of single crystal PtS2 is not well elucidated. In this work, we proposed a method of preparation that combines magnetron sputtering and chemical vapor transport to obtain monocrystalline PtS2 on a SiO2/Si substrate. By controlling the growth temperature and time, we have synthesized a single crystalline PtS2 of hexagonal shape and size of 1-2 μm on a silicon substrate. Combining the molecular dynamics simulation, the growth mechanism of single crystal PtS2 was investigated both experimentally and theoretically. The synthesis method has a short production cycle and low cost, which opens the door for the fabrication of other TMDs single crystals.

Integration of Ultrathin Hafnium Oxide with a Clean van der Waals Interface for Two-Dimensional Sandwich Heterostructure Electronics

Integrating high-κ dielectrics with a small equivalent oxide thickness (EOT) with two-dimensional (2D) semiconductors for low-power consumption van der Waals (vdW) heterostructure electronics remains challenging in meeting both interface quality and dielectric property requirements. Here, we demonstrate the integration of ultrathin amorphous HfOx sandwiched within vdW heterostructures by the selective thermal oxidation of HfSe2 precursors. The self-cleaning process ensures a high-quality interface with a low interface state density of 1011-1012 cm-2 eV-1. The synthesized HfOx displays excellent dielectric properties with an EOT of ∼1.5 nm, i.e., a high κ of ∼16, an ultralow leakage current of 10-6 A/cm2, and an impressively high breakdown field of 9.5 MV/cm. This facilitates low-power consumption vdW heterostructure MoS2 transistors, demonstrating steep switching with a low subthreshold swing of 61 mV/decade. This one-step integration of high-κ dielectrics into vdW sandwich heterostructures holds immense potential for developing low-power consumption 2D electronics while meeting comprehensive dielectric requirements.

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Silicon transistors are approaching their physical limit, calling for the emergence of a technological revolution. As the acknowledged ultimate version of transistor channels, 2D semiconductors are of interest for the development of post-Moore electronics due to their useful properties and all-in-one potentials. Here, the promise and current status of 2D semiconductors and transistors are reviewed, from materials and devices to integrated applications. First, we outline the evolution and challenges of silicon-based integrated circuits, followed by a detailed discussion on the properties and preparation strategies of 2D semiconductors and van der Waals heterostructures. Subsequently, the significant progress of 2D transistors, including device optimization, large-scale integration, and unconventional devices, are presented. We also examine 2D semiconductors for advanced heterogeneous and multifunctional integration beyond CMOS. Finally, the key technical challenges and potential strategies for 2D transistors and integrated circuits are also discussed. We envision that the field of 2D semiconductors and transistors could yield substantial progress in the upcoming years and hope this review will trigger the interest of scientists planning their next experiment.

Non-volatile rippled-assisted optoelectronic array for all-day motion detection and recognition

In-sensor processing has the potential to reduce the energy consumption and hardware complexity of motion detection and recognition. However, the state-of-the-art all-in-one array integration technologies with simultaneous broadband spectrum image capture (sensory), image memory (storage) and image processing (computation) functions are still insufficient. Here, macroscale (2 × 2 mm2) integration of a rippled-assisted optoelectronic array (18 × 18 pixels) for all-day motion detection and recognition. The rippled-assisted optoelectronic array exhibits remarkable uniformity in the memory window, optically stimulated non-volatile positive and negative photoconductance. Importantly, the array achieves an extensive optical storage dynamic range exceeding 106, and exceptionally high room-temperature mobility up to 406.7 cm2 V-1 s-1, four times higher than the International Roadmap for Device and Systems 2028 target. Additionally, the spectral range of each rippled-assisted optoelectronic processor covers visible to near-infrared (405 nm-940 nm), achieving function of motion detection and recognition.

The Roadmap of 2D Materials and Devices Toward Chips

Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked.

Hidden Direct Bandgap of Bi2O2Se by Se Vacancy and Enhanced Direct Bandgap of Bismuth Oxide Overlayer

The Bi2O2Se surfaces are well-known to possess 50% Se vacancies, yet they have shown no in-gap states within the indirect bandgap (∼0.8 eV). We have found that the hidden in-gap states arising from the Se vacancies in a 2 × 1 pattern induce a reduced direct bandgap (∼0.5 eV). Such a reduced direct bandgap is responsible for the high electron mobility of Bi2O2Se. Moreover, the Bi oxide overlayers of the Bi thin films, formed through air exposure and annealing, unexpectedly exhibit a large direct bandgap (∼2.1 eV). The simplified fabrication of Bi oxide overlayers provides promise for improving Bi2O2Se electronic devices and enhancing photocatalytic activity.

Asymmetric conducting route and potential redistribution determine the polarization-dependent conductivity in layered ferroelectrics

Precise control of the conductivity of layered ferroelectric semiconductors is required to make these materials suitable for advanced transistor, memory and logic circuits. Although proof-of-principle devices based on layered ferroelectrics have been demonstrated, it remains unclear how the polarization inversion induces conductivity changes. Therefore, function design and performance optimization remain cumbersome. Here we combine ab initio calculations with transport experiments to unveil the mechanism underlying the polarization-dependent conductivity in ferroelectric channel field-effect transistors. We find that the built-in electric field gives rise to an asymmetric conducting route formed by the hidden Stark effect and competes with the potential redistribution caused by the external field of the gate. Furthermore, leveraging our mechanistic findings, we control the conductivity threshold in α-In2Se3 ferroelectric channel field-effect transistors. We demonstrate logic-in-memory functionality through the implementation of electrically self-switchable primary (AND, OR) and composite (XOR, NOR, NAND) logic gates. Our work provides mechanistic insights into conductivity modulation in a broad class of layered ferroelectrics, providing foundations for their application in logic and memory electronics.

Tunable Contacts of Bi2 O2 Se Nanosheets MSM Photodetectors by Metal-Assisted Transfer Approach for Self-Powered Near-Infrared Photodetection

Owing to the Fermi pinning effect arose in the metal electrodes deposition process, metal-semiconductor contact is always independent on the work function, which challenges the next-generation optoelectronic devices. In this work, a metal-assisted transfer approach is developed to transfer Bi2 O2 Se nanosheets onto the pre-deposited metal electrodes, benefiting to the tunable metal-semiconductor contact. The success in Bi2 O2 Se nanosheets transfer is contributed to the stronger van der Waals adhesion of metal electrodes than that of growth substrates. With the pre-deposited asymmetric electrodes, the self-powered near-infrared photodetectors are realized, demonstrating low dark current of 0.04 pA, high Ilight /Idark ratio of 380, fast rise and decay times of 4 and 6 ms, respectively, under the illumination of 1310 nm laser. By pre-depositing the metal electrodes on polyimide and glass, high-performance flexible and omnidirectional self-powered near-infrared photodetectors are achieved successfully. This study opens up new opportunities for low-dimensional semiconductors in next-generation high-performance optoelectronic devices.

Comprehensive understanding of electron mobility and superior performance in sub-10 nm DG ML tetrahex-GeC2 n-type MOSFETs

In this study, we have investigated the electron mobility of monolayered (ML) tetrahex-GeC2 by solving the linearized Boltzmann transport equation (BTE) with the normalized full-band relaxation time approximation (RTA) using density functional theory (DFT). Contrary to what the deformation potential theory (DPT) suggested, the ZA acoustic mode was determined to be the most restrictive for electron mobility, not the LA mode. The electron mobility at 300 K is 803 cm2 (V s)-1, exceeding the 400 cm2 (V s)-1 of MoS2 which was calculated using the same method and measured experimentally. The ab initio quantum transport simulations were performed to assess the performance limits of sub-10 nm DG ML tetrahex-GeC2 n-type MOSFETs, including gate lengths (Lg) of 3 nm, 5 nm, 7 nm, and 9 nm, with the underlap (UL) effect considered for the first two. For both high-performance (HP) and low-power (LP) applications, their on-state currents (Ion) can meet the requirements of similar nodes in the ITRS 2013. In particular, the Ion is more remarkable for HP applications than that of the extensively studied MoS2. For LP applications, the Ion values at Lg of 7 and 9 nm surpass those of arsenene, known for having the largest Ion among 2D semiconductors. Subthreshold swings (SSs) as low as 69/53 mV dec-1 at an Lg of 9 nm were observed for HP/LP applications, and 73 mV dec-1 at an Lg of 5 nm for LP applications, indicating the excellent gate control capability. Moreover, the delay time τ and power dissipation (PDP) at Lg values of 3 nm, 5 nm, 7 nm, and 9 nm are all below the upper limits of the ITRS 2013 HP/LP proximity nodes and are comparable to or lower than those of typical 2D semiconductors. The sub-10 nm DG ML tetrahex-GeC2 n-type MOSFETs can be down-scaled to 9 nm and 5 nm for HP and LP applications, respectively, displaying desirable Ion, delay time τ, and PDP in the ballistic limit, making them a potential choice for sub-10 nm transistors.

Robust multiferroic in interfacial modulation synthesized wafer-scale one-unit-cell of chromium sulfide

Multiferroic materials offer a promising avenue for manipulating digital information by leveraging the cross-coupling between ferroelectric and ferromagnetic orders. Despite the ferroelectricity has been uncovered by ion displacement or interlayer-sliding, one-unit-cell of multiferroic materials design and wafer-scale synthesis have yet to be realized. Here we develope an interface modulated strategy to grow 1-inch one-unit-cell of non-layered chromium sulfide with unidirectional orientation on industry-compatible c-plane sapphire. The interfacial interaction between chromium sulfide and substrate induces the intralayer-sliding of self-intercalated chromium atoms and breaks the space reversal symmetry. As a result, robust room-temperature ferroelectricity (retaining more than one month) emerges in one-unit-cell of chromium sulfide with ultrahigh remanent polarization. Besides, long-range ferromagnetic order is discovered with the Curie temperature approaching 200 K, almost two times higher than that of bulk counterpart. In parallel, the magnetoelectric coupling is certified and which makes 1-inch one-unit-cell of chromium sulfide the largest and thinnest multiferroics.

Polarized Tunneling Transistor for Ultralow-Energy-Consumption Artificial Synapse toward Neuromorphic Computing

Neural networks based on low-power artificial synapses can significantly reduce energy consumption, which is of great importance in today's era of artificial intelligence. Two-dimensional (2D) material-based floating-gate transistors (FGTs) have emerged as compelling candidates for simulating artificial synapses owing to their multilevel and nonvolatile data storage capabilities. However, the low erasing/programming speed of FGTs renders them unsuitable for low-energy-consumption artificial synapses, thereby limiting their potential in high-energy-efficient neuromorphic computing. Here, we introduce a FGT-inspired MoS2/Trap/PZT heterostructure-based polarized tunneling transistor (PTT) with a simple fabrication process and significantly enhanced erasing/programming speed. Distinct from the FGT, the PTT lacks a tunnel layer, leading to a marked improvement in its erasing/programming speed. The PTT's highest erasing/programming (operation) speed can reach ∼20 ns, which outperforms the performance of most FGTs based on 2D heterostructures. Furthermore, the PTT has been utilized as an artificial synapse, and its weight-update energy consumption can be as low as 0.0002 femtojoule (fJ), which benefits from the PTT's ultrahigh operation speed. Additionally, PTT-based artificial synapses have been employed in constructing artificial neural network simulations, achieving facial-recognition accuracy (95%). This groundbreaking work makes it possible for fabricating future high-energy-efficient neuromorphic transistors utilizing 2D materials.

Layer-Controlled Growth of Single-Crystalline 2D Bi2O2Se Film Driven by Interfacial Reconstruction

As semiconductor scaling continues to reach sub-nanometer levels, two-dimensional (2D) semiconductors are emerging as a promising candidate for the post-silicon material. Among these alternatives, Bi2O2Se has risen as an exceptionally promising 2D semiconductor thanks to its excellent electrical properties, attributed to its appropriate bandgap and small effective mass. However, unlike other 2D materials, growth of large-scale Bi2O2Se films with precise layer control is still challenging due to its large surface energy caused by relatively strong interlayer electrostatic interactions. Here, we present the successful growth of a wafer-scale (∼3 cm) Bi2O2Se film with precise thickness control down to the monolayer level on TiO2-terminated SrTiO3 using metal-organic chemical vapor deposition (MOCVD). Scanning transmission electron microscopy (STEM) analysis confirmed the formation of a [BiTiO4]1- interfacial structure, and density functional theory (DFT) calculations revealed that the formation of [BiTiO4]1- significantly reduced the interfacial energy between Bi2O2Se and SrTiO3, thereby promoting 2D growth. Additionally, spectral responsivity measurements of two-terminal devices confirmed a bandgap increase of up to 1.9 eV in monolayer Bi2O2Se, which is consistent with our DFT calculations. Finally, we demonstrated high-performance Bi2O2Se field-effect transistor (FET) arrays, exhibiting an excellent average electron mobility of 56.29 cm2/(V·s). This process is anticipated to enable wafer-scale applications of 2D Bi2O2Se and facilitate exploration of intriguing physical phenomena in confined 2D systems.

Ultrahigh responsivity of non-van der Waals Bi2O2Se photodetector

Bismuth oxyselenide has recently gained tremendous attention as a promising 2D material for next-generation electronic and optoelectronic devices due to its ultrahigh mobility, moderate bandgap, exceptional environmental stability, and presence of high-dielectric constant native oxide. In this study, we have synthesized single-crystalline nanosheets of Bismuth oxyselenide with thicknesses measuring below ten nanometers on Fluorophlogopite mica using an atmospheric pressure chemical vapor deposition system. We transferred as-grown samples to different substrates using a non-corrosive nail polish-assisted dry transfer method. Back-gated Bi2O2Se field effect transistors showed decent field effect mobility of 100 cm2V-1s-1. The optoelectronic property study revealed an ultrahigh responsivity of 1.16 × 106A W-1and a specific detectivity of 2.55 × 1013Jones. The samples also exhibited broadband photoresponse and gate-tunable photoresponse time. These results suggest that Bi2O2Se is an excellent candidate for future high-performance optoelectronic device applications.

Site-directed placement of three-dimensional DNA origami

The combination of lithographic methods with two-dimensional DNA origami self-assembly has led, among others, to the development of photonic crystal cavity arrays and the exploration of sensing nanoarrays where molecular devices are patterned on the sub-micrometre scale. Here we extend this concept to the third dimension by mounting three-dimensional DNA origami onto nanopatterned substrates, followed by silicification to provide hybrid DNA-silica structures exhibiting mechanical and chemical stability and achieving feature sizes in the sub-10-nm regime. Our versatile and scalable method relying on self-assembly at ambient temperatures offers the potential to three-dimensionally position any inorganic and organic components compatible with DNA origami nanoarchitecture, demonstrated here with gold nanoparticles. This way of nanotexturing could provide a route for the low-cost production of complex and three-dimensionally patterned surfaces and integrated devices designed on the molecular level and reaching macroscopic dimensions.

An Amorphous Native Oxide Shell for High Bias-Stress Stability Nanowire Synaptic Transistor

The inhomogeneous native oxide shells on the surfaces of III-V group semiconductors typically yield inferior and unstable electrical properties metrics, challenging the development of next-generation integrated circuits. Herein, the native GaOx shells are profitably utilized by a simple in-situ thermal annealing process to achieve high-performance GaSb nanowires (NWs) field-effect-transistors (FETs) with excellent bias-stress stability and synaptic behaviors. By an optimal annealing time of 5 min, the as-constructed GaSb NW FET demonstrates excellent stability with a minimal shift of transfer curve (ΔVth ≈ 0.54 V) under a 60 min gate bias, which is far more stable than that of pristine GaSb NW FET (ΔVth ≈ 8.2 V). When the high bias-stress stability NW FET is used as the chargeable-dielectric free synaptic transistor, the typical synaptic behaviors, such as short-term plasticity, long-term plasticity, spike-time-dependent plasticity, and reliable learning stability are demonstrated successfully through the voltage tests. The mobile oxygen ion in the native GaOx shell strongly offsets the trapping states and leads to enhanced bias-stress stability and charge retention capability for synaptic behaviors. This work provides a new way of utilizing the native oxide shell to realize stable FET for chargeable-dielectric free neuromorphic computing systems.

p-Type Two-Dimensional Semiconductors: From Materials Preparation to Electronic Applications

Two-dimensional (2D) materials are regarded as promising candidates in many applications, including electronics and optoelectronics, because of their superior properties, including atomic-level thickness, tunable bandgaps, large specific surface area, and high carrier mobility. In order to bring 2D materials from the laboratory to industrialized applications, materials preparation is the first prerequisite. Compared to the n-type analogs, the family of p-type 2D semiconductors is relatively small, which limits the broad integration of 2D semiconductors in practical applications such as complementary logic circuits. So far, many efforts have been made in the preparation of p-type 2D semiconductors. In this review, we overview recent progresses achieved in the preparation of p-type 2D semiconductors and highlight some promising methods to realize their controllable preparation by following both the top-down and bottom-up strategies. Then, we summarize some significant application of p-type 2D semiconductors in electronic and optoelectronic devices and their superiorities. In end, we conclude the challenges existed in this field and propose the potential opportunities in aspects from the discovery of novel p-type 2D semiconductors, their controlled mass preparation, compatible engineering with silicon production line, high-κ dielectric materials, to integration and applications of p-type 2D semiconductors and their heterostructures in electronic and optoelectronic devices. Overall, we believe that this review will guide the design of preparation systems to fulfill the controllable growth of p-type 2D semiconductors with high quality and thus lay the foundations for their potential application in electronics and optoelectronics.

Vertically grown ultrathin Bi2SiO5 as high-κ single-crystalline gate dielectric

Single-crystalline high-κ dielectric materials are desired for the development of future two-dimensional (2D) electronic devices. However, curent 2D gate insulators still face challenges, such as insufficient dielectric constant and difficult to obtain free-standing and transferrable ultrathin films. Here, we demonstrate that ultrathin Bi₂SiO₅ crystals grown by chemical vapor deposition (CVD) can serve as excellent gate dielectric layers for 2D semiconductors, showing a high dielectric constant (>30) and large band gap (~3.8 eV). Unlike other 2D insulators synthesized via in-plane CVD on substrates, vertically grown Bi₂SiO₅ can be easily transferred onto other substrates by polymer-free mechanical pressing, which greatly facilitates its ideal van der Waals integration with few-layer MoS₂ as high-κ dielectrics and screening layers. The Bi₂SiO₅ gated MoS₂ field-effect transistors exhibit an ignorable hysteresis (~3 mV) and low drain induced barrier lowering (~5 mV/V). Our work suggests vertically grown Bi₂SiO₅ nanoflakes as promising candidates to improve the performance of 2D electronic devices.