Three-dimensional integration of two-dimensional field-effect transistors

Precursor-Confined Chemical Vapor Deposition of 2D Single-Crystalline SexTe1-x Nanosheets for p-Type Transistors and Inverters

Two-dimensional (2D) tellurium (Te) is emerging as a promising p-type candidate for constructing complementary metal-oxide-semiconductor (CMOS) architectures. However, its small bandgap leads to a high leakage current and a low on/off current ratio. Although alloying Te with selenium (Se) can tune its bandgap, thermally evaporated SexTe1-x thin films often suffer from grain boundaries and high-density defects. Herein, we introduce a precursor-confined chemical vapor deposition (CVD) method for synthesizing single-crystalline SexTe1-x alloy nanosheets. These nanosheets, with tunable compositions, are ideal for high-performance field-effect transistors (FETs) and 2D inverters. The preformation of Se-Te frameworks in our developed CVD method plays a critical role in the growth of SexTe1-x nanosheets with high crystallinity. Optimizing the Se composition resulted in a Se0.30Te0.70 nanosheet-based p-type FET with a large on/off current ratio of 4 × 105 and a room-temperature hole mobility of 120 cm2·V-1·s-1, being eight times higher than thermally evaporated SexTe1-x with similar composition and thickness. Moreover, we successfully fabricated an inverter based on p-type Se0.30Te0.70 and n-type MoS2 nanosheets, demonstrating a typical voltage transfer curve with a gain of 30 at an operation voltage of Vdd = 3 V.

Van der Waals polarity-engineered 3D integration of 2D complementary logic

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1-3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6-8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9-17) and MoS2 (refs. 11,18-28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V-1 s-1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Synthesis of 2D Gallium Sulfide with Ultraviolet Emission by MOCVD

Two-dimensional (2D) materials exhibit the potential to transform semiconductor technology. Their rich compositional and stacking varieties allow tailoring materials' properties toward device applications. Monolayer to multilayer gallium sulfide (GaS) with its ultraviolet band gap, which can be tuned by varying the layer number, holds promise for solar-blind photodiodes and light-emitting diodes as applications. However, achieving commercial viability requires wafer-scale integration, contrasting with established, limited methods such as mechanical exfoliation. Here the one-step synthesis of 2D GaS is introduced via metal-organic chemical vapor deposition on sapphire substrates. The pulsed-mode deposition of industry-standard precursors promotes 2D growth by inhibiting the vapor phase and on-surface pre-reactions. The interface chemistry with the growth of a Ga adlayer that results in an epitaxial relationship is revealed. Probing structure and composition validate thin-film quality and 2D nature with the possibility to control the thickness by the number of GaS pulses. The results highlight the adaptability of established growth facilities for producing atomically thin to multilayered 2D semiconductor materials, paving the way for practical applications.

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40 nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7 nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

A 2D Cryptographic Hash Function Incorporating Homomorphic Encryption for Secure Digital Signatures

User authentication is a critical aspect of any information exchange system which verifies the identities of individuals seeking access to sensitive information. Conventionally, this approachrelies on establishing robust digital signature protocols which employ asymmetric encryption techniques involving a key pair consisting of a public key and its matching private key. In this article, a user verification platform constructed using integrated circuits (ICs) with atomically thin two-dimensional (2D) monolayer molybdenum disulfide (MoS2 ) memtransistors is presented. First, generation of secure cryptographic keys is demonstrated by exploiting the inherent stochasticity of carrier trapping and detrapping at the 2D/oxide interface trap sites. Subsequently, the ability to manipulate the functionality of logical NOR is leveraged to create a secure one-way hash function which when homomorphically operated upon with NAND, XOR, OR, NOT, and AND logic circuits generate distinct digital signatures. These signatures when subsequently decrypted, verify the authenticity of the receiver while ensuring complete preservation of data integrity and confidentiality as the underlying information is never revealed. Finally, the advantages of implementing a NOR-based hashing techniques in comparison to the conventional XOR-based encryption method are established. This demonstration highlights the potential of 2D-based ICs in developing critical hardware information security primitives.