RRAM-based synapse devices for neuromorphic systems

Eco-Friendly Biomemristive Nonvolatile Memory: Harnessing Organic Waste for Sustainable Technology

Organic material-based bioelectronic nonvolatile memory devices have recently received a lot of attention due to their environmental compatibility, simple fabrication recipe, preferred scalability, low cost, low power consumption, and numerous additional advantages. Resistive random-access memory (RRAM) devices work on the principle of resistive switching, which has the potential for applications in memory storage and neuromorphic computing. Here, natural organically grown orange peel was used to extract biocompatible pectin to design a resistive switching-based memory device of the structure Ag/Pectin/Indium tin oxide (ITO), and the behavior was studied between a temperature range of 10K and 300K. The microscopic characterization revealed the texture of the surface and thickness of the layers. The memristive current-voltage characteristics performed over 1000 consecutive cycles of repeated switching revealed sustainable bipolar resistive switching behavior with a high ON/OFF ratio. The underlying principle of Resistive Switching behavior is based on the formation of conductive filaments between the electrodes, which is explained in this work. Further, we have also designed a 2 × 2 crossbar array of RRAM devices to demonstrate various logic circuit operations useful for neuromorphic computing. The robust switching characteristics suggest possible uses of such devices for the design of ecofriendly bioelectronic memory applications and in-memory computing.

Improvement of volatile switching in scaled silicon nanofin memristor for high performance and efficient reservoir computing

Conductive-bridge random access memory can be used as a physical reservoir for temporal learning in reservoir computing owing to its volatile nature. Herein, a scaled Cu/HfOx/n+-Si memristor was fabricated and characterized for reservoir computing. The scaled, silicon nanofin bottom electrode formation is verified by scanning electron and transmission electron microscopy. The scaled device shows better cycle-to-cycle switching variability characteristics compared with those of large-sized cells. In addition, synaptic characteristics such as conductance changes due to pulses, paired-pulse facilitation, and excitatory postsynaptic currents are confirmed in the scaled memristor. High-pattern accuracy is demonstrated by deep neural networks applied in neuromorphic systems in conjunction with the use of the Modified National Institute of Standards and Technology database. Furthermore, a reservoir computing system is introduced with six different states attained by adjusting the amplitude of the input pulse. Finally, high-performance and efficient volatile reservoir computing in the scaled device is demonstrated by conductance control and system-level reservoir computing simulations.

Realization of Multiple Synapse Plasticity by Coexistence of Volatile and Nonvolatile Characteristics of Interface Type Memristor

Studies on neuromorphic computing systems are becoming increasingly important in the big-data-processing era as these systems are capable of energy-efficient parallel data processing and can overcome the present limitations owing to the von Neumann bottleneck. The Pt/WOx/ITO resistive random-access memory device can be used to implement versatile synapse functions because it possesses both volatile and nonvolatile characteristics. The gradual increase and decrease in the current of the Pt/WOx/ITO device with its uniform resistance state for endurance and retention enables additional synaptic applications that can be controlled using electric pulses. If the volatile and nonvolatile device properties are set through rehearsal and forgetting processes, the device can emulate various synaptic behaviors, such as potentiation and depression, paired-pulse facilitation, post-tetanic potentiation, image training, Hebbian learning rules, excitatory postsynaptic current, and Pavlov's test. Furthermore, reservoir computing can be implemented for applications such as pattern generation and recognition. This emphasizes the various applications of future neuromorphic devices, demonstrating the various favorable characteristics of pulse-enhanced Pt/WOx/ITO devices.

Artificial sensory system based on memristive devices

In the biological nervous system, the integration and cooperation of parallel system of receptors, neurons, and synapses allow efficient detection and processing of intricate and disordered external information. Such systems acquire and process environmental data in real-time, efficiently handling complex tasks with minimal energy consumption. Memristors can mimic typical biological receptors, neurons, and synapses by implementing key features of neuronal signal-processing functions such as selective adaption in receptors, leaky integrate-and-fire in neurons, and synaptic plasticity in synapses. External stimuli are sensitively detected and filtered by "artificial receptors," encoded into spike signals via "artificial neurons," and integrated and stored through "artificial synapses." The high operational speed, low power consumption, and superior scalability of memristive devices make their integration with high-performance sensors a promising approach for creating integrated artificial sensory systems. These integrated systems can extract useful data from a large volume of raw data, facilitating real-time detection and processing of environmental information. This review explores the recent advances in memristor-based artificial sensory systems. The authors begin with the requirements of artificial sensory elements and then present an in-depth review of such elements demonstrated by memristive devices. Finally, the major challenges and opportunities in the development of memristor-based artificial sensory systems are discussed.

Implementation of Artificial Synapse Using IGZO-Based Resistive Switching Device

In this study, we present the resistive switching characteristics and the emulation of a biological synapse using the ITO/IGZO/TaN device. The device demonstrates efficient energy consumption, featuring low current resistive switching with minimal set and reset voltages. Furthermore, we establish that the device exhibits typical bipolar resistive switching with the coexistence of non-volatile and volatile memory properties by controlling the compliance during resistive switching phenomena. Utilizing the IGZO-based RRAM device with an appropriate pulse scheme, we emulate a biological synapse based on its electrical properties. Our assessments include potentiation and depression, a pattern recognition system based on neural networks, paired-pulse facilitation, excitatory post-synaptic current, and spike-amplitude dependent plasticity. These assessments confirm the device's effective emulation of a biological synapse, incorporating both volatile and non-volatile functions. Furthermore, through spike-rate dependent plasticity and spike-timing dependent plasticity of the Hebbian learning rules, high-order synapse imitation was done.

Spike Optimization to Improve Properties of Ferroelectric Tunnel Junction Synaptic Devices for Neuromorphic Computing System Applications

The continuous advancement of Artificial Intelligence (AI) technology depends on the efficient processing of unstructured data, encompassing text, speech, and video. Traditional serial computing systems based on the von Neumann architecture, employed in information and communication technology development for decades, are not suitable for the concurrent processing of massive unstructured data tasks with relatively low-level operations. As a result, there arises a pressing need to develop novel parallel computing systems. Recently, there has been a burgeoning interest among developers in emulating the intricate operations of the human brain, which efficiently processes vast datasets with remarkable energy efficiency. This has led to the proposal of neuromorphic computing systems. Of these, Spiking Neural Networks (SNNs), designed to closely resemble the information processing mechanisms of biological neural networks, are subjects of intense research activity. Nevertheless, a comprehensive investigation into the relationship between spike shapes and Spike-Timing-Dependent Plasticity (STDP) to ensure efficient synaptic behavior remains insufficiently explored. In this study, we systematically explore various input spike types to optimize the resistive memory characteristics of Hafnium-based Ferroelectric Tunnel Junction (FTJ) devices. Among the various spike shapes investigated, the square-triangle (RT) spike exhibited good linearity and symmetry, and a wide range of weight values could be realized depending on the offset of the RT spike. These results indicate that the spike shape serves as a crucial indicator in the alteration of synaptic connections, representing the strength of the signals.

Multifunctional Crystalline InGaSnO Phototransistor Exhibiting Photosensing and Photosynaptic Behavior Using Oxygen Vacancy Engineering

A multifunctional optoelectronic device implementing photodetector, photosynapse, and photomemory is of increasing attention for neuromorphic system. This enables multiple devices to be replaced with a single device, which simplifies the structure of complex, highly integrated electronics. Here, a multifunctional c-axis-aligned crystalline indium gallium tin oxide thin-film transistor (TFT) optoelectronic device is demonstrated. The photodetecting and photosynaptic behaviors could be demonstrated by tuning of gate pulse. The device shows a high responsivity of 1.1 × 106  A W-1 to blue light (467 nm) and cutoff frequency (f-3dB ) of 2400 Hz exhibiting high frequency switching using a gate reset pulse. It is possible to implement photosynaptic behavior using persistent photoconductivity effect by applying a gate bias to make the TFT depletion mode. When potentiation and depression of synaptic weight are implemented with light pulse and gate voltage pulse, respectively, 64-state potentiation-depression curves are demonstrated with excellent nonlinearity of 1.13 and 2.03, respectively. When an artificial neural network is constructed with this device for the Modified National Institute of Standards and Technology training pattern recognition simulation, it shows a high pattern recognition accuracy of 90.4%.

Three-dimensional vertical structural electrochemical random access memory for high-density integrated synapse device

Three-terminal (3T) structured electrochemical random access memory (ECRAM) has been proposed as a synaptic device based on improved synaptic characteristics. However, the proposed 3T ECRAM has a larger area requirement than 2T synaptic devices; thereby limiting integration density. To overcome this limitation, this study presents the development of a high-density vertical structure for the 3T ECRAM. In addition, complementary metal-oxide semiconductor (CMOS)-compatible materials and 8-inch wafer-based CMOS fabrication processes were utilized to verify the feasibility of mass production. The achievements of this work demonstrate the potential for high-density integration and mass production of 3T ECRAM devices.

Intensive harmonized synapses with amorphous Cu2O-based memristors using ultrafine Cu nanoparticle sublayers formed via atomically controlled electrochemical pulse deposition

Resistive random-access memory (RRAM) devices have significant advantages for neuromorphic computing but have fatal problems of uncontrollability and abrupt resistive switching behaviors degrading their synaptic performance. In this paper, we propose the electrochemical design of an active Cu2O layer containing a strategic sublayer of ultrafine Cu nanoparticles (U-Cu NPs) to form uniformly dispersed conducting filaments, which can effectively improve the reliability for analog switching of RRAM-based neuromorphic computing. The electrochemical pulse deposited (EPD) U-Cu NPs are linked to the bottom electrode through a semi-conductive path within the bottom Cu2O layer, since the EPD is preferentially carried out on the conductive sites. All Cu2O films with U-Cu NPs are developed in situ in the single electrolyte bath without any pause. The proposed U-Cu NPs can concentrate the external electric field and can generate conductive filament paths for analog resistive switching. The applied electric field was uniformly spread to U-Cu NPs at the center of the active layer and displays resistive switching behavior via multiple conductive filaments. This shows a strong harmony between the resistance-switching characteristics and the analog operation of the active layer. This RRAM device shows outstanding gradual analog switching, great linearity, dynamic range, endurance, precision, speed, and retention characteristics simultaneously and adequately for neuromorphic computing by realizing multiple weak filament-type operation.

Reset-First and Multibit-Level Resistive-Switching Behavior of Lanthanum Nickel Oxide (LaNiO3-x) Thin Films

The resistive random-access memory (RRAM) with multi-level storage capability has been considered one of the most promising emerging devices to mimic synaptic behavior and accelerate analog computations. In this study, we investigated the reset-first bipolar resistive switching (RS) and multi-level characteristics of a LaNiO_3-x thin film deposited using a reactive magnetron co-sputtering method. Polycrystalline phases of LaNiO₃ (LNO), without La₂O₃ and NiO phases, were observed at similar fractions of Ni and La at a constant partial pressure of oxygen. The relative chemical proportions of Ni³⁺ and Ni²⁺ ions in LaNiO_3-x indicated that it was an oxygen-deficient LaNiO_3-x thin film, exhibiting RS behavior, compared to LNO without Ni²⁺ ions. The TiN/LaNiO_3-x/Pt devices exhibited gradual resistance changes under various DC/AC voltage sweeps and consecutive pulse modes. The nonlinearity values of the conductance, measured via constant-pulse programming, were 0.15 for potentiation and 0.35 for depression, indicating the potential of the as-fabricated devices as analog computing devices. The LaNiO_3-x-based device could reach multi-level states without an electroforming step and is a promising candidate for state-of-the-art RS memory and synaptic devices for neuromorphic computing.

Trade-off between Gradual Set and On/Off Ratio in HfOx-Based Analog Memory with a Thin SiOx Barrier Layer

HfO_x-based synapses are widely accepted as a viable candidate for both in-memory and neuromorphic computing. Resistance change in oxide-based synapses is caused by the motion of oxygen vacancies. HfO_x-based synapses typically demonstrate an abrupt nonlinear resistance change under positive bias application (set), limiting their viability as analog memory. In this work, a thin barrier layer of AlO_x or SiO_x is added to the bottom electrode/oxide interface to slow the migration of oxygen vacancies. Electrical results show that the resistance change in HfO_x/SiO_x devices is more controlled than the HfO_x devices during the set. While the on/off ratio for the HfO_x/SiO_x devices is still large (∼10), it is shown to be smaller than that of HfO_x/AlO_x and HfO_x devices. Finite element modeling suggests that the slower oxygen vacancy migration in HfO_x/SiO_x devices during reset results in a narrower rupture region in the conductive filament. The narrower rupture region causes a lower high resistance state and, thus, a smaller on/off ratio for the HfO_x/SiO_x devices. Overall, the results show that slowing the motion of oxygen vacancies in the barrier layer devices improves the resistance change during the set but lowers the on/off ratio.

Superior artificial synaptic properties applicable to neuromorphic computing system in HfOx-based resistive memory with high recognition rates

With the development of artificial intelligence and the importance of big data processing, research is actively underway to break away from data bottlenecks and modern Von Neumann architecture computing structures that consume considerable energy. Among these, hardware technology for neuromorphic computing is in the spotlight as a next-generation intelligent hardware system because it can efficiently process large amounts of data with low power consumption by simulating the brain’s calculation algorithm. In addition to memory devices with existing commercial structures, various next-generation memory devices, including memristors, have been studied to implement neuromorphic computing. In this study, we evaluated the synaptic characteristics of a resistive random access memory (ReRAM) with a Ru/HfOx /TiN structure. Under a series of presynaptic spikes, the device successfully exhibited remarkable long-term plasticity and excellent nonlinearity properties. This synaptic device has a high operating speed (20 ns, 50 ns), long data retention time (> 2 h @85 ℃) and high recognition rate (94.7%). Therefore, we propose that memory and learning capabilities can be used as promising HfOx -based memristors in next-generation artificial neuromorphic computing systems.

Linear and symmetric synaptic weight update characteristics by controlling filament geometry in oxide/suboxide HfOx bilayer memristive device for neuromorphic computing

Memristive devices have been explored as electronic synaptic devices to mimic biological synapses for developing hardware-based neuromorphic computing systems. However, typical oxide memristive devices suffered from abrupt switching between high and low resistance states, which limits access to achieve various conductance states for analog synaptic devices. Here, we proposed an oxide/suboxide hafnium oxide bilayer memristive device by altering oxygen stoichiometry to demonstrate analog filamentary switching behavior. The bilayer device with Ti/HfO₂/HfO_2-x(oxygen-deficient)/Pt structure exhibited analog conductance states under a low voltage operation through controlling filament geometry as well as superior retention and endurance characteristics thanks to the robust nature of filament. A narrow cycle-to-cycle and device-to-device distribution were also demonstrated by the filament confinement in a limited region. The different concentrations of oxygen vacancies at each layer played a significant role in switching phenomena, as confirmed through X-ray photoelectron spectroscopy analysis. The analog weight update characteristics were found to strongly depend on the various conditions of voltage pulse parameters including its amplitude, width, and interval time. In particular, linear and symmetric weight updates for accurate learning and pattern recognition could be achieved by adopting incremental step pulse programming (ISPP) operation scheme which rendered a high-resolution dynamic range with linear and symmetry weight updates as a consequence of precisely controlled filament geometry. A two-layer perceptron neural network simulation with HfO₂/HfO_2-x synapses provided an 80% recognition accuracy for handwritten digits. The development of oxide/suboxide hafnium oxide memristive devices has the capacity to drive forward the development of efficient neuromorphic computing systems.

α-Fe2O3-based artificial synaptic RRAM device for pattern recognition using artificial neural networks

We report on theα-Fe₂O₃-based artificial synaptic resistive random access memory device, which is a promising candidate for artificial neural networks (ANN) to recognize the images. The device consists of a structure Ag/α-Fe₂O₃/FTO and exhibits non-volatility with analog resistive switching characteristics. We successfully demonstrated synaptic learning rules such as long-term potentiation, long-term depression, and spike time-dependent plasticity. In addition, we also presented off-chip training to obtain good accuracy by backpropagation algorithm considering the synaptic weights obtained fromα-Fe₂O₃based artificial synaptic device. The proposedα-Fe₂O₃-based device was tested with the FMNIST and MNIST datasets and obtained a high pattern recognition accuracy of 88.06% and 97.6% test accuracy respectively. Such a high pattern recognition accuracy is attributed to the combination of the synaptic device performance as well as the novel weight mapping strategy used in the present work. Therefore, the ideal device characteristics and high ANN performance showed that the fabricated device can be useful for practical ANN implementation.

Low-Frequency Noise-Based Mechanism Analysis of Endurance Degradation in Al/αTiOx/Al Resistive Random Access Memory Devices

In this work, we analyze a resistive switching random access memory (RRAM) device with the metal-insulator-metal structure of Al/αTiO_x/Al. The transport mechanism of our RRAM device is trap-controlled space-charge limited conduction, which does not change during the endurance test. As the number of resistive switching (RS) cycles increases, the current in the low-resistance state (LRS) does not change significantly. In contrast, degradation in the high-resistance state (HRS) is noticeably evident. According to the RS cycle, the current shift fits well with the stretched-exponential equation. The normalized noise power spectral density (S_i/I²) measured in the HRS is an order of magnitude higher than that in the LRS owing to the difference in the degree of trap occupancy, which is responsible for the transition of resistance states. During the consecutive RS, the S_i/I² in the HRS rapidly decreases for approximately 100 cycles and then saturates. In contrast, in the LRS, the S_i/I² does not change significantly. Here we propose a model associated with the endurance degradation of the experimental device, and the model is verified with a 1/f noise measurement.

Short-Term Memory Characteristics of IGZO-Based Three-Terminal Devices

A three-terminal synaptic transistor enables more accurate controllability over the conductance compared with traditional two-terminal synaptic devices for the synaptic devices in hardware-oriented neuromorphic systems. In this work, we fabricated IGZO-based three-terminal devices comprising HfAlO_x and CeO_x layers to demonstrate the synaptic operations. The chemical compositions and thicknesses of the devices were verified by transmission electron microscopy and energy dispersive spectroscopy in cooperation. The excitatory post-synaptic current (EPSC), paired-pulse facilitation (PPF), short-term potentiation (STP), and short-term depression (STD) of the synaptic devices were realized for the short-term memory behaviors. The IGZO-based three-terminal synaptic transistor could thus be controlled appropriately by the amplitude, width, and interval time of the pulses for implementing the neuromorphic systems.

Forgetting memristor based STDP learning circuit for neural networks

The circuit implementation of STDP based on memristor is of great significance for the application of neural network. However, recent research shows that the research on the pure circuit implementation of forgetting memristor and STDP is still rare. This paper proposes a new STDP learning rule implementation circuit based on the forgetting memristor. This kind of forgetting memory resistance synapse makes the neural network have the function of time-division multiplexing, but the instability of short-term memory will affect the learning ability of the neural network. This paper analyzes and discusses the influence of synapses with long-term and short-term memory on the learning characteristics of neural network STDP, which lays a foundation for the construction of time-division multiplexing neural network with long-term and short-term memory synapses. Through this circuit, it is found that the volatile memristor has different behaviors to the stimulus signal in different initial states, and the resulting LTP phenomenon is more in line with the forgetting effect in biology. This circuit has multiple adjustable parameters, which can fit the STDP learning rules under different conditions. The application of neural network proves the availability of this circuit.

The gate injection-based field-effect synapse transistor with linear conductance update for online training

Neuromorphic computing, an alternative for von Neumann architecture, requires synapse devices where the data can be stored and computed in the same place. The three-terminal synapse device is attractive for neuromorphic computing due to its high stability and controllability. However, high nonlinearity on weight update, low dynamic range, and incompatibility with conventional CMOS systems have been reported as obstacles for large-scale crossbar arrays. Here, we propose the CMOS compatible gate injection-based field-effect transistor employing thermionic emission to enhance the linear conductance update. The dependence of the linearity on the conduction mechanism is examined by inserting an interfacial layer in the gate stack. To demonstrate the conduction mechanism, the gate current measurement is conducted under varying temperatures. The device based on thermionic emission achieves superior synaptic characteristics, leading to high performance on the artificial neural network simulation as 93.17% on the MNIST dataset.

Surface-Dominated HfO2 Nanorod-Based Memristor Exhibiting Highly Linear and Symmetrical Conductance Modulation for High-Precision Neuromorphic Computing

The switching characteristics and performance of oxide-based memristors are predominately determined by oxygen- or oxygen-vacancy-mediated redox reactions and the consequent formation of conducting filaments (CFs). Devices using oxide thin films as the switching layer usually require an electroforming process for subsequent switching operations, which induces large device-to-device variations. In addition, the hard-to-control redox reaction during repeated switching causes random fluctuations or degradation of each resistance state, hindering reliable switching operations. In this study, an HfO₂ nanorod (NR)-based memristor is proposed for simultaneously achieving highly uniform, electroforming-free, fast, and reliable analogue switching properties. The well-controlled redox reaction due to the easy gas exchange with the environment at the surface of the NRs enhances the generation of oxygen or oxygen vacancies during the switching operation, resulting in electroforming-free and reliable switching behavior. In addition, the one-dimensional surface growth of CFs facilitates highly linear conductance modulation with smaller conductance changes compared with the two-dimensional volume growth in thin-film-based memristors, resulting in a high accuracy of >92% in the Modified National Institute of Standards and Technology pattern-recognition test and desirable spike-timing-dependent plasticity.

Improved Resistive Switching with Low-Power Synaptic Behaviors of ZnO/Al2O3 Bilayer Structure

In this work, the resistive switching behavior of bilayer ZnO/Al₂O₃-based resistive-switching random access memory (RRAM) devices is demonstrated. The polycrystalline nature of the ZnO layer confirms the grain boundary, which helps easy oxygen ion diffusion. Multilevel resistance states were modulated under DC bias by varying the current compliance from 0.1 mA to 0.8 mA, the SET operations where the low resistance state of the memristor device was reduced from 25 kΩ to 2.4 kΩ. The presence of Al₂O₃ acts as a redox layer and facilitates oxygen vacancy exchange that demonstrates stable gradual conductance change. Stepwise disruption of conductive filaments was monitored depending on the slow DC voltage sweep rate. This is attributed to the atomic scale modulation of oxygen vacancies with four distinct reproducible quantized conductance states, which shows multilevel data storage capability. Moreover, several crucial synaptic properties such as potentiation/depression under identical presynaptic pulses and the spike-rate-dependent plasticity were implemented on ITO/ZnO/Al₂O₃/TaN memristor. The postsynaptic current change was monitored defining the long-term potentiation by increasing the presynaptic stimulus frequency from 5 Hz to 100 Hz. Moreover, the repetitive pulse voltage stimulation transformed the short-term plasticity to long-term plasticity during spike-number-dependent plasticity.

Controlled Growth of Wafer-Scale Transition Metal Dichalcogenides with a Vertical Composition Gradient for Artificial Synapses with High Linearity

Artificial synapses are promising for dealing with large amounts of data computing. Great progress has been made recently in terms of improving the on/off current ratio, the number of states, and the energy efficiency of synapse devices. However, the nonlinear weight update behavior of a synapse caused by the uncertain direction of the conductive filament leads to complex weight modulation, which degrades the delivery accuracy of information. Here we propose a strategy to improve the weight update behavior of synapses using chemical-vapor-deposition-grown transition metal dichalcogenides (TMDCs) with a vertical composition gradient, where the sulfur concentration decreases gradually along the thickness direction of TMDCs and thus forms a certain direction of the conduction filament for synapse devices. It is worth noting that the devices show an excellent linear conductance of potentiation and depression with a high linearity of 0.994 (surpassing most state-of-the-art synapses), have a large number of states, and are able to fabricate synapse arrays with wafer-scale. Furthermore, the devices based on the TMDCs with the vertical composition gradient exhibit an asymmetric feature of potentiation and depression behaviors with high linearity and follow the simulated linear Leaky ReLU function, resulting in a high recognition accuracy of 94.73%, which overcomes the unreliability issue in the Sigmoid function due to the vanishing gradient phenomenon. This study not only provides a universal method to grow TMDCs with a vertical composition gradient but also contributes to exploring highly linear synapses toward neuromorphic computing.

HfOx /AlOy Superlattice-Like Memristive Synapse

The adjustable conductance of a two-terminal memristor in a crossbar array can facilitate vector-matrix multiplication in one step, making the memristor a promising synapse for efficiently implementing neuromorphic computing. To achieve controllable and gradual switching of multi-level conductance, important for neuromorphic computing, a theoretical design of a superlattice-like (SLL) structure switching layer for the multi-level memristor is proposed and validated, refining the growth of conductive filaments (CFs) and preventing CFs from the abrupt formation and rupture. Ti/(HfO_x /AlO_y )_SLL /TiN memristors are shown with transmission electron microscopy , X-ray photoelectron spectroscopy , and ab initio calculation findings corroborate the SLL structure of HfO_x /AlO_y film. The optimized SLL memristor achieves outstanding conductance modulation performance with linearly synaptic weight update (nonlinear factor α = 1.06), and the convolutional neural network based on the SLL memristive synapse improves the handwritten digit recognition accuracy to 94.95%. Meanwhile, this improved synaptic device has a fast operating speed (30 ns), a long data retention time (≥ 10⁴ s at 85 ℃), scalability, and CMOS process compatibility. Finally, its physical nature is explored and the CF evolution process is characterized using nudged elastic band calculations and the conduction mechanism fitting. In this work, as an example the HfO_x /AlO_y SLL memristor provides a design viewpoint and optimization strategy for neuromorphic computing.

Resistive Switching and Synaptic Characteristics in ZnO/TaON-Based RRAM for Neuromorphic System

We fabricated an ITO/ZnO/TaON/TaN device as nonvolatile memory (NVM) with resistive switching for complementary metal-oxide-semiconductor (CMOS) compatibility. It is appropriate for the age of big data, which demands high speed and capacity. We produced a TaON layer by depositing a ZnO layer on a TaN layer using an oxygen-reactive radio frequency (RF) sputtering system. The bi-layer formation of ZnO and TaON interferes with the filament rupture after the forming process and then raises the current level slightly. The current levels were divided into high- and low-compliance modes. The retention, endurance, and pulse conductance were verified with a neuromorphic device. This device was stable and less consumed when it was in low mode rather than high mode.

Intrinsic variation effect in memristive neural network with weight quantization

To analyze the effect of the intrinsic variations of the memristor device on the neuromorphic system, we fabricated 32 × 32 Al₂O₃/TiO_x-based memristor crossbar array and implemented 3 bit multilevel conductance as weight quantization by utilizing the switching characteristics to minimize the performance degradation of the neural network. The tuning operation for 8 weight levels was confirmed with a tolerance of ±4μA (±40μS). The endurance and retention characteristics were also verified, and the random telegraph noise (RTN) characteristics were measured according to the weight range to evaluate the internal stochastic variation effect. Subsequently, a memristive neural network was constructed by off-chip training with differential memristor pairs for the Modified National Institute of Standards and Technology (MNIST) handwritten dataset. The pre-trained weights were quantized, and the classification accuracy was evaluated by applying the intrinsic variations to each quantized weight. The intrinsic variations were applied using the measured weight inaccuracy given by the tuning tolerance, RTN characteristics, and the fault device yield. We believe these results should be considered when the pre-trained weights are transferred to a memristive neural network by off-chip training.

Novel training method for metal-oxide memristive synapse device to overcome trade-off between linearity and dynamic range

Synapse devices are essential for the hardware implementation of neuromorphic computing systems. However, it is difficult to realize ideal synapse devices because of issues such as nonlinear conductance change (linearity) and a small number of conductance states (dynamic range). In this study, the correlation between the linearity and dynamic range was investigated. Consequently, we found a trade-off relationship between the linearity and dynamic range and proposed a novel training method to overcome this trade-off.

Improved resistive switching characteristics of a multi-stacked HfO2/Al2O3/HfO2 RRAM structure for neuromorphic and synaptic applications: experimental and computational study

Atomic Layer Deposition (ALD) was used for a tri-layer structure (HfO2/Al2O3/HfO2) at low temperature over an Indium Tin Oxide (ITO) transparent electrode. First, the microstructure of the fabricated TaN/HfO2/Al2O3/HfO2/ITO RRAM device was examined by the cross-sectional High-Resolution Transmission Electron Microscopy (HRTEM). Then, Energy Dispersive X-ray Spectroscopy (EDS) was performed to probe compositional mapping. The bipolar resistive switching mode of the device was confirmed through SET/RESET characteristic plots for 100 cycles as a function of applied biasing voltage. An endurance test was performed for 100 DC switching cycles @0.2 V wherein; data retention was found up to 104 s. Moreover, for better insight into the charge conduction mechanism in tri-layer HfO2/Al2O3/HfO2, based on oxygen vacancies (VOX), total density of states (TDOS), partial density of states (PDOS) and isosurface three-dimensional charge density analysis was performed using WEIN2k and VASP simulation packages under Perdew-Burke-Ernzerhof _Generalized Gradient approximation (PBE-GGA). The experimental and theoretical outcomes can help in finding proper stacking of the active resistive switching (RS) layer for resistive random-access memory (RRAM) applications.

Improved analog switching characteristics of Ta2O5-based memristor using indium tin oxide buffer layer for neuromorphic computing

A memristor is defined as a non-volatile memory switching two-terminal resistor, and a memristor with digital switching characteristics is widely studied as a next-generation non-volatile memory because of its simple structure, high integration density, and low power consumption. Recently, analog memristors with gradual resistance switching (RS) characteristics have garnered great attention because of their potential to implement artificial synapses that can emulate the brain functions. Transition metal oxides are thought to be strong candidate materials for the RS. In particular, tantalum oxide (TaO_x)-based memristive devices provide stable and durable switching characteristics. TaO_x-based memristors utilize analog switching characteristics and have excellent durability and reliability, so they can be applied as artificial synaptic device. In this study, the characteristics of analog RS using Ta₂O₅-based memristive devices were investigated. The current level of the Pt/Ta₂O₅/Pt memristors was improved by adjusting the thickness of Ta₂O₅. In particular, when an indium-tin-oxide (ITO) buffer layer was added to Ta₂O₅forming a Pt/ITO/Ta₂O₅/Pt heterostructured double-layer device, it showed more symmetrical potentiation and depression characteristics under both polarities than a single-layer device without ITO layer. The symmetrical and linear potentiation and depression characteristics are essential for the development of efficient memristor-based neuromorphic systems. Insertion of the ITO buffer layer improves linearity, symmetry, and stability of the analog RS properties of Ta₂O₅-based memristors to artificial synapses.

Emergent solution based IGZO memristor towards neuromorphic applications

Solution-based memristors are emergent devices, due to their potential in electrical performance for neuromorphic computing combined with simple and cheap fabrication processes. However, to achieve practical application in crossbar design tens to hundreds of uniform memristors are required. Regarding this, the production step optimization should be considered as the main objective to achieve high performance devices. In this work, solution-based indium gallium zinc oxide (IGZO) memristor devices are produced using a combustion synthesis process. The performance of the device is optimized by using different annealing temperatures and active layer thicknesses to reach a higher reproducibility and stability. All IGZO memristors show a low operating voltage, good endurance, and retention up to 10⁵ s under air conditions. The optimized devices can be programmed in a multi-level cell operation mode, with 8 different resistive states. Also, preliminary results reveal synaptic behavior by replicating the plasticity of a synaptic junction through potentiation and depression; this is a significant step towards low-cost processes and large-scale compatibility of neuromorphic computing systems.

Mnemonic-opto-synaptic transistor for in-sensor vision system

A mnemonic-opto-synaptic transistor (MOST) that has triple functions is demonstrated for an in-sensor vision system. It memorizes a photoresponsivity that corresponds to a synaptic weight as a memory cell, senses light as a photodetector, and performs weight updates as a synapse for machine vision with an artificial neural network (ANN). Herein the memory function added to a previous photodetecting device combined with a photodetector and a synapse provides a technical breakthrough for realizing in-sensor processing that is able to perform image sensing and signal processing in a sensor. A charge trap layer (CTL) was intercalated to gate dielectrics of a vertical pillar-shaped transistor for the memory function. Weight memorized in the CTL makes photoresponsivity tunable for real-time multiplication of the image with a memorized photoresponsivity matrix. Therefore, these multi-faceted features can allow in-sensor processing without external memory for the in-sensor vision system. In particular, the in-sensor vision system can enhance speed and energy efficiency compared to a conventional vision system due to the simultaneous preprocessing of massive data at sensor nodes prior to ANN nodes. Recognition of a simple pattern was demonstrated with full sets of the fabricated MOSTs. Furthermore, recognition of complex hand-written digits in the MNIST database was also demonstrated with software simulations.

Electrolyte-Gated Vertical Synapse Array based on Van Der Waals Heterostructure for Parallel Computing

Recently, three-terminal synaptic devices, which separate read and write terminals, have attracted significant attention because they enable nondestructive read-out and parallel-access for updating synaptic weights. However, owing to their structural features, it is difficult to address the relatively high device density compared with two-terminal synaptic devices. In this study, a vertical synaptic device featuring remotely controllable weight updates via e-field-dependent movement of mobile ions in the ion-gel layer is developed. This synaptic device successfully demonstrates all essential synaptic characteristics, such as excitatory/inhibitory postsynaptic current (E/IPSC), paired-pulse facilitation (PPF), and long-term potentiation/depression (LTP/D) by electrical measurements, and exhibits competitive LTP/D characteristics with a dynamic range (G_max /G_min ) of 31.3, and asymmetry (AS) of 8.56. The stability of the LTP/D characteristics is also verified through repeated measurements over 50 cycles; the relative standard deviations (RSDs) of G_max /G_min and AS are calculated as 1.65% and 0.25%, respectively. These excellent synaptic properties enable a recognition rate of ≈99% in the training and inference tasks for acoustic and emotional information patterns. This study is expected to be an important foundation for the realization of future parallel computing networks for energy-efficient and high-speed data processing.

Artificial Neurons and Synapses Based on Al/a-SiNxOy:H/P+-Si Device with Tunable Resistive Switching from Threshold to Memory

As the building block of brain-inspired computing, resistive switching memory devices have recently attracted great interest due to their biological function to mimic synapses and neurons, which displays the memory switching or threshold switching characteristic. To make it possible for the Si-based artificial neurons and synapse to be integrated with the neuromorphic chip, the tunable threshold and memory switching characteristic is highly in demand for their perfect compatibility with the mature CMOS technology. We first report artificial neurons and synapses based on the Al/a-SiN_xO_y:H/P⁺-Si device with the tunable switching from threshold to memory can be realized by controlling the compliance current. It is found that volatile TS from Al/a-SiN_xO_y:H/P⁺-Si device under the lower compliance current is induced by the weak Si dangling bond conductive pathway, which originates from the broken Si-H bonds. While stable nonvolatile MS under the higher compliance current is attributed to the strong Si dangling bond conductive pathway, which is formed by the broken Si-H and Si-O bonds. Theoretical calculation reveals that the conduction mechanism of TS and MS agree with P-F model, space charge limited current model and Ohm’s law, respectively. The tunable TS and MS characteristic of Al/a-SiN_xO_y:H/P⁺-Si device can be successfully employed to mimic the biological behavior of neurons and synapse including the integrate-and-fire function, paired-pulse facilitation, long-term potentiation and long-term depression as well as spike-timing-dependent plasticity. Our discovery supplies an effective way to construct the neuromorphic devices for brain-inspired computing in the AI period.

Research Progress of Biomimetic Memristor Flexible Synapse

With the development of the Internet of things, artificial intelligence, and wearable devices, massive amounts of data are generated and need to be processed. High standards are required to store and analyze this information. In the face of the explosive growth of information, the memory used in data storage and processing faces great challenges. Among many types of memories, memristors have received extensive attentions due to their low energy consumption, strong tolerance, simple structure, and strong miniaturization. However, they still face many problems, especially in the application of artificial bionic synapses, which call for higher requirements in the mechanical properties of the device. The progress of integrated circuit and micro-processing manufacturing technology has greatly promoted development of the flexible memristor. The use of a flexible memristor to simulate nerve synapses will provide new methods for neural network computing and bionic sensing systems. In this paper, the materials and structure of the flexible memristor are summarized and discussed, and the latest configuration and new materials are described. In addition, this paper will focus on its application in artificial bionic synapses and discuss the challenges and development direction of flexible memristors from this perspective.

Neuromorphic Dynamics at the Nanoscale in Silicon Suboxide RRAM

Resistive random-access memories, also known as memristors, whose resistance can be modulated by the electrically driven formation and disruption of conductive filaments within an insulator, are promising candidates for neuromorphic applications due to their scalability, low-power operation and diverse functional behaviors. However, understanding the dynamics of individual filaments, and the surrounding material, is challenging, owing to the typically very large cross-sectional areas of test devices relative to the nanometer scale of individual filaments. In the present work, conductive atomic force microscopy is used to study the evolution of conductivity at the nanoscale in a fully CMOS-compatible silicon suboxide thin film. Distinct filamentary plasticity and background conductivity enhancement are reported, suggesting that device behavior might be best described by composite core (filament) and shell (background conductivity) dynamics. Furthermore, constant current measurements demonstrate an interplay between filament formation and rupture, resulting in current-controlled voltage spiking in nanoscale regions, with an estimated optimal energy consumption of 25 attojoules per spike. This is very promising for extremely low-power neuromorphic computation and suggests that the dynamic behavior observed in larger devices should persist and improve as dimensions are scaled down.

Ionic Sieving Through One-Atom-Thick 2D Material Enables Analog Nonvolatile Memory for Neuromorphic Computing

The first report on ion transport through atomic sieves of atomically thin 2D material is provided to solve critical limitations of electrochemical random-access memory (ECRAM) devices. Conventional ECRAMs have random and localized ion migration paths; as a result, the analog switching efficiency is inadequate to perform in-memory logic operations. Herein ion transport path scaled down to the one-atom-thick (≈0.33 nm) hexagonal boron nitride (hBN), and the ionic transport area is confined to a small pore (≈0.3 nm² ) at the single-hexagonal ring. One-atom-thick hBN has ion-permeable pores at the center of each hexagonal ring due to weakened electron cloud and highly polarized B-N bond. The experimental evidence indicates that the activation energy barrier for H⁺ ion transport through single-layer hBN is ≈0.51 eV. Benefiting from the controlled ionic sieving through single-layer hBN, the ECRAMs exhibit superior nonvolatile analog switching with good memory retention and high endurance. The proposed approach enables atomically thin 2D material as an ion transport layer to regulate the switching of various ECRAM devices for artificial synaptic electronics.

Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array

As one of the most promising embedded non-volatile storage solutions for advanced CMOS modules, resistive random access memory's (RRAM) applications depend highly on its cyclability. Through detailed analysis, links have been found between noise types, filament configurations and the occurrence of reset failure during cycling test. In addition, a recovery treatment is demonstrated to restore the cyclability of RRAM. An early detection circuit for vulnerable cells in an array is also proposed for further improving the overall endurance of an RRAM array. Lifetime of RRAM can be extended to over 10 k cycles without fail bits in an array.

Improved synaptic functionalities of Li-based nano-ionic synaptic transistor with ultralow conductance enabled by Al2O3barrier layer

In this study, we investigated the effect of an Al₂O₃barrier layer in an all-solid-state inorganic Li-based nano-ionic synaptic transistor (LST) with Li₃PO₄electrolyte/WO_xchannel structure. Near-ideal synaptic behavior in the ultralow conductance range (∼50 nS) was obtained by controlling the abrupt ion migration through the introduction of a sputter-deposited thin (∼3 nm) Al₂O₃interfacial layer. A trade-off relationship between the weight update linearity and on/off ratio with varying Al₂O₃layer thickness was also observed. To determine the origin of the Al₂O₃barrier layer effects, cyclic voltammetry analysis was conducted, and the optimal ionic diffusivity and mobility were found to be key parameters in achieving ideal synaptic behavior. Owing to the controlled ion migration, the retention characteristics were considerably improved by the Al₂O₃barrier. Finally, a highly improved pattern recognition accuracy (83.13%) was achieved using the LST with an Al₂O₃barrier of optimal thickness.

Optically tunable ultra-fast resistive switching in lead-free methyl-ammonium bismuth iodide perovskite films

Resistive RAMs (Re-RAMs) have come to the fore as a rising star among the next generation non-volatile memories with fast operational speed, excellent endurance and prolonged data retention capabilities. Re-RAMs are being profusely used as storage and processing modules in neuromorphic hardware and high frequency switches in radio-frequency (RF) circuits. Owing to its intrinsic hysteresis and abundance of charge migration pathways, lead halide perovskites have emerged as a promising switching medium in Re-RAMs besides their ubiquitous usage in optoelectronic devices. Here, we adopted a lead-free eco-friendly methyl-ammonium bismuth iodide (MA₃Bi₂I₉) perovskite (prepared by solvent-free engineering) as the switching medium sandwiched between copper (Cu) and indium doped tin oxide (ITO) electrodes. The devices exhibited a 10⁴ high ON/OFF ratio that provided a large window for the multi-bit data storage in a single cell with good accuracy. Robust endurance of 1730 cycles and good data retention ability of >3 × 10⁵ s were also observed. Careful switching speed measurements showed the devices can operate with an ultra-fast speed of 10 ns for writing and erasing respectively. The devices responded to light illumination and the prolonged retention of the opto-electrically tuned resistance states paved the way for image memorization.

Learning to Approximate Functions Using Nb-Doped SrTiO3 Memristors

Memristors have attracted interest as neuromorphic computation elements because they show promise in enabling efficient hardware implementations of artificial neurons and synapses. We performed measurements on interface-type memristors to validate their use in neuromorphic hardware. Specifically, we utilized Nb-doped SrTiO3 memristors as synapses in a simulated neural network by arranging them into differential synaptic pairs, with the weight of the connection given by the difference in normalized conductance values between the two paired memristors. This network learned to represent functions through a training process based on a novel supervised learning algorithm, during which discrete voltage pulses were applied to one of the two memristors in each pair. To simulate the fact that both the initial state of the physical memristive devices and the impact of each voltage pulse are unknown we injected noise into the simulation. Nevertheless, discrete updates based on local knowledge were shown to result in robust learning performance. Using this class of memristive devices as the synaptic weight element in a spiking neural network yields, to our knowledge, one of the first models of this kind, capable of learning to be a universal function approximator, and strongly suggests the suitability of these memristors for usage in future computing platforms.

Growth and Interlayer Engineering of 2D Layered Semiconductors for Future Electronics

Layered materials that do not form a covalent bond in a vertical direction can be prepared in a few atoms to one atom thickness without dangling bonds. This distinctive characteristic of limiting thickness around the sub-nanometer level allowed scientists to explore various physical phenomena in the quantum realm. In addition to the contribution to fundamental science, various applications were proposed. Representatively, they were suggested as a promising material for future electronics. This is because (i) the dangling-bond-free nature inhibits surface scattering, thus carrier mobility can be maintained at sub-nanometer range; (ii) the ultrathin nature allows the short-channel effect to be overcome. In order to establish fundamental discoveries and utilize them in practical applications, appropriate preparation methods are required. On the other hand, adjusting properties to fit the desired application properly is another critical issue. Hence, in this review, we first describe the preparation method of layered materials. Proper growth techniques for target applications and the growth of emerging materials at the beginning stage will be extensively discussed. In addition, we suggest interlayer engineering via intercalation as a method for the development of artificial crystal. Since infinite combinations of the host-intercalant combination are possible, it is expected to expand the material system from the current compound system. Finally, inevitable factors that layered materials must face to be used as electronic applications will be introduced with possible solutions. Emerging electronic devices realized by layered materials are also discussed.

From Memristive Materials to Neural Networks

The information technologies have been increasing exponentially following Moore's law over the past decades. This has fundamentally changed the ways of work and life. However, further improving data process efficiency is facing great challenges because of physical and architectural limitations. More powerful computational methodologies are crucial to fulfill the technology gap in the post-Moore's law period. The memristor exhibits promising prospects in information storage, high-performance computing, and artificial intelligence. Since the memristor was theoretically predicted by L. O. Chua in 1971 and experimentally confirmed by HP Laboratories in 2008, it has attracted great attention from worldwide researchers. The intrinsic properties of memristors, such as simple structure, low power consumption, compatibility with the complementary metal oxide-semiconductor (CMOS) process, and dual functionalities of the data storage and computation, demonstrate great prospects in many applications. In this review, we cover the memristor-relevant computing technologies, from basic materials to in-memory computing and future prospects. First, the materials and mechanisms in the memristor are discussed. Then, we present the development of the memristor in the domains of the synapse simulating, in-memory logic computing, deep neural networks (DNNs) and spiking neural networks (SNNs). Finally, the existent technology challenges and outlook of the state-of-art applications are proposed.

Curved neuromorphic image sensor array using a MoS2-organic heterostructure inspired by the human visual recognition system

Conventional imaging and recognition systems require an extensive amount of data storage, pre-processing, and chip-to-chip communications as well as aberration-proof light focusing with multiple lenses for recognizing an object from massive optical inputs. This is because separate chips (i.e., flat image sensor array, memory device, and CPU) in conjunction with complicated optics should capture, store, and process massive image information independently. In contrast, human vision employs a highly efficient imaging and recognition process. Here, inspired by the human visual recognition system, we present a novel imaging device for efficient image acquisition and data pre-processing by conferring the neuromorphic data processing function on a curved image sensor array. The curved neuromorphic image sensor array is based on a heterostructure of MoS₂ and poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane). The curved neuromorphic image sensor array features photon-triggered synaptic plasticity owing to its quasi-linear time-dependent photocurrent generation and prolonged photocurrent decay, originated from charge trapping in the MoS₂-organic vertical stack. The curved neuromorphic image sensor array integrated with a plano-convex lens derives a pre-processed image from a set of noisy optical inputs without redundant data storage, processing, and communications as well as without complex optics. The proposed imaging device can substantially improve efficiency of the image acquisition and recognition process, a step forward to the next generation machine vision.

Designing efficient bio-inspired visual recognition system remains a challenge. Here the authors present a curved neuromorphic image sensor array based on a heterostructure of MoS2 and pV3D3 integrated with a plano-convex lens for efficient image acquisition and data pre-processing.

Filament-Free Bulk Resistive Memory Enables Deterministic Analogue Switching

Digital computing is nearing its physical limits as computing needs and energy consumption rapidly increase. Analogue-memory-based neuromorphic computing can be orders of magnitude more energy efficient at data-intensive tasks like deep neural networks, but has been limited by the inaccurate and unpredictable switching of analogue resistive memory. Filamentary resistive random access memory (RRAM) suffers from stochastic switching due to the random kinetic motion of discrete defects in the nanometer-sized filament. In this work, this stochasticity is overcome by incorporating a solid electrolyte interlayer, in this case, yttria-stabilized zirconia (YSZ), toward eliminating filaments. Filament-free, bulk-RRAM cells instead store analogue states using the bulk point defect concentration, yielding predictable switching because the statistical ensemble behavior of oxygen vacancy defects is deterministic even when individual defects are stochastic. Both experiments and modeling show bulk-RRAM devices using TiO_{2- X} switching layers and YSZ electrolytes yield deterministic and linear analogue switching for efficient inference and training. Bulk-RRAM solves many outstanding issues with memristor unpredictability that have inhibited commercialization, and can, therefore, enable unprecedented new applications for energy-efficient neuromorphic computing. Beyond RRAM, this work shows how harnessing bulk point defects in ionic materials can be used to engineer deterministic nanoelectronic materials and devices.

Multi-Level Analog Resistive Switching Characteristics in Tri-Layer HfO2/Al2O3/HfO2 Based Memristor on ITO Electrode

Atomic layer deposited (ALD) HfO2/Al2O3/HfO2 tri-layer resistive random access memory (RRAM) structure has been studied with a transparent indium tin oxide (ITO) transparent electrode. Highly stable and reliable multilevel conductance can be controlled by the set current compliance and reset stop voltage in bipolar resistive switching. Improved gradual resistive switching was achieved because of the interdiffusion in the HfO2/Al2O3 interface where tri-valent Al incorporates with HfO2 and produces HfAlO. The uniformity in bipolar resistive switching with Ion/Ioff ratio (>10) and excellent endurance up to >103 cycles was achieved. Multilevel conductance levels in potentiation/depression were realized with constant amplitude pulse train and increasing pulse amplitude. Thus, tri-layer structure-based RRAM can be a potential candidate for the synaptic device in neuromorphic computing.

Enhancing Short-Term Plasticity by Inserting a Thin TiO2 Layer in WOx-Based Resistive Switching Memory

In this work, we emulate biological synaptic properties such as long-term plasticity (LTP) and short-term plasticity (STP) in an artificial synaptic device with a TiN/TiO2/WOx/Pt structure. The graded WOx layer with oxygen vacancies is confirmed via X-ray photoelectron spectroscopy (XPS) analysis. The control TiN/WOx/Pt device shows filamentary switching with abrupt set and gradual reset processes in DC sweep mode. The TiN/WOx/Pt device is vulnerable to set stuck because of negative set behavior, as verified by both DC sweep and pulse modes. The TiN/WOx/Pt device has good retention and can mimic long-term memory (LTM), including potentiation and depression, given repeated pulses. On the other hand, TiN/TiO2/WOx/Pt devices show non-filamentary type switching that is suitable for fine conductance modulation. Potentiation and depression are demonstrated in the TiN/TiO2 (2 nm)/WOx/Pt device with moderate conductance decay by application of identical repeated pulses. Short-term memory (STM) is demonstrated by varying the interval time of pulse inputs for the TiN/TiO2 (6 nm)/WOx/Pt device with a quick decay in conductance.

Vertical organic synapse expandable to 3D crossbar array

Recently, three-terminal synaptic devices have attracted considerable attention owing to their nondestructive weight-update behavior, which is attributed to the completely separated terminals for reading and writing. However, the structural limitations of these devices, such as a low array density and complex line design, are predicted to result in low processing speeds and high energy consumption of the entire system. Here, we propose a vertical three-terminal synapse featuring a remote weight update via ion gel, which is also extendable to a crossbar array structure. This synaptic device exhibits excellent synaptic characteristics, which are achieved via precise control of ion penetration onto the vertical channel through the weight-control terminal. Especially, the applicability of the developed vertical organic synapse array to neuromorphic computing is demonstrated using a simple crossbar synapse array. The proposed synaptic device technology is expected to be an important steppingstone to the development of high-performance and high-density neural networks.

Memory technology-a primer for material scientists

From our own experience, we know that there is a gap to bridge between the scientists focused on basic material research and their counterparts in a close-to-application community focused on identifying and solving final technological and engineering challenges. In this review, we try to provide an easy-to-grasp introduction to the field of memory technology for materials scientists. An understanding of the big picture is vital, so we first provide an overview of the development and architecture of memories as part of a computer and call attention to some basic limitations that all memories are subject to. As any new technology has to compete with mature existing solutions on the market, today's mainstream memories are explained, and the need for future solutions is highlighted. The most prominent contenders in the field of emerging memories are introduced and major challenges on their way to commercialization are elucidated. Based on these discussions, we derive some predictions for the memory market to conclude the paper.