Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor

Modeling and Analysis of Environmental Electromagnetic Interference in Multiple-Channel Neural Recording Systems for High Common-Mode Interference Rejection Performance

Environmental electromagnetic interference (EMI) has always been a major interference source for multiple-channel neural recording systems, and little theoretical work has been attempted to address it. In this paper, equivalent circuit models are proposed to model both electromagnetic interference sources and neural signals in such systems, and analysis has been performed to generate the design guidelines for neural probes and the subsequent recording circuit towards higher common-mode interference (CMI) rejection performance while maintaining the recorded neural action potential (AP) signal quality. In vivo animal experiments with a configurable 32-channel neural recording system are carried out to validate the proposed models and design guidelines. The results show the power spectral density (PSD) of environmental 50 Hz EMI interference is reduced by three orders from 4.43 × 10-3 V2/Hz to 4.04 × 10-6 V2/Hz without affecting the recorded AP signal quality in an unshielded experiment environment.

A Fully Differential Analog Front-End for Signal Processing from EMG Sensor in 28 nm FDSOI Technology

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 GΩ with a chip area of 0.09 mm2.

Light Modulation of Brain and Development of Relevant Equipment

Light modulation plays an important role in understanding the pathology of brain disorders and improving brain function. Optogenetic techniques can activate or silence targeted neurons with high temporal and spatial accuracy and provide precise control, and have recently become a method for quick manipulation of genetically identified types of neurons. Photobiomodulation (PBM) is light therapy that utilizes non-ionizing light sources, including lasers, light emitting diodes, or broadband light. It provides a safe means of modulating brain activity without any irreversible damage and has established optimal treatment parameters in clinical practice. This manuscript reviews 1) how optogenetic approaches have been used to dissect neural circuits in animal models of Alzheimer's disease, Parkinson's disease, and depression, and 2) how low level transcranial lasers and LED stimulation in humans improves brain activity patterns in these diseases. State-of-the-art brain machine interfaces that can record neural activity and stimulate neurons with light have good prospects in the future.

A Review of Microelectronic Systems and Circuit Techniques for Electrical Neural Recording Aimed at Closed-Loop Epilepsy Control

Closed-loop implantable electronics offer a new trend in therapeutic systems aimed at controlling some neurological diseases such as epilepsy. Seizures are detected and electrical stimulation applied to the brain or groups of nerves. To this aim, the signal recording chain must be very carefully designed so as to operate in low-power and low-latency, while enhancing the probability of correct event detection. This paper reviews the electrical characteristics of the target brain signals pertaining to epilepsy detection. Commercial systems are presented and discussed. Finally, the major blocks of the signal acquisition chain are presented with a focus on the circuit architecture and a careful attention to solutions to issues related to data acquisition from multi-channel arrays of cortical sensors.

A Power Efficient Low-noise and High Swing CMOS Amplifier for Neural Recording Applications

In this paper, a power efficient, low-noise and high swing capacitively-coupled amplifier (CCA) for neural recording applications is proposed. The use of current splitting technique and current scaling technique in a current mirror operational transconductance amplifier (CM-OTA) has lead to a very good trade-off between power and noise. The presented architecture is simple, without cascode transistor while it has more than 80 dB open-loop gain without extra power consumption. As a result, the proposed structure has a better power efficiency factor (PEF) and output swing in comparison with previous reported architectures is increased to the 2Vov below the maximum supply voltage. In order to reduce flicker noise and achieve better trade-off between the power and noise, PMOS transistors with an optimum size have been utilized which operate in sub-threshold region. The amplifier is designed and simulated in a commercially available 0.18 μm CMOS technology. Monte Carlo simulations for process and mismatch have been carried out. The gain of the proposed amplifier is 39.22 dB in its bandwidth (3 Hz - 5 kHz). Total input-referred noise is 3.03 μVrms over 1 Hz - 10 kHz. The power consumption of the amplifier is 2.98 μW at supply voltage of 1.4 V. The noise efficiency factor (NEF) and PEF are 2.4 and 8.06, respectively. The output swing is about 1.16 V. It means the proposed amplifier can tolerate up to 13.2 mV peak-to-peak input signal while its total harmonic distortion (THD) is less than 1%.

Merging brain-computer interface and functional electrical stimulation technologies for movement restoration

BCI (brain-computer interface) and functional electrical stimulation (FES) technologies have advanced significantly over the last several decades. Recent efforts have involved the integration of these technologies with the goal of restoring functional movement in paralyzed patients. Implantable BCIs have provided neural recordings with increased spatial resolution and have been combined with sophisticated neural decoding algorithms and increasingly capable FES systems to advance efforts toward this goal. This chapter reviews historical developments that have occurred as the exciting fields of BCI and FES have evolved and now overlapped to allow new breakthroughs in medicine, targeting restoration of movement and lost function in users with disabilities.

Telemetry-controlled simultaneous stimulation-and-recording device (SRD) to study interhemispheric cortical circuits in rat primary somatosensory (SI) cortex

Background

A growing need exists for neuroscience platforms that can perform simultaneous chronic recording and stimulation of neural tissue in animal models in a telemetry-controlled fashion with signal processing for analysis of the chronic recording data and external triggering capability. We describe the system design, testing, evaluation, and implementation of a wireless simultaneous stimulation-and-recording device (SRD) for modulating cortical circuits in physiologically identified sites in primary somatosensory (SI) cortex in awake-behaving and freely-moving rats. The SRD was developed using low-cost electronic components and open-source software. The function of the SRD was assessed by bench and in-vivo testing.

Results

The SRD recorded spontaneous spiking and bursting neuronal activity, evoked responses to programmed intracortical microstimulation (ICMS) delivered internally by the SRD, and evoked responses to external peripheral forelimb stimulation.

Conclusions

The SRD is capable of wireless stimulation and recording on a predetermined schedule or can be wirelessly synchronized with external input as would be required in behavioral testing prior to, during, and following ICMS.

A 400 GΩ Input-Impedance Active Electrode for Non-Contact Capacitively Coupled ECG Acquisition With Large Linear-Input-Range and High CM-Interference-Tolerance

Electrocardiogram (ECG) is one of the major physiological vital signs and an effective monitoring method for patients with cardiovascular diseases. However, existing ECG recordings require a galvanic body contact, which is unpractical in daily life. This paper presents the design of an ECG chip that facilitates non-contact ECG recording through capacitive coupling. With the input impedance boosting techniques, as well as an active driven-right-leg (DRL) which boosts common-mode rejection ratio to 70 dB, the single-ended capacitive feedback active electrode (AE) achieves ultra-high input impedance of 400 GΩ (< 0.5 Hz), a large common-mode interference tolerance (2.8 V_PP), and a high linear-input-range (220 m V_PP). Implemented in 0.18 μm 5V CMOS process, the prototype occupies an area of 1.23 mm², and consumes 18 μA and 13 μA for the AE and DRL, respectively. Real life non-contact capacitively coupled ECG acquisition has been demonstrated, obtaining ECG waves and heart rate in the presence of motion artifacts as well as ambient interference.

A Low-Power Current-Reuse Analog Front-End for High-Density Neural Recording Implants

Studying brain activity in vivo requires collecting bioelectrical signals from several microelectrodes simultaneously in order to capture neuron interactions. In this work, we present a new current-reuse analog front-end (AFE), which is scalable to very large numbers of recording channels, thanks to its small implementation silicon area and its low-power consumption. This current-reuse AFE, which is including a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), employs a new fully differential current-mirror topology using fewer transistors, and improving several design parameters, such as power consumption and noise, over previous current-reuse amplifier circuit implementations. We show that the proposed current-reuse amplifier can provide a theoretical noise efficiency factor (NEF) as low as 1.01, which is the lowest reported theoretical NEF provided by an LNA topology. A foue-channel current-reuse AFE implemented in a CMOS 0.18-μm technology is presented as a proof-of-concept. T-network capacitive circuits are used to decrease the size of input capacitors and to increase the gain accuracy in the AFE. The measured performance of the whole AFE is presented. The total power consumption per channel, including the LNA and the PGA stage, is 9 μW (4.5 μW for LNA and 4.5 μW for PGA), for an input referred noise of 3.2 μV_rms, achieving a measured NEF of 1.94. The entire AFE presents three selectable gains of 35.04, 43.1, and 49.5 dB, and occupies a die area of 0.072 mm² per channel. The implemented circuit has a measured inter-channel rejection ratio of 54 dB. In vivo recording results obtained with the proposed AFE are reported. It successfully allows collecting low-amplitude extracellular action potential signals from a tungsten wire microelectrode implanted in the hippocampus of a laboratory mouse.

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation

OBJECTIVE

The ability to record and to control action potential firing in neuronal circuits is critical to understand how the brain functions. The objective of this study is to develop a monolithic integrated circuit (IC) to record action potentials and simultaneously control action potential firing using optogenetics.

METHODS

A low-noise and high input impedance (or low input capacitance) neural recording amplifier is combined with a high current laser/light-emitting diode (LED) driver in a single IC.

RESULTS

The low input capacitance of the amplifier (9.7 pF) was achieved by adding a dedicated unity gain stage optimized for high impedance metal electrodes. The input referred noise of the amplifier is [Formula: see text], which is lower than the estimated thermal noise of the metal electrode. Thus, the action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of at least 6.6. The LED/laser current driver delivers a maximum current of 330 mA, which is adequate for optogenetic control. The functionality of the IC was tested with an anesthetized Mongolian gerbil and auditory stimulated action potentials were recorded from the inferior colliculus. Spontaneous firings of fifth (trigeminal) nerve fibers were also inhibited using the optogenetic protein Halorhodopsin. Moreover, a noise model of the system was derived to guide the design.

SIGNIFICANCE

A single IC to measure and control action potentials using optogenetic proteins is realized so that more complicated behavioral neuroscience research and the translational neural disorder treatments become possible in the future.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

A Low Noise Amplifier for Neural Spike Recording Interfaces

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.

A new architecture for neural signal amplification in implantable brain machine interfaces

This paper reports a new architecture for variable gain-bandwidth amplification of neural signals to be used in implantable multi-channel recording systems. The two most critical requirements in such a front-end circuit are low power consumption and chip area, especially as number of channels increases. The presented architecture employs a single super-performing amplifier, with tunable gain and bandwidth, combined with several low-key preamplifiers and multiplexors for multi-channel recordings. This is in contrast to using copies of high performing amplifier for each channel as is typically reported in earlier literature. The resulting circuits consume lower power and require smaller area as compared to existing designs. Designed in 0.5 µmCMOS, the 8-channel prototype can simultaneously record Local Field Potentials and neural spikes, with an effective power consumption of 3.5 µW per channel and net core area of 0.407 mm(2).

A compact and autoclavable system for acute extracellular neural recording and brain pressure monitoring for humans

One of the most difficult tasks for the surgeon during the removal of low-grade gliomas is to identify as precisely as possible the borders between functional and non-functional brain tissue with the aim of obtaining the maximal possible resection which allows to the patient the longer survival. For this purpose, systems for acute extracellular recordings of single neuron and multi-unit activity are considered promising. Here we describe a system to be used with 16 microelectrodes arrays that consists of an autoclavable headstage, a built-in inserter for precise electrode positioning and a system that measures and controls the pressure exerted by the headstage on the brain with a twofold purpose: to increase recording stability and to avoid disturbance of local perfusion which would cause a degradation of the quality of the recording and, eventually, local ischemia. With respect to devices where only electrodes are autoclavable, our design permits the reduction of noise arising from long cable connections preserving at the same time the flexibility and avoiding long-lasting gas sterilization procedures. Finally, size is much smaller and set up time much shorter compared to commercial systems currently in use in surgery rooms, making it easy to consider our system very useful for intra-operatory mapping operations.

2.5D heterogeneously integrated microsystem for high-density neural sensing applications

Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with μ-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of μ-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 × 24 μ-probe array with embedded TSVs is fabricated on a 5×5 mm(2) chip and bonded on the back side of the interposer. Thus, each channel contains 6 × 6 μ -probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus ( μ-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 μW for 16-channel neural sensing.

Compact low-power cortical recording architecture for compressive multichannel data acquisition

This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 [Formula: see text]m CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 [Formula: see text]W of power within an effective area of 250 [Formula: see text]m × 250 [Formula: see text]m per channel.

A digitally assisted, signal folding neural recording amplifier

A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

Advances in Microelectronics for Implantable Medical Devices

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field.

Development of an ultra low noise, miniature signal conditioning device for vestibular evoked response recordings

BACKGROUND

Inner ear evoked potentials are small amplitude (<1 μVpk) signals that require a low noise signal acquisition protocol for successful extraction; an existing such technique is Electrocochleography (ECOG). A novel variant of ECOG called Electrovestibulography (EVestG) is currently investigated by our group, which captures vestibular responses to a whole body tilt. The objective is to design and implement a bio-signal amplifier optimized for ECOG and EVestG, which will be superior in noise performance compared to low noise, general purpose devices available commercially.

METHOD

A high gain configuration is required (>85 dB) for such small signal recordings; thus, background power line interference (PLI) can have adverse effects. Active electrode shielding and driven-right-leg circuitry optimized for EVestG/ECOG recordings were investigated for PLI suppression. A parallel pre-amplifier design approach was investigated to realize low voltage, and current noise figures for the bio-signal amplifier.

RESULTS

In comparison to the currently used device, PLI is significantly suppressed by the designed prototype (by >20 dB in specific test scenarios), and the prototype amplifier generated noise was measured to be 4.8 nV/Hz @ 1 kHz (0.45 μVRMS with bandwidth 10 Hz-10 kHz), which is lower than the currently used device generated noise of 7.8 nV/Hz @ 1 kHz (0.76 μVRMS). A low noise (<1 nV/Hz) radio frequency interference filter was realized to minimize noise contribution from the pre-amplifier, while maintaining the required bandwidth in high impedance measurements. Validation of the prototype device was conducted for actual ECOG recordings on humans that showed an increase (p < 0.05) of ~5 dB in Signal-to-Noise ratio (SNR), and for EVestG recordings using a synthetic ear model that showed a ~4% improvement (p < 0.01) over the currently used amplifier.

CONCLUSION

This paper presents the design and evaluation of an ultra-low noise and miniaturized bio-signal amplifier tailored for EVestG and ECOG. The increase in SNR for the implemented amplifier will reduce variability associated with bio-features extracted from such recordings; hence sensitivity and specificity measures associated with disease classification are expected to increase. Furthermore, immunity to PLI has enabled EVestG and ECOG recordings to be carried out in a non-shielded clinical environment.

A low-power current-reuse dual-band analog front-end for multi-channel neural signal recording

Thoroughly studying the brain activity of freely moving subjects requires miniature data acquisition systems to measure and wirelessly transmit neural signals in real time. In this application, it is mandatory to simultaneously record the bioelectrical activity of a large number of neurons to gain a better knowledge of brain functions. However, due to limitations in transferring the entire raw data to a remote base station, employing dedicated data reduction techniques to extract the relevant part of neural signals is critical to decrease the amount of data to transfer. In this work, we present a new dual-band neural amplifier to separate the neuronal spike signals (SPK) and the local field potential (LFP) simultaneously in the analog domain, immediately after the pre-amplification stage. By separating these two bands right after the pre-amplification stage, it is possible to process LFP and SPK separately. As a result, the required dynamic range of the entire channel, which is determined by the signal-to-noise ratio of the SPK signal of larger bandwidth, can be relaxed. In this design, a new current-reuse low-power low-noise amplifier and a new dual-band filter that separates SPK and LFP while saving capacitors and pseudo resistors. A four-channel dual-band (SPK, LFP) analog front-end capable of simultaneously separating SPK and LFP is implemented in a TSMC 0.18 μm technology. Simulation results present a total power consumption per channel of 3.1 μw for an input referred noise of 3.28 μV and a NEF for 2.07. The cutoff frequency of the LFP band is fc=280 Hz, and fL=725 Hz and fL=11.2 KHz for SPK, with 36 dB gain for LFP band 46 dB gain for SPK band.

A compact, low input capacitance neural recording amplifier

Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm(2). It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated.

Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization

The design of a high-density neural recording system targeting epilepsy monitoring is presented. Circuit challenges and techniques are discussed to optimize the amplifier topology and the included OTA. A new platform supporting active recording devices targeting wireless and high-resolution focus localization in epilepsy diagnosis is also proposed. The post-layout simulation results of an amplifier dedicated to this application are presented. The amplifier is designed in a UMC 0.18µm CMOS technology, has an NEF of 2.19 and occupies a silicon area of 0.038 mm(2), while consuming 5.8 µW from a 1.8-V supply.

Modeling of the cell-electrode interface noise for microelectrode arrays

Microelectrodes are widely used in the physiological recording of cell field potentials. As microelectrode signals are generally in the μV range, characteristics of the cell-electrode interface are important to the recording accuracy. Although the impedance of the microelectrode-solution interface has been well studied and modeled in the past, no effective model has been experimentally verified to estimate the noise of the cell-electrode interface. Also in existing interface models, spectral information is largely disregarded. In this work, we developed a model for estimating the noise of the cell-electrode interface from interface impedances. This model improves over existing noise models by including the cell membrane capacitor and frequency dependent impedances. With low-noise experiment setups, this model is verified by microelectrode array (MEA) experiments with mouse muscle myoblast cells. Experiments show that the noise estimated from this model has <;10% error, which is much less than estimations from existing models. With this model, noise of the cell-electrode interface can be estimated by simply measuring interface impedances. This model also provides insights for micro- electrode design to achieve good recording signal-to-noise ratio.

A 0.09 μW low power front-end biopotential amplifier for biosignal recording

This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm². With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09μW, respectively.

A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

A low-power programmable neural spike detection channel with embedded calibration and data compression

This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.