A low-power configurable neural recording system for epileptic seizure detection

Methods for Lowering the Power Consumption of OS-Based Adaptive Deep Brain Stimulation Controllers

The identification of a new generation of adaptive strategies for deep brain stimulation (DBS) will require the development of mixed hardware-software systems for testing and implementing such controllers clinically. Towards this aim, introducing an operating system (OS) that provides high-level features (multitasking, hardware abstraction, and dynamic operation) as the core element of adaptive deep brain stimulation (aDBS) controllers could expand the capabilities and development speed of new control strategies. However, such software frameworks also introduce substantial power consumption overhead that could render this solution unfeasible for implantable devices. To address this, in this work four techniques to reduce this overhead are proposed and evaluated: a tick-less idle operation mode, reduced and dynamic sampling, buffered read mode, and duty cycling. A dual threshold adaptive deep brain stimulation algorithm for suppressing pathological oscillatory neural activity was implemented along with the proposed energy saving techniques on an energy-efficient OS, YetiOS, running on a STM32L476RE microcontroller. The system was then tested using an emulation environment coupled to a mean field model of the parkinsonian basal ganglia to simulate local field potential (LFPs) which acted as a biomarker for the controller. The OS-based controller alone introduced a power consumption overhead of 10.03 mW for a sampling rate of 1 kHz. This was reduced to 12 μW by applying the proposed tick-less idle mode, dynamic sampling, buffered read and duty cycling techniques. The OS-based controller using the proposed methods can facilitate rapid and flexible testing and implementation of new control methods. Furthermore, the approach has the potential to become a central element in future implantable devices to enable energy-efficient implementation of a wide range of control algorithms across different neurological conditions and hardware platforms.

Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces

This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13 [Formula: see text] CMOS process. To reduce thermal noise folding ratio, and suppress kT/C noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress kT/C noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and In-Vivo experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8 [Formula: see text] from 1 [Formula: see text] to 300 [Formula: see text], and 2.3 [Formula: see text] from 300 [Formula: see text] to 8 kHz respectively, and In-Vivo experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20 [Formula: see text]. In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.

The Complex Adaptive Delta-Modulator in Sliding Mode Theory

In this paper, we consider the stability and various dynamical behaviors of both discrete-time delta modulator (Δ-M) and adaptive Δ-M. The stability constraints and conditions of Δ-M and adaptive Δ-M are derived following the theory of quasi-sliding mode. Furthermore, the periodic behaviors are explored for both the systems with steady-state inputs and certain parameter values. The results derived in this paper are validated using simulated examples which confirms the derived stability conditions and the existence of periodicity.

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, low-power Delta-Sigma analog-to-digital converter (ADC) and a real-time spike processor based on one exponential component-polynomial component (EC-PC) algorithm. High-precision data conversion with low power consumption and small chip area is achieved by employing several techniques, such as opamp-sharing, multi-bit successive approximation (SAR) quantizer, two-step summation, and ultra-low distortion data weighted averaging (DWA). The on-chip EC-PC engine enables low latency, automatic detection, and extraction of spiking activities, thus supporting closed-loop control, real-time data compression and /or neural information decoding. The prototype chip was fabricated in a 0.13  μm CMOS process and verified in both bench-top and In-Vivo experiments. Bench-top measurement results indicate the designed ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 91.8 dB and a dynamic range of 93.0 dB over a 10 kHz bandwidth, where the total power consumption of the modulator is only 20  μW at 1.0 V supply, corresponding to a figure-of-merit (FOM) of 31.4fJ /conversion-step. In In-Vivo experiments, the proposed DAQ system has been demonstrated to obtain high-quality neural activities from a rat's motor cortex and also greatly reduce recovery time from system saturation due to electrical microstimulation.

Multi-Channel Neural Recording Implants: A Review

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain-machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

Discrimination of EMG Signals Using a Neuromorphic Implementation of a Spiking Neural Network

An accurate description of muscular activity plays an important role in the clinical diagnosis and rehabilitation research. The electromyography (EMG) is the most used technique to make accurate descriptions of muscular activity. The EMG is associated with the electrical changes generated by the activity of the motor neurons. Typically, to decode the muscular activation during different movements, a large number of individual motor neurons are monitored simultaneously, producing large amounts of data to be transferred and processed by the computing devices. In this paper, we follow an alternative approach that can be deployed locally on the sensor side. We propose a neuromorphic implementation of a spiking neural network (SNN) to extract spatio-temporal information of EMG signals locally and classify hand gestures with very low power consumption. We present experimental results on the input data stream using a mixed-signal analog/digital neuromorphic processor. We performed a thorough investigation on the performance of the SNN implemented on the chip, by: first, calculating PCA on the activity of the silicon neurons at the input and the hidden layers to show how the network helps in separating the samples of different classes; second, performing classification of the data using state-of-the-art SVM and logistic regression methods and a hardware-friendly spike-based read-out. The traditional algorithm achieved a classification rate of [Formula: see text] and [Formula: see text], respectively, and the spiking learning method achieved [Formula: see text]. The power consumption of the SNN is [Formula: see text], showing the potential of this approach for ultra-low power processing.

A Real-Time QRS Detection System With PR/RT Interval and ST Segment Measurements for Wearable ECG Sensors Using Parallel Delta Modulators

This paper presents a real-time electrocardiogram (ECG) monitoring system for wearable devices. The system is based on the proposed parallel delta modulator architecture with local maximum point and local minimum point algorithms to detect QRS and PT waves. Therefore, using the proposed system and algorithm, real-time PR and RT intervals, and ST segment measurements can be achieved in long-term wearable ECG recording. The algorithm is tested with the MIT-BIH Arrhythmia Database for QRS complex detection and with the QT Database for the P and T wave detections. The simulation result shows that the algorithm achieves above 99%, 91%, and 98% accuracy in the QRS complex, P wave, and T wave detections, respectively. Experimental results are presented from the system prototype, in which the parallel delta modulator circuits are fabricated in IBM 0.13 $\mu \text{m}$ standard CMOS technology and the algorithms are implemented in a Xilinx Spartan-6 field programmable gate array (FPGA). The parallel delta modulators consume 720 nW at 1 kHz sampling rate with $\pm$0.6 V power supply. The proposed system has the potential to be applied in future long-term wearable ECG recording devices.

Efficient Hardware Implementation of Real-Time Low-Power Movement Intention Detector System Using FFT and Adaptive Wavelet Transform

The brain-computer interfacing (BCI), a platform to extract features and classify different motor movement tasks from noisy and highly correlated electroencephalogram signals, is limited mostly by the complex and power-hungry algorithms. Among different techniques recently devised to tackle this issue, real-time onset detection, due to its negligible delay and minimal power overhead, is the most efficient one. Here, we propose a novel algorithm that outperforms the state-of-the-art design by sixfold in terms of speed, without sacrificing the accuracy for a real-time, hand movement intention detection based on the adaptive wavelet transform with only 1 s detection delay and maximum sensitivity of 88% and selectivity of 78% (only 7% loss of sensitivity).

A 1.83 μJ/Classification, 8-Channel, Patient-Specific Epileptic Seizure Classification SoC Using a Non-Linear Support Vector Machine

A non-linear support vector machine (NLSVM) seizure classification SoC with 8-channel EEG data acquisition and storage for epileptic patients is presented. The proposed SoC is the first work in literature that integrates a feature extraction (FE) engine, patient specific hardware-efficient NLSVM classification engine, 96 KB SRAM for EEG data storage and low-noise, high dynamic range readout circuits. To achieve on-chip integration of the NLSVM classification engine with minimum area and energy consumption, the FE engine utilizes time division multiplexing (TDM)-BPF architecture. The implemented log-linear Gaussian basis function (LL-GBF) NLSVM classifier exploits the linearization to achieve energy consumption of 0.39 μ J/operation and reduces the area by 28.2% compared to conventional GBF implementation. The readout circuits incorporate a chopper-stabilized DC servo loop to minimize the noise level elevation and achieve noise RTI of 0.81 μ Vrms for 0.5-100 Hz bandwidth with an NEF of 4.0. The 5 × 5 mm (2) SoC is implemented in a 0.18 μm 1P6M CMOS process consuming 1.83 μ J/classification for 8-channel operation. SoC verification has been done with the Children's Hospital Boston-MIT EEG database, as well as with a specific rapid eye-blink pattern detection test, which results in an average detection rate, average false alarm rate and latency of 95.1%, 0.94% (0.27 false alarms/hour) and 2 s, respectively.

A High Performance Delta-Sigma Modulator for Neurosensing

Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-μm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 μW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

A frequency shaping neural recorder with 3 pF input capacitance and 11 plus 4.5 bits dynamic range

This paper presents a frequency-shaping (FS) neural recording architecture and its implementation in a 0.13 μ m CMOS process. Compared with its conventional counterpart, the proposed architecture inherently rejects electrode offset, increases input impedance 5-10 fold, compresses neural data dynamic range (DR) by 4.5-bit, simultaneously records local field potentials (LFPs) and extracellular spikes, and is more suitable for long-term recording experiments. Measured at a 40 kHz sampling clock and ± 0.6 V supply, the recorder consumes 50 μW/ch, of which 22 μW per FS amplifier, 24 μ W per buffer, 4 μ W per 11-bit successive approximation register analog-to-digital converter (SAR ADC). The input-referred noise for LFPs and extracellular spikes are 13 μ Vrms and 7 μVrms, respectively, which are sufficient to achieve high-fidelity full-spectrum neural data. In addition, the designed recorder has a 3 pF input capacitance and allows " 11+4.5"-bit neural data DR without system saturation, where the extra 4.5-bit owes to the FS technique. Its figure-of-merit (FOM) based on data DR reaches 36.0 fJ/conversion-step.

A 0.45 V 100-channel neural-recording IC with sub- μW/channel consumption in 0.18 μm CMOS

Neural prosthetics and personal healthcare have increasing need of high channel density low noise low power neural sensor interfaces. The input referred noise and quantization resolution are two essential factors which prevent conventional neural sensor interfaces from simultaneously achieving a good noise efficiency factor and low power consumption. In this paper, a neural recording architecture with dynamic range folding and current reuse techniques is proposed and dedicated to solving the noise and dynamic range trade-off under low voltage low power operation. Measured results from the silicon prototype show that the proposed design achieves 3.2 μVrms input referred noise and 8.27 effective number of bits at only 0.45 V supply and 0.94 μW/channel power consumption.