Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation

A 16-Channel Low-Power Neural Connectivity Extraction and Phase-Locked Deep Brain Stimulation SoC

Growing evidence suggests that phase-locked deep brain stimulation (DBS) can effectively regulate abnormal brain connectivity in neurological and psychiatric disorders. This letter therefore presents a low-power SoC with both neural connectivity extraction and phase-locked DBS capabilities. A 16-channel low-noise analog front-end (AFE) records local field potentials (LFPs) from multiple brain regions with precise gain matching. A novel low-complexity phase estimator and neural connectivity processor subsequently enable energy-efficient, yet accurate measurement of the instantaneous phase and cross-regional synchrony measures. Through flexible combination of neural biomarkers such as phase synchrony and spectral energy, a four-channel charge-balanced neurostimulator is triggered to treat various pathological brain conditions. Fabricated in 65-nm CMOS, the SoC occupies a silicon area of 2.24 mm2 and consumes 60 μW, achieving over 60% power saving in neural connectivity extraction compared to the state-of-the-art. Extensive in-vivo measurements demonstrate multi-channel LFP recording, real-time extraction of phase and neural connectivity measures, and phase-locked stimulation in rats.

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode−tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

Brain functional and effective connectivity based on electroencephalography recordings: A review

Functional connectivity and effective connectivity of the human brain, representing statistical dependence and directed information flow between cortical regions, significantly contribute to the study of the intrinsic brain network and its functional mechanism. Many recent studies on electroencephalography (EEG) have been focusing on modeling and estimating brain connectivity due to increasing evidence that it can help better understand various brain neurological conditions. However, there is a lack of a comprehensive updated review on studies of EEG-based brain connectivity, particularly on visualization options and associated machine learning applications, aiming to translate those techniques into useful clinical tools. This article reviews EEG-based functional and effective connectivity studies undertaken over the last few years, in terms of estimation, visualization, and applications associated with machine learning classifiers. Methods are explored and discussed from various dimensions, such as either linear or nonlinear, parametric or nonparametric, time-based, and frequency-based or time-frequency-based. Then it is followed by a novel review of brain connectivity visualization methods, grouped by Heat Map, data statistics, and Head Map, aiming to explore the variation of connectivity across different brain regions. Finally, the current challenges of related research and a roadmap for future related research are presented.

EEG-Single-Channel Envelope Synchronisation and Classification for Seizure Detection and Prediction

This paper tackles the complex issue of detecting and classifying epileptic seizures whilst maintaining the total calculations at a minimum. Where many systems depend on the coupling between multiple sources, leading to hundreds of combinations of electrodes, our method calculates the instantaneous phase between non-identical upper and lower envelopes of a single-electroencephalography channel reducing the workload to the total number of electrode points. From over 600 h of simulations, our method shows a sensitivity and specificity of 100% for high false-positive rates and 83% and 75%, respectively, for moderate to low false positive rates, which compares well to both single- and multi-channel-based methods. Furthermore, pre-ictal variations in synchronisation were detected in over 90% of patients implying a possible prediction system.