Strong coupling between a microwave photon and a singlet-triplet qubit

Combining superconducting resonators and quantum dots has triggered tremendous progress in quantum information, however, attempts at coupling a resonator to even charge parity spin qubits have resulted only in weak spin-photon coupling. Here, we integrate a zincblende InAs nanowire double quantum dot with strong spin-orbit interaction in a magnetic-field resilient, high-quality resonator. The quantum confinement in the nanowire is achieved using deterministically grown wurtzite tunnel barriers. Our experiments on even charge parity states and at large magnetic fields, allow us to identify the relevant spin states and to measure the spin decoherence rates and spin-photon coupling strengths. We find an anti-crossing between the resonator mode in the single photon limit and a singlet-triplet qubit with a spin-photon coupling strength of g/2π = 139 ± 4 MHz. This coherent coupling exceeds the resonator decay rate κ/2π = 19.8 ± 0.2 MHz and the qubit dephasing rate γ/2π = 116 ± 7 MHz, putting our system in the strong coupling regime.

Ambipolar transport in narrow bandgap semiconductor InSb nanowires

We report on a transport measurement study of top-gated field effect transistors made out of InSb nanowires grown by chemical vapor deposition. The transistors exhibit ambipolar transport characteristics revealed by three distinguished gate-voltage regions: In the middle region where the Fermi level resides within the bandgap, the electrical resistance shows an exponential dependence on temperature and gate voltage. With either more positive or negative gate voltages, the devices enter the electron and hole transport regimes, revealed by the resistance decreasing linearly with decreasing temperature. From the transport measurement data of a 1 μm-long device made from a nanowire of 50 nm in diameter, we extracted a bandgap energy of 190-220 meV. The off-state current of this device is found to be suppressed within the measurement noise at a temperature of T = 4 K. A shorter, 260 nm-long device is found to exhibit a finite off-state current and a circumference-normalized on-state hole current of 11 μA μm^-1 at V_D = 50 mV which is the highest for such a device to our knowledge. The ambipolar transport characteristics make the InSb nanowires attractive for CMOS electronics, hybrid electron-hole quantum systems and hole based spin qubits.

Electrical control of spins and giant g-factors in ring-like coupled quantum dots

Emerging theoretical concepts for quantum technologies have driven a continuous search for structures where a quantum state, such as spin, can be manipulated efficiently. Central to many concepts is the ability to control a system by electric and magnetic fields, relying on strong spin-orbit interaction and a large g-factor. Here, we present a mechanism for spin and orbital manipulation using small electric and magnetic fields. By hybridizing specific quantum dot states at two points inside InAs nanowires, nearly perfect quantum rings form. Large and highly anisotropic effective g-factors are observed, explained by a strong orbital contribution. Importantly, we find that the orbital contributions can be efficiently quenched by simply detuning the individual quantum dot levels with an electric field. In this way, we demonstrate not only control of the effective g-factor from 80 to almost 0 for the same charge state, but also electrostatic change of the ground state spin.

Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs

Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (V_d = 10 mV) and current drive up to 40 μA/wire (V_d = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.

Formation of nanogaps in InAs nanowires by selectively etching embedded InP segments

We present a method to fabricate nanometer scale gaps within InAs nanowires by selectively etching InAs/InP heterostructure nanowires. We used vapor-liquid-solid grown InAs nanowires with embedded InP segments of 10-60 nm length and developed an etching recipe to selectively remove the InP segment. A photo-assisted wet etching process in a mixture of acetic acid and hydrobromic acid gave high selectivity, with accurate removal of InP segments down to 20 nm, leaving the InAs wire largely unattacked, as verified using scanning electron and transmission electron microscopy. The obtained nanogaps in InAs wires have potential as semiconducting electrodes to investigate electronic transport in nanoscale objects. We demonstrate this functionality by dielectrophoretically trapping 30 nm diameter gold nanoparticles into the gap.

Fully tunable, non-invasive thermal biasing of gated nanostructures suitable for low-temperature studies

There is much recent interest in the thermoelectric (TE) characterization of single nanostructures at low temperatures, because such measurements yield information that is complementary to traditional conductance measurements, and because they may lead to novel paradigms for TE energy conversion. However, previously reported techniques for thermal biasing of nanostructures are difficult to use at low temperatures because of unintended global device heating, the lack of ability to continuously tune the thermal bias, or limited compatibility with gating techniques. By placing a heater directly on top of the electrical contact to a single InAs nanowire, we demonstrate fully tunable thermal biases of up to several tens of Kelvin, combined with negligible overall heating of the device, and with full functionality of a back gate, in the temperature range between 4 K and 300 K.

Control and understanding of kink formation in InAs-InP heterostructure nanowires

Nanowire heterostructures are of special interest for band structure engineering due to an expanded range of defect-free material combinations. However, the higher degree of freedom in nanowire heterostructure growth comes at the expense of challenges related to nanowire-seed particle interactions, such as undesired composition, grading and kink formation. To better understand the mechanisms of kink formation in nanowires, we here present a detailed study of the dependence of heterostructure nanowire morphology on indium pressure, nanowire diameter, and nanowire density. We investigate InAs-InP-InAs heterostructure nanowires grown with chemical beam epitaxy, which is a material system that allows for very abrupt heterointerfaces. Our observations indicate that the critical parameter for kink formation is the availability of indium, and that the resulting morphology is also highly dependent on the length of the InP segment. It is shown that kinking is associated with the formation of an inclined facet at the interface between InP and InAs, which destabilizes the growth and leads to a change in growth direction. By careful tuning of the growth parameters, it is possible to entirely suppress the formation of this inclined facet and thereby kinking at the heterointerface. Our results also indicate the possibility of producing controllably kinked nanowires with a high yield.

The electrical and structural properties of n-type InAs nanowires grown from metal-organic precursors

The electrical and structural properties of 111B-oriented InAs nanowires grown using metal-organic precursors have been studied. On the basis of electrical measurements it was found that the trends in carbon incorporation are similar to those observed in the layer growth, where an increased As/In precursor ratio and growth temperature result in a decrease in carbon-related impurities. Our results also show that the effect of non-intentional carbon doping is weaker in InAs nanowires compared to bulk, which may be explained by lower carbon incorporation in the nanowire core. We determine that differences in crystal quality, here quantified as the stacking fault density, are not the primary cause for variations in resistivity of the material studied. The effects of some n-dopant precursors (S, Se, Si, Sn) on InAs nanowire morphology, crystal structure and resistivity were also investigated. All precursors result in n-doped nanowires, but high precursor flows of Si and Sn also lead to enhanced radial overgrowth. Use of the Se precursor increases the stacking fault density in wurtzite nanowires, ultimately at high flows leading to a zinc blende crystal structure with strong overgrowth and very low resistivity.

Time-resolved photoluminescence investigations on HfO2-capped InP nanowires

We have employed time-resolved photoluminescence (PL) spectroscopy to study the impact of HfO(2) surface capping by atomic layer deposition (ALD) on the optical properties of InP nanowires (NWs). The deposition of high-kappa dielectrics acting as a gate oxide is of particular interest in view of possible applications of semiconductor NWs in future wrap-gated field effect transistors (FETs). A high number of charged states at the NW-dielectrics interface can strongly degrade the performance of the FET which explains the strong interest in high quality deposition of high-kappa dielectrics. In the present work we show that time-resolved spectroscopy is a valuable and direct tool to monitor the surface quality of HfO(2)-capped InP NWs. In particular, we have studied the impact of ALD process parameters as well as surface treatment prior to the oxide capping on the NW-dielectrics interface quality. The best results in terms of the surface recombination velocity (S(0) = 9.5 x 10(3) cm s(-1)) were obtained for InP/GaP core/shell NWs in combination with a low temperature (100 degrees C) ALD process. While the present report focuses on the InP material system, our method of addressing the surface treatment for semiconductors with high-kappa dielectrics will also be applicable to nanoelectronic devices based on other III/V material systems such as InAs.

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.