Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

With the advancement of Moore's Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device's failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging.

Laboratory X-ray Microscopy of 3D Nanostructures in the Hard X-ray Regime Enabled by a Combination of Multilayer X-ray Optics

High-resolution imaging of buried metal interconnect structures in advanced microelectronic products with full-field X-ray microscopy is demonstrated in the hard X-ray regime, i.e., at photon energies > 10 keV. The combination of two multilayer optics-a side-by-side Montel (or nested Kirkpatrick-Baez) condenser optic and a high aspect-ratio multilayer Laue lens-results in an asymmetric optical path in the transmission X-ray microscope. This optics arrangement allows the imaging of 3D nanostructures in opaque objects at a photon energy of 24.2 keV (In-Kα X-ray line). Using a Siemens star test pattern with a minimal feature size of 150 nm, it was proven that features < 150 nm can be resolved. In-Kα radiation is generated from a Ga-In alloy target using a laboratory X-ray source that employs the liquid-metal-jet technology. Since the penetration depth of X-rays into the samples is significantly larger compared to 8 keV photons used in state-of-the-art laboratory X-ray microscopes (Cu-Kα radiation), 3D-nanopattered materials and structures can be imaged nondestructively in mm to cm thick samples. This means that destructive de-processing, thinning or cross-sectioning of the samples are not needed for the visualization of interconnect structures in microelectronic products manufactured using advanced packaging technologies. The application of laboratory transmission X-ray microscopy in the hard X-ray regime is demonstrated for Cu/Cu6Sn5/Cu microbump interconnects fabricated using solid-liquid interdiffusion (SLID) bonding.

A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

The ever-increasing demand for faster computing has led us to an era of heterogeneous integration, where interposers and package substrates have become essential components for further performance scaling. High-bandwidth connections are needed for faster communication between logic and memory dies. There are several limitations to current generation technologies, and dielectric buildup layers are a key part of addressing those issues. Although there are several polymer dielectrics available commercially, there are numerous challenges associated with incorporating them into interposers or package substrates. This article reviewed the properties of polymer dielectric materials currently available, their properties, and the challenges associated with their fabrication, electrical performance, mechanical reliability, and electrical reliability. The current state-of-the-art is discussed, and guidelines are provided for polymer dielectrics for the next-generation interposers.

Thermal, Mechanical, and Electrical Stability of Cu Films in an Integration Process with Photosensitive Polyimide (PSPI) Films

Photosensitive polyimides (PSPIs) have been widely developed in microelectronics, which is due to their excellent thermal properties and reasonable dielectric properties and can be directly patterned to simplify the processing steps. In this study, 3 μm~7 μm thick PSPI films were deposited on different substrates, including Si, 50 nm SiN, 50 nm SiO2, 100 nm Cu, and 100 nm Al, for the optimization of the process of integration with Cu films. In situ temperature-dependent resistance measurements were conducted by using a four-point probe system to study the changes in resistance of the 70 nm thick Cu films on different dielectrics with thick diffusion films of 30 nm Mn, Co, and W films in a N2 ambient. The lowest possible change in thickness due to annealing at the higher temperature ranges of 325 °C to 375 °C is displayed, which suggests the high stability of PSPI. The PSPI films show good adhesion with each Cu diffusion barrier up to 350 °C, and we believe that this will be helpful for new packaging applications, such as a 3D IC with a Cu interconnect.

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application

Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper-copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

Recrystallization and Grain Growth in Cu-Cu Joints under Electromigration at Low Temperatures

The behavior of recrystallization and grain growth was examined in Cu-Cu joints during electromigration at 150 °C. Recrystallization and grain growth were observed in all the joints after electromigration for 9000 h. Voiding was formed in Cu current-feeding lines and in bonding interfaces, and resistance increased with time due to the void formation. However, instead of rising abruptly, the resistance of certain Cu joints dropped after 7000 h. Microstructural analysis revealed that a large grain growth occurred in these joints at 150 °C, and the bonding interface was eliminated. Therefore, the electromigration lifetime can be prolonged for these joints.

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm², which was 27.51% shorter than 4.5 A/cm² at the same temperature difference. When the current density exceeded 4.5 A/cm², the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm²~4.5 A/cm².

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

The system-in-package (SiP) has gained much interest in the current rapid development of integrated circuits (ICs) due to its advantages of integration, shrinking, and high density. This review examined the SiP as its focus, provides a list of the most-recent SiP innovations based on market needs, and discusses how the SiP is used in various fields. Reliability issues must be resolved if the SiP is to operate normally. Three factors-thermal management, mechanical stress and electrical properties-can be paired with specific examples in order to detect and improve package reliability. This review provides a thorough overview of SiP technology, serves as a guide and foundation for the SiP in package reliability design, and addresses the challenges and potential for further development of this kind of package.

Fast Filling of Microvia by Pre-Settling Particles and Following Cu Electroplating

Microvia interconnectors are a critical element of 3D packaging technology, as they provide the shortest interconnection path between stacked chips. However, low efficiency of microvia filling is a long-standing problem. This study proposed a two-step method to enhance the electroplating filling efficiency by pre-setting metal particles in microvias and later electroplating the Cu to fill the gaps among the pre-settled particles. Since these particles occupy a certain volume in the microvia, less electroplating Cu is needed for microvia filling, leading to a shorter electroplating period.