Low-Temperature Growth of InGaAs Quantum Wells Using Migration-Enhanced Epitaxy

The growth of InGaAs quantum wells (QWs) epitaxially on InP substrates is of great interest due to their wide application in optoelectronic devices. However, conventional molecular beam epitaxy requires substrate temperatures between 400 and 500 °C, which can lead to disorder scattering, dopant diffusion, and interface roughening, adversely affecting device performance. Lower growth temperatures enable the fabrication of high-speed optoelectronic devices by increasing arsenic antisite defects and reducing carrier lifetimes. This work investigates the low-temperature epitaxial growth of InAs/GaAs short-period superlattices as an ordered replacement for InGaAs quantum wells, using migration-enhanced epitaxy (MEE) with low growth temperatures down to 200-250 °C. The InAs/GaAs multi-quantum wells with InAlAs barriers using MEE grown at 230 °C show good single crystals with sharp interfaces, without mismatch dislocations found. The Raman results reveal that the MEE mode enables the growth of (InAs)4(GaAs)3/InAlAs QWs with excellent periodicity, effectively reducing alloy scattering. The room temperature (RT) photoluminescence (PL) measurement shows the strong PL responses with narrow peaks, revealing the good quality of the MEE-grown QWs. The RT electron mobility of the sample grown in low-temperature MEE mode is as high as 2100 cm2/V∗s. In addition, the photoexcited band-edge carrier lifetime was about 3.3 ps at RT. The high-quality superlattices obtained confirm MEE's effectiveness for enabling advanced III-V device structures at reduced temperatures. This promises improved performance for applications in areas such as high-speed transistors, terahertz imaging, and optical communications.

Uncooled Mid-Infrared Sensing Enabled by Chip-Integrated Low-Temperature-Grown 2D PdTe2 Dirac Semimetal

Next-generation mid-infrared (MIR) imaging chips demand free-cooling capability and high-level integration. The rising two-dimensional (2D) semimetals with excellent infrared (IR) photoresponses are compliant with these requirements. However, challenges remain in scalable growth and substrate-dependence for on-chip integration. Here, we demonstrate the inch-level 2D palladium ditelluride (PdTe2) Dirac semimetal using a low-temperature self-stitched epitaxy (SSE) approach. The low formation energy between two precursors facilitates low-temperature multiple-point nucleation (∼300 °C), growing up, and merging, resulting in self-stitching of PdTe2 domains into a continuous film, which is highly compatible with back-end-of-line (BEOL) technology. The uncooled on-chip PdTe2/Si Schottky junction-based photodetector exhibits an ultrabroadband photoresponse of up to 10.6 μm with a large specific detectivity. Furthermore, the highly integrated device array demonstrates high-resolution room-temperature imaging capability, and the device can serve as an optical data receiver for IR optical communication. This study paves the way toward low-temperature growth of 2D semimetals for uncooled MIR sensing.

Superior Quality Low-Temperature Growth of Three-Dimensional Semiconductors Using Intermediate Two-Dimensional Layers

The low-temperature growth of materials that support high-performance devices is crucial for advanced semiconductor technologies such as integrated circuits built using monolithic three-dimensional (3D) integration and flexible electronics. However, low growth temperature prohibits sufficient atomic diffusion and directly leads to poor material quality, imposing severe challenges that limit device performance. Here, we demonstrate superior quality growth of 3D semiconductors at growth temperatures reduced by >200 °C by using two-dimensional (2D) materials as intermediate layers to optimize the potential energy barrier for adatom diffusion. We reveal the benefits of maintaining, but reducing, the potential field through the 2D layer, which coupled with the inert surface of the 2D material lowers the kinetic barriers, enabling long-distance atomic diffusion and enhanced material quality at lower growth temperatures. As model systems, GaN and ZnSe, grown using WSe₂ and graphene intermediate layers, exhibit larger grains, preferred orientation, reduced strain, and improved carrier mobility, all at temperatures lower by >200 °C compared to direct growth as characterized by diffraction, X-ray photoelectron spectroscopy, Raman, and Hall measurements. The realization of high-performance materials using 2D intermediate layers can enable transformative technologies under thermal budget restrictions, and the 2D/3D heterostructures could enable promising heterostructures for future device designs.

Bottom-up synthesis of graphene films hosting atom-thick molecular-sieving apertures

Incorporation of a high density of molecular-sieving nanopores in the graphene lattice by the bottom-up synthesis is highly attractive for high-performance membranes. Herein, we achieve this by a controlled synthesis of nanocrystalline graphene where incomplete growth of a few nanometer-sized, misoriented grains generates molecular-sized pores in the lattice. The density of pores is comparable to that obtained by the state-of-the-art postsynthetic etching (10¹² cm^-2) and is up to two orders of magnitude higher than that of molecular-sieving intrinsic vacancy defects in single-layer graphene (SLG) prepared by chemical vapor deposition. The porous nanocrystalline graphene (PNG) films are synthesized by precipitation of C dissolved in the Ni matrix where the C concentration is regulated by controlled pyrolysis of precursors (polymers and/or sugar). The PNG film is made of few-layered graphene except near the grain edge where the grains taper down to a single layer and eventually terminate into vacancy defects at a node where three or more grains meet. This unique nanostructure is highly attractive for the membranes because the layered domains improve the mechanical robustness of the film while the atom-thick molecular-sized apertures allow the realization of large gas transport. The combination of gas permeance and gas pair selectivity is comparable to that from the nanoporous SLG membranes prepared by state-of-the-art postsynthetic lattice etching. Overall, the method reported here improves the scale-up potential of graphene membranes by cutting down the processing steps.

Low-Temperature As-Grown Crystalline β-Ga2O3 Films via Plasma-Enhanced Atomic Layer Deposition

We report on the low-temperature growth of crystalline Ga₂O₃ films on Si, sapphire, and glass substrates using plasma-enhanced atomic layer deposition (PEALD) featuring a hollow-cathode plasma source. Films were deposited by using triethylgallium (TEG) and Ar/O₂ plasma as metal precursor and oxygen co-reactant, respectively. Growth experiments have been performed within 150-240 °C substrate temperature and 30-300 W radio-frequency (rf) plasma power ranges. Additionally, each unit AB-type ALD cycle was followed by an in situ Ar plasma annealing treatment, which consisted of an extra (50-300 W) Ar plasma exposure for 20 s ending just before the next TEG pulse. The growth per cycle (GPC) of the films without Ar plasma annealing step ranged between 0.69 and 1.31 Å/cycle, and as-grown refractive indices were between 1.67 and 1.75 within the scanned plasma power range. X-ray diffraction (XRD) measurements showed that Ga₂O₃ films grown without in situ Ar plasma annealing exhibited amorphous character irrespective of substrate temperature and rf power values. With the incorporation of the in situ Ar plasma annealing process, the GPC of Ga₂O₃ films ranged between 0.76 and 1.03 Å/cycle along with higher refractive index values of 1.75-1.79. The increased refractive index (1.79) and slightly reduced GPC (1.03 Å/cycle) at 250 W plasma annealing indicated possible densification and crystallization of the films. Indeed, X-ray measurements confirmed that in situ plasma annealed films grow in a monoclinic β-Ga₂O₃ crystal phase. The film crystallinity and density further enhance (from 5.11 to 5.60 g/cm³) by increasing the rf power value used during in situ Ar plasma annealing process. X-ray photoelectron spectroscopy (XPS) measurement of the β-Ga₂O₃ sample grown under optimal in situ plasma annealing power (250 W) revealed near-ideal film stoichiometry (O/Ga of ∼1.44) with relatively low carbon content (∼5 at. %), whereas 50 W rf power treated film was highly non-stoichiometric (O/Ga of ∼2.31) with considerably elevated carbon content. Our results demonstrate the effectiveness of in situ Ar plasma annealing process to transform amorphous wide bandgap oxide semiconductors into crystalline films without needing high-temperature post-deposition annealing treatment.

Direct Growth of Light-Emitting III-V Nanowires on Flexible Plastic Substrates

Semiconductor nanowires are routinely grown on high-priced crystalline substrates as it is extremely challenging to grow directly on plastics and flexible substrates due to high-temperature requirements and substrate preparation. At the same time, plastic substrates can offer many advantages such as extremely low price, light weight, mechanical flexibility, shock and thermal resistance, and biocompatibility. We explore the direct growth of high-quality III-V nanowires on flexible plastic substrates by metal-organic vapor phase epitaxy (MOVPE). We synthesize InAs and InP nanowires on polyimide and show that the fabricated NWs are optically active with strong light emission in the mid-infrared range. We create a monolithic flexible nanowire-based p-n junction device on plastic in just two fabrication steps. Overall, we demonstrate that III-V nanowires can be synthesized directly on flexible plastic substrates inside a MOVPE reactor, and we believe that our results will further advance the development of the nanowire-based flexible electronic devices.

Epitaxial Growth of 6 in. Single-Crystalline Graphene on a Cu/Ni (111) Film at 750 °C via Chemical Vapor Deposition

The future electronic application of graphene highly relies on the production of large-area high-quality single-crystal graphene. However, the growth of single-crystal graphene on different substrates via either single nucleation or seamless stitching is carried out at a temperature of 1000 °C or higher. The usage of this high temperature generates a variety of problems, including complexity of operation, higher contamination, metal evaporation, and wrinkles owing to the mismatch of thermal expansion coefficients between the substrate and graphene. Here, a new approach for the fabrication of ultraflat single-crystal graphene using Cu/Ni (111)/sapphire wafers at lower temperature is reported. It is found that the temperature of epitaxial growth of graphene using Cu/Ni (111) can be reduced to 750 °C, much lower than that of earlier reports on catalytic surfaces. Devices made of graphene grown at 750 °C have a carrier mobility up to ≈9700 cm² V^-1 s^-1 at room temperature. This work shines light on a way toward a much lower temperature growth of high-quality graphene in single crystallinity, which could benefit future electronic applications.

Horizontal-to-Vertical Transition of 2D Layer Orientation in Low-Temperature Chemical Vapor Deposition-Grown PtSe2 and Its Influences on Electrical Properties and Device Applications

Two-dimensional (2D) transition-metal dichalcogenides (2D TMDs) in the form of MX₂ (M: transition metal, X: chalcogen) exhibit intrinsically anisotropic layered crystallinity wherein their material properties are determined by constituting M and X elements. 2D platinum diselenide (2D PtSe₂) is a relatively unexplored class of 2D TMDs with noble-metal Pt as M, offering distinct advantages over conventional 2D TMDs such as higher carrier mobility and lower growth temperatures. Despite the projected promise, much of its fundamental structural and electrical properties and their interrelation have not been clarified, and so its full technological potential remains mostly unexplored. In this work, we investigate the structural evolution of large-area chemical vapor deposition (CVD)-grown 2D PtSe₂ layers of tailored morphology and clarify its influence on resulting electrical properties. Specifically, we unveil the coupled transition of structural-electrical properties in 2D PtSe₂ layers grown at a low temperature (i.e., 400 °C). The layer orientation of 2D PtSe₂ grown by the CVD selenization of seed Pt films exhibits horizontal-to-vertical transition with increasing Pt thickness. While vertically aligned 2D PtSe₂ layers present metallic transports, field-effect-transistor gate responses were observed with thin horizontally aligned 2D PtSe₂ layers prepared with Pt of small thickness. Density functional theory calculation identifies the electronic structures of 2D PtSe₂ layers undergoing the transition of horizontal-to-vertical layer orientation, further confirming the presence of this uniquely coupled structural-electrical transition. The advantage of low-temperature growth was further demonstrated by directly growing 2D PtSe₂ layers of controlled orientation on polyimide polymeric substrates and fabricating their Kirigami structures, further strengthening the application potential of this material. Discussions on the growth mechanism behind the horizontal-to-vertical 2D layer transition are also presented.

Low-Temperature Graphene Growth by Forced Convection of Plasma-Excited Radicals

We developed the forced convection (FC)-PECVD method for the synthesis of graphene, in which a specially designed blowing plasma source is used at moderate gas pressure (1-10 Torr) and the distribution of reactive radicals reaching the substrate surface can be controlled by forced convection. Self-limiting growth of graphene occurs on copper foil, and monolayer graphene growth with a few defects is achieved even at low temperatures (<400 °C). We also demonstrated the enlargement of the growth area using the scalable blowing plasma source. We expect that the FC-PECVD method overcomes the limitations of conventional low-temperature PECVD and provides a breakthrough for the achievement of industrial applications based on graphene.

High-Mobility Helical Tellurium Field-Effect Transistors Enabled by Transfer-Free, Low-Temperature Direct Growth

The transfer-free direct growth of high-performance materials and devices can enable transformative new technologies. Here, room-temperature field-effect hole mobilities as high as 707 cm2 V-1 s-1 are reported, achieved using transfer-free, low-temperature (≤120 °C) direct growth of helical tellurium (Te) nanostructure devices on SiO2 /Si. The Te nanostructures exhibit significantly higher device performance than other low-temperature grown semiconductors, and it is demonstrated that through careful control of the growth process, high-performance Te can be grown on other technologically relevant substrates including flexible plastics like polyethylene terephthalate and graphene in addition to amorphous oxides like SiO2 /Si and HfO2 . The morphology of the Te films can be tailored by the growth temperature, and different carrier scattering mechanisms are identified for films with different morphologies. The transfer-free direct growth of high-mobility Te devices can enable major technological breakthroughs, as the low-temperature growth and fabrication is compatible with the severe thermal budget constraints of emerging applications. For example, vertical integration of novel devices atop a silicon complementary metal oxide semiconductor platform (thermal budget <450 °C) has been theoretically shown to provide a 10× systems level performance improvement, while flexible and wearable electronics (thermal budget <200 °C) can revolutionize defense and medical applications.

Low-Temperature and Rapid Growth of Large Single-Crystalline Graphene with Ethane

Future applications of graphene rely highly on the production of large-area high-quality graphene, especially large single-crystalline graphene, due to the reduction of defects caused by grain boundaries. However, current large single-crystalline graphene growing methodologies are suffering from low growth rate and as a result, industrial graphene production is always confronted by high energy consumption, which is primarily caused by high growth temperature and long growth time. Herein, a new growth condition achieved via ethane being the carbon feedstock to achieve low-temperature yet rapid growth of large single-crystalline graphene is reported. Ethane condition gives a growth rate about four times faster than methane, achieving about 420 µm min^-1 for the growth of sub-centimeter graphene single crystals at temperature about 1000 °C. In addition, the temperature threshold to obtain graphene using ethane can be reduced to 750 °C, lower than the general growth temperature threshold (about 1000 °C) with methane on copper foil. Meanwhile ethane always keeps higher graphene growth rate than methane under the same growth temperature. This study demonstrates that ethane is indeed a potential carbon source for efficient growth of large single-crystalline graphene, thus paves the way for graphene in high-end electronical and optoelectronical applications.

Low-Temperature Growth of Two-Dimensional Layered Chalcogenide Crystals on Liquid

The growth of high-quality two-dimensional (2D) layered chalcogenide crystals is highly important for practical applications in future electronics, optoelectronics, and photonics. Current route for the synthesis of 2D chalcogenide crystals by vapor deposition method mainly involves an energy intensive high-temperature growth process on solid substrates, often suffering from inhomogeneous nucleation density and grain size distribution. Here, we first demonstrate a facile vapor-phase synthesis of large-area high-quality 2D layered chalcogenide crystals on liquid metal surface with relatively low surface energy at a growth temperature as low as ∼100 °C. Uniform and large-domain-sized 2D crystals of GaSe and GaxIn1-xSe were grown on liquid metal surface even supported on a polyimide film. As-grown 2D GaSe crystals have been fabricated to flexible photodetectors, showing high photoresponse and excellent flexibility. Our strategy of energy-sustainable low-temperature growth on liquid metal surface may open a route to the synthesis of high-quality 2D crystals of Ga-, In-, Bi-, Hg-, Pb-, or Sn-based chalcogenides and halides.

Nonstoichiometric Low-Temperature Grown GaAs Nanowires

The structural and electronic properties of nonstoichiometric low-temperature grown GaAs nanowire shells have been investigated with scanning tunneling microscopy and spectroscopy, pump-probe reflectivity, and cathodoluminescence measurements. The growth of nonstoichiometric GaAs shells is achieved through the formation of As antisite defects, and to a lower extent, after annealing, As precipitates. Because of the high density of atomic steps on the nanowire sidewalls, the Fermi level is pinned midgap, causing the ionization of the subsurface antisites and the formation of depleted regions around the As precipitates. Controlling their incorporation offers a way to obtain unique electronic and optical properties that depart from the ones found in conventional GaAs nanowires.

Low-Temperature Growth of Carbon Nanotube Forests Consisting of Tubes with Narrow Inner Spacing Using Co/Al/Mo Catalyst on Conductive Supports

We grow dense carbon nanotube forests at 450 °C on Cu support using Co/Al/Mo multilayer catalyst. As a partial barrier layer for the diffusion of Co into Mo, we apply very thin Al layer with the nominal thickness of 0.50 nm between Co and Mo. This Al layer plays an important role in the growth of dense CNT forests, partially preventing the Co-Mo interaction. The forests have an average height of ∼300 nm and a mass density of 1.2 g cm(-3) with tubes exhibiting extremely narrow inner spacing. An ohmic behavior is confirmed between the forest and Cu support with the lowest resistance of ∼8 kΩ. The forest shows a high thermal effusivity of 1840 J s(-0.5) m(-2) K(-1), and a thermal conductivity of 4.0 J s(-1) m(-1) K(-1), suggesting that these forests are useful for heat dissipation devices.

Spray-combustion synthesis: efficient solution route to high-performance oxide transistors

Metal-oxide (MO) semiconductors have emerged as enabling materials for next generation thin-film electronics owing to their high carrier mobilities, even in the amorphous state, large-area uniformity, low cost, and optical transparency, which are applicable to flat-panel displays, flexible circuitry, and photovoltaic cells. Impressive progress in solution-processed MO electronics has been achieved using methodologies such as sol gel, deep-UV irradiation, preformed nanostructures, and combustion synthesis. Nevertheless, because of incomplete lattice condensation and film densification, high-quality solution-processed MO films having technologically relevant thicknesses achievable in a single step have yet to be shown. Here, we report a low-temperature, thickness-controlled coating process to create high-performance, solution-processed MO electronics: spray-combustion synthesis (SCS). We also report for the first time, to our knowledge, indium-gallium-zinc-oxide (IGZO) transistors having densification, nanoporosity, electron mobility, trap densities, bias stability, and film transport approaching those of sputtered films and compatible with conventional fabrication (FAB) operations.

Fabrication of Well-Aligned ZnO Nanorods Using a Composite Seed Layer of ZnO Nanoparticles and Chitosan Polymer

In this study, by taking the advantage of both inorganic ZnO nanoparticles and the organic material chitosan as a composite seed layer, we have fabricated well-aligned ZnO nanorods on a gold-coated glass substrate using the hydrothermal growth method. The ZnO nanoparticles were characterized by the Raman spectroscopic techniques, which showed the nanocrystalline phase of the ZnO nanoparticles. Different composites of ZnO nanoparticles and chitosan were prepared and used as a seed layer for the fabrication of well-aligned ZnO nanorods. Field emission scanning electron microscopy, energy dispersive X-ray, high-resolution transmission electron microscopy, X-ray diffraction, and infrared reflection absorption spectroscopic techniques were utilized for the structural characterization of the ZnO nanoparticles/chitosan seed layer-coated ZnO nanorods on a gold-coated glass substrate. This study has shown that the ZnO nanorods are well-aligned, uniform, and dense, exhibit the wurtzite hexagonal structure, and are perpendicularly oriented to the substrate. Moreover, the ZnO nanorods are only composed of Zn and O atoms. An optical study was also carried out for the ZnO nanoparticles/chitosan seed layer-coated ZnO nanorods, and the obtained results have shown that the fabricated ZnO nanorods exhibit good crystal quality. This study has provided a cheap fabrication method for the controlled morphology and good alignment of ZnO nanorods, which is of high demand for enhancing the working performance of optoelectronic devices.