Total Ionizing Dose Effects on the Threshold Voltage of GaN Cascode Devices

GaN devices are nowadays attracting global attention due to their outstanding performance in high voltage, high frequency, and anti-radiation ability. Research on total ionizing dose and annealing effects on E-mode GaN Cascode devices has been carried out. The Cascode device consists of a low-voltage MOSFET and a high-voltage depletion-mode GaN MISHEMT. Cascode devices of both conventional processed MOSFET and radiation-hardened MOSFET devices are fabricated to observe the TID effects. Experiment results indicate that, for the Cascode device with conventional processed MOSFET, the VTH shifts to negative values at 100 krad(Si). For the Cascode device with radiation-hardened MOSFET, the VTH shifts by -0.5 V at 100 krad(Si), while shifts to negative values are 500 krad(Si). The annealing process, after the TID experiment, shows that it can release trapped charges and help VTH recover. On one hand, the VTH shift and recover trends are similar to those of a single MOSFET device, suggesting that the MOSFET is the vulnerable part in the Cascode which determines the anti-TID ability of the device. On the other hand, the VTH shift amount of the Cascode device is much larger than that of a previously reported p-GaN HEMT device, indicating that GaN material shows a better anti-TID ability than Si.

Experimental Study on Critical Parameters Degradation of Nano PDSOI MOSFET under TDDB Stress

In today's digital circuits, Si-based MOS devices have become the most widely used technology in medical, military, aerospace, and aviation due to their advantages of mature technology, high performance, and low cost. With the continuous integration of transistors, the characteristic size of MOSFETs is shrinking. Time-dependent dielectric electrical breakdown (TDDB) is still a key reliability problem of MOSFETs in recent years. Many researchers focus on the TDDB life of advanced devices and the mechanism of oxide damage, ignoring the impact of the TDDB effect on device parameters. Therefore, in this paper, the critical parameters of partially depleted silicon-on-insulator (PDSOI) under time-dependent dielectric electrical breakdown (TDDB) stress are studied. By applying the TDDB acceleration stress experiment, we obtained the degradation of the devices' critical parameters including transfer characteristic curves, threshold voltage, off-state leakage current, and the TDDB lifetime. The results show that TDDB acceleration stress will lead to the accumulation of negative charge in the gate oxide. The negative charge affects the electric field distribution. The transfer curves of the devices are positively shifted, as is the threshold voltage. Comparing the experimental data of I/O and Core devices, we can conclude that the ultra-thin gate oxide device's electrical characteristics are barely affected by the TDDB stress, while the opposite is true for a thick-gate oxide device.

Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene)

We investigated the effect of gate bias stress (GBS) on the electrical characteristics of ferroelectric oxide thin-film transistors (FeOxTFTs) with poly(vinylidenefluoride-trifluoroethylene). Generally, conventional oxide thin-film transistors (OxTFTs) with dielectric gate insulators exhibit a small negative shift under negative gate bias stress (NBS) and a large positive shift under positive gate bias stress (PBS) in transfer characteristic curves. In contrast, the FeOxTFTs show a small positive shift and a large negative shift under NBS and PBS, respectively. It was confirmed that sufficient changes in the electrical characteristics are obtained by 10 min NBS and PBS. The changed electrical characteristics such as threshold voltage shift, memory on- and memory off-current were maintained for more than 168 h after NBS and 24 h after PBS. It is deduced that, since the dipole alignment of the ferroelectric layer is maximized during GBS, these changes in electrical properties are caused by the remnant dipole moments still being retained during the gate sweep. The memory on- and memory off-current are controlled by GBS and the best on/off current ratio at 10⁷ was obtained after NBS. By repeatedly alternating NBS and PBS, the electrical characteristics were reversibly changed. Our results provide the scientific and technological basis for the development of stability and performance optimization of FeOxTFTs.

Investigation of Negative Bias Temperature Instability Effect in Nano PDSOI PMOSFET

The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was investigated by accelerated stress tests. The results show that NBTI leads to a threshold voltage negative shift, saturate drain current reduction and transconductance degradation of the PMOSFET. Next, the relationship between the threshold voltage shift and stress time, gate bias and temperature, and the channel length is investigated, and the NBTI lifetime prediction model is established. The results show that the NBTI lifetime of a 130 nm T-Gate PDSOI PMOSFET is approximately 18.7 years under the stress of VG = -1.2 V and T = 125 °C. Finally, the effect of the floating-body effect on NBTI of PDSOI PMOSFET is investigated. It is found that the NBTI degradation of T-Gate SOI devices is greater than that of the floating-body SOI devices, which indicates that the floating-body effect suppresses the NBTI degradation of SOI devices.

Defects Induced Charge Trapping/Detrapping and Hysteresis Phenomenon in MoS2 Field-Effect Transistors: Mechanism Revealed by Anharmonic Marcus Charge Transfer Theory

One critical problem inhibiting the application of MoS₂ field-effect transistors (FETs) is the hysteresis in their transfer characteristics, which is typically associated with charge trapping (CT) and charge detrapping (CDT) induced by atomic defects at the MoS₂-dielectric interface. Here, we propose a novel atomistic framework to simulate electronic processes across the MoS₂-SiO₂ interface, demonstrating the distinct CT/CDT behavior of different types of atomic defects and further revealing the defect type(s) that most likely cause hysteresis. An anharmonic approximation of the classical Marcus theory is developed and combined with state-of-the-art density functional theory to calculate the gate bias-dependent CT/CDT rates. All the key electronic quantities are calculated with Heyd-Scuseria-Ernzerhof hybrid functionals. The results show that single Si-dangling bond defects are active electron trapping centers. Single O-dangling bond defects are active hole trapping centers, which are more likely to be responsible for the hysteresis phenomenon due to their significant CT rate and apparent threshold voltage shift. In contrast, double Si-dangling bond defects are not active trap centers. These findings provide fundamental physical insights for understanding the hysteresis behavior of MoS₂ FETs and provide vital support for understanding and solving the reliability of nanoscale devices.

Maximized Hole Trapping in a Polystyrene Transistor Dielectric from a Highly Branched Iminobis(aminoarene) Side Chain

We synthesized highly branched and electron-donating side chain subunits and attached them to polystyrene (PS) used as a dielectric layer in a pentacene field-effect transistor. The influence of these groups on dielectric function, charge retention, and threshold voltage shifts (ΔV_th) depending on their positions in dielectric multilayers was determined. We compared the observations made on an N-perphenylated iminobisaniline side chain with those from the same side chains modified with ZnO nanoparticles and with an adduct formed from tetracyanoethylene (TCNE). We also synthesized an analogue in which six methoxy groups are present instead of two amine nitrogens. At 6 mol % side chain, hopping transport was sufficient to cause shorting of the gate, while at 2 mol %, charge trapping was observable as transistor threshold voltage shifts (ΔV_th). We created three types of devices: with the substituted PS layer as single-layer dielectric, on top of a cross-linked PS layer but in contact with the pentacene (bilayers), and sandwiched between two PS layers in trilayers. Especially large bias stress effects and ΔV_th, larger than those in the case of the hexamethoxy and previously studied dimethoxy analogues, were observed in the second case, and the effects increased with the increasing electron-donating properties of the modified side chains. The highest ΔV_th was consistent with a majority of the side chains stabilizing the trapped charge. Trilayer devices showed decreased charge storage capability compared to previous work in which we used less donating side chains but in higher concentrations. The ZnO and TCNE modifications resulted in slightly more and less negative ΔV_th, respectively, when the side chain polystyrene was not in contact with the pentacene and isolated from the gate electrode. The results indicate a likely maximum combination of molecular charge stabilizing activity and side chain concentration that still allows gate dielectric function.

Relieving the Photosensitivity of Organic Field-Effect Transistors

It is generally believed that the photoresponse behavior of organic field-effect transistors (OFETs) reflects the intrinsic property of organic semiconductors. However, this photoresponse hinders the application of OFETs in transparent displays as driven circuits due to the current instability resulting from the threshold voltage shift under light illumination. It is necessary to relieve the photosensitivity of OFETs to keep the devices stable. 2,6-diphenyl anthracene thin-film and single-crystal OFETs are fabricated on different substrates, and it is found that the degree of molecular order in the conducting channels and the defects at the dielectric/semiconductor interface play important roles in determining the phototransistor performance. When highly ordered single-crystal OFETs are fabricated on polymeric substrates with low defects, the photosensitivity (P) decreases by more than 10⁵ times and the threshold voltage shift (ΔV_T ) is almost eliminated compared with the corresponding thin-film OFETs. This phenomenon is further verified by using another three organic semiconductors for similar characterizations. The decreased P and ΔV_T of OFETs ensure a good current stability for OFETs to drive organic light-emitting diodes efficiently, which is essential to the application of OFETs in flexible and transparent displays.

Role of Hole Trap Sites in MoS2 for Inconsistency in Optical and Electrical Phenomena

Because of strong Coulomb interaction in two-dimensional van der Waals-layered materials, the trap charges at the interface strongly influence the scattering of the majority carriers and thus often degrade their electrical properties. However, the photogenerated minority carriers can be trapped at the interface, modulate the electron-hole recombination, and eventually influence the optical properties. In this study, we report the role of the hole trap sites on the inconsistency in the electrical and optical phenomena between two systems with different interfacial trap densities, which are monolayer MoS₂-based field-effect transistors (FETs) on hexagonal boron nitride (h-BN) and SiO₂ substrates. Electronic transport measurements indicate that the use of h-BN as a gate insulator can induce a higher n-doping concentration of the monolayer MoS₂ by suppressing the free-electron transfer from the intrinsically n-doped MoS₂ to the SiO₂ gate insulator. Nevertheless, optical measurements show that the electron concentration in MoS₂/SiO₂ is heavier than that in MoS₂/h-BN, manifested by the relative red shift of the A_1g Raman peak. The inconsistency in the evaluation of the electron concentration in MoS₂ by electrical and optical measurements is explained by the trapping of the photogenerated holes in the spatially modulated valence band edge of the monolayer MoS₂ caused by the local strain from the SiO₂/Si substrate. This photoinduced electron doping in MoS₂/SiO₂ is further confirmed by the development of the trion component in the power-dependent photoluminescence spectra and negative shift of the threshold voltage of the FET after illumination.

Grain Size and Interface Dependence of Bias Stress Stability of n-Type Organic Field Effect Transistors

The effect of grain size and interface dependence of bias stress stability of C60-based n-type organic field effect transistors (OFETs) has been studied. It has been realized that, with increasing grain size of C60, the bias stress induced threshold voltage shift can be controlled and this effect is mainly attributed to the mechanism of charge trapping at grain boundaries. It is further studied that the growth of C60 on the surface of parylene at elevated substrate temperature leads to the creation of radicals at the interface between the active layer and the gate dielectric. These radicals help to improve the bias stress stability of C60-based n-type OFETs. For achieving the bias stress stability, we have presented a procedure of creation of radicals at the interface between C60 and parylene in single gate OFETs instead of dual gate OFETs.

Geometrical structure and interface dependence of bias stress induced threshold voltage shift in C60-based OFETs

The influence of the nature of interface between organic semiconductor and gate dielectric on bias stress electrical stability of n-type C60-based organic field effect transistors (OFETs) was studied. The bias stress induced threshold voltage (Vth) shift was found to depend critically on the OFET device structure: the direction of V(th) shift in top-gate OFETs was opposite to that in bottom-gate OFETs, while the use of the dual-gate OFET structure resulted in just very small variations in V(th). The opposite direction of Vth shift is attributed to the different nature of interfaces between C60 semiconductor and Parylene dielectric in these devices. The V(th) shift to more positive voltages upon bias stress in bottom-gate C60-OFET was similar to that observed for other n-type semiconductors and rationalized by electron trapping in the dielectric or at the gate dielectric/C60 interface. The opposite direction of Vth shift in top-gate C60-OFETs is attributed to free radical species created in the course of Parylene deposition on the surface of C60 during device fabrication, which produce plenty of hole traps. It was also realized that the dual-gate OFETs gives stable characteristics, which are immune to bias stress effects.