Fast Fabrication Nanopores on a PMMA Membrane by a Local High Electric Field Controlled Breakdown

The sensitivity and accuracy of nanopore sensors are severely hindered by the high noise associated with solid-state nanopores. To mitigate this issue, the deposition of organic polymer materials onto silicon nitride (SiNx) membranes has been effective in obtaining low-noise measurements. Nonetheless, the fabrication of nanopores sub-10 nm on thin polymer membranes remains a significant challenge. This work proposes a method for fabricating nanopores on polymethyl methacrylate (PMMA) membrane by the local high electrical field controlled breakdown, exploring the impact of voltage and current on the breakdown of PMMA membranes and discussing the mechanism underlying the breakdown voltage and current during the formation of nanopores. By improving the electric field application method, transient high electric fields that are one-seven times higher than the breakdown electric field can be utilized to fabricate nanopores. A comparative analysis was performed on the current noise levels of nanopores in PMMA-SiNx composite membranes and SiNx nanopores with a 5 nm diameter. The results demonstrated that the fast fabrication of nanopores on PMMA-SiNx membranes exhibited reduced current noise compared to SiNx nanopores. This finding provides evidence supporting the feasibility of utilizing this technology for efficiently fabricating low-noise nanopores on polymer composite membranes.

Using N-I-N Photodiodes Made of Perovskite Single Crystals for Low Noise Gamma-Ray Spectroscopy

Solution-processed lead halide perovskite single crystals (LHPSCs) are believed to have great potential in gamma-ray spectroscopy. However, obtaining low-defect LHPSCs from a solution at low temperatures is difficult compared to obtaining Bridgman single crystals such as CdTe and Si. Herein, noise from the intrinsic defects of LHPSCs is considered as the main problem hindering their gamma-ray detection performance. By isolating the defect-induced holes in LHPSCs via energy barriers, we show that NIN photodiodes based on three types of LHPSCs, i.e., MAPbBr3 (MA = CH3NH3), MAPbBr2.5Cl0.5, and cascade LHPSCs, have demonstrated good energy resolution in the range of 6.7-10.3% for 662 keV 137Cs gamma-ray photons. The noise for >10 mm3 devices is low, in the order of 340-860 electrons, and the electron collection efficiency reaches 23-43%. These results pave the way for obtaining low-cost, large, high energy-resolution gamma-ray detectors at room temperature (300 K).

High-Power-Efficiency Readout Circuit Employing Average Capacitance-to-Voltage Converter for Micro-Electro-Mechanical System Capacitive Accelerometers

A capacitance-to-voltage converter (CVC) is proposed in this paper and applied to a readout circuit for a micro-electro-mechanical system (MEMS) accelerometer to improve the power efficiency. In a traditional readout circuit, the front-end CVC has to operate at a high sampling frequency to resist thermal noise deterioration due to the large parasitic capacitance introduced by the mechanical sensing element. Thus, the back-end analog-to-digital converter (ADC) also has to operate at a high sampling frequency to avoid noise aliasing when sampling the output signal of the CVC, which leads to high power consumption. The average CVC technique is proposed in this paper to reduce the sampling frequency requirement of the back-end ADC and thus reduce the power consumption. Both the traditional readout circuit and the proposed readout circuit are simulated with a commercial 0.18 μm BCD process. The simulation results show that noise aliasing occurs, and the noise power spectral density (PSD) of the traditional readout circuit increases by 12 dB when the sampling frequency of back-end ADC is reduced by 24 dB. However, in the proposed readout circuit, a noise aliasing effect does not occur. Moreover, the proposed readout circuit reduces the power consumption by 53% without thermal noise deterioration. In addition, the proposed CVC circuits are fabricated in an 0.18 μm BCD process, and the test results show that the presented readout circuit based on the average CVC technique can obtain better performance than the traditional CVC-based readout circuit.

A Review of High-Power Semiconductor Optical Amplifiers in the 1550 nm Band

The 1550 nm band semiconductor optical amplifier (SOA) has great potential for applications such as optical communication. Its wide-gain bandwidth is helpful in expanding the bandwidth resources of optical communication, thereby increasing total capacity transmitted over the fiber. Its relatively low cost and ease of integration also make it a high-performance amplifier of choice for LiDAR applications. In recent years, with the rapid development of quantum-well (QW) material systems, SOAs have gradually overcome the shortcomings of polarization sensitivity and high noise. The research on quantum-dot (QD) materials has further improved the noise characteristics and transmission loss of SOAs. The design of special waveguide structures-such as plate-coupled optical waveguide amplifiers and tapered amplifiers-has also increased the saturation output power of SOAs. The maximum gain of the SOA has been reported to be more than 21 dB. The maximum saturation output power has been reported to be more than 34.7 dBm. The maximum 3 dB gain bandwidth has been reported to be more than 120 nm, the lowest noise figure has been reported to be less than 4 dB, and the lowest polarization-dependent gain has been reported to be 0.1 dB. This study focuses on the improvement and enhancement of the main performance parameters of high-power SOAs in the 1550 nm band and introduces the performance parameters, the research progress of high-power SOAs in the 1550 nm band, and the development and application status of SOAs. Finally, the development trends and prospects of high-power SOAs in the 1550 nm band are summarized.

Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor

This paper presents a novel ultra-high speed, high conversion-gain, low noise CMOS image sensor (CIS) based on charge-sweep transfer gates implemented in a standard 180 nm CIS process. Through the optimization of the photodiode geometry and the utilization of charge-sweep transfer gates, the proposed pixels achieve a charge transfer time of less than 10 ns without requiring any process modifications. Moreover, the gate structure significantly reduces the floating diffusion capacitance, resulting in an increased conversion gain of 183 µV/e-. This advancement enables the image sensor to achieve the lowest reported noise of 5.1 e- rms. To demonstrate the effectiveness of both optimizations, a proof-of-concept CMOS image sensor is designed, taped-out and characterized.

Weak Capacitance Detection Circuit of Micro-Hemispherical Gyroscope Based on Common-Mode Feedback Fusion Modulation and Demodulation

As an effective capacitance signal produced by a micro-hemisphere gyro is usually below the pF level, and the capacitance reading process is susceptible to parasitic capacitance and environmental noise, it is highly difficult to acquire an effective capacitance signal. Reducing and suppressing noise in the gyro capacitance detection circuit is a key means to improve the performance of detecting the weak capacitance generated by MEMS gyros. In this paper, we propose a novel capacitance detection circuit, where three different means are utilized to achieve noise reduction. Firstly, the input common-mode feedback is applied to the circuit to solve the input common-mode voltage drift caused by both parasitic capacitance and gain capacitance. Secondly, a low-noise, high-gain amplifier is used to reduce the equivalent input noise. Thirdly, the modulator-demodulator and filter are introduced to the proposed circuit to effectively mitigate the side effects of noise; thus, the accuracy of capacitance detection can be further improved. The experimental results show that with the input voltage of 6 V, the newly designed circuit produces an output dynamic range of 102 dB and the output voltage noise of 5.69 nV/√Hz, achieving a sensitivity of 12.53 V/pF.

Wafer-Scale Fabrication of Uniform, Micrometer-Sized, Triangular Membranes on Sapphire for High-Speed Protein Sensing in a Nanopore

Ultra-low-noise solid-state nanopores are attractive for high-accuracy single-molecule sensing. A conventional silicon platform introduces acute capacitive noise to the system, which seriously limits the recording bandwidth. Recently, we have demonstrated the creation of thin triangular membranes on an insulating crystal sapphire wafer to eliminate the parasitic device capacitance. Uniquely different from the previous triangular etching window designs, here hexagonal windows were explored to produce triangular membranes by aligning to the sapphire crystal within a large tolerance of alignment angles (10-35°). Interestingly, sapphire facet competition serves to suppress the formation of more complex polygons but creates stable triangular membranes with their area insensitive to the facet alignment. Accordingly, a new strategy was successfully established on a 2 in. sapphire wafer to produce chips with an average membrane side length of 4.7 μm, an area of <30 μm² for 81% chips, or estimated calculated membrane capacitance as low as 0.06 pF. We finally demonstrated <4 μs high-speed and high-fidelity low-noise protein detection under 250 kHz high bandwidth.

Design of a Differential Low-Noise Amplifier Using the JFET IF3602 to Improve TEM Receiver

The observed data of transient electromagnetic (TEM) systems is often contaminated by various noises. Even after stacking averages or applying various denoising algorithms, the interference of the system noise floor cannot be eliminated fundamentally, which limits the survey capability and detection efficiency of TEM. To improve the noise performance of the TEM receiver, we have designed a low-noise amplifier using the current source long-tail differential structure and JFET IF3602 through analyzing the power spectrum characteristics of the TEM forward response. By the designed circuit structure, the JFET operating point is easy to set up. The adverse effect on the JFET differential structure by JFET performance differences is also weakened. After establishing the noise model and optimizing the parameters, the designed low-noise differential amplifier has a noise level of 0.60nV/Hz, which increases the number of effective data 2.6 times compared with the LT1028 amplifier.

Doping Compensation Enables High-Detectivity Infrared Organic Photodiodes for Image Sensing

Infrared organic photodiodes have gained increasing attention due to their great application potentials in night vision, optical communication, and all-weather imaging. However, the commonly occurring high dark current and low detectivity impede infrared photodetectors from portable applications at room temperature. Herein, an efficient and generic doping compensation strategy is developed to improve the detectivity of infrared organic photodiodes. A series of n-type organic semiconductors is investigated, and it is found that doping compensation strategy not only reduces the trap density of states and dark currents, but also restrains the nonradiative recombination with improved charge transport and collection. As a result, an ultralow noise spectral density of 8 × 10^-15 A Hz^-1/2 as well as a high specific detectivity over 10¹³ Jones in 780-1070 nm is achieved at room temperature. More importantly, the high-performance infrared organic photodiodes can be successfully applied in high-pixel-density image arrays without patterning sensing layers. These findings provide important compensation design insights that will be crucial to further improve the performance of infrared organic photodiodes in the future.

Threshold Uniformity Improvement in 1b Quanta Image Sensor Readout Circuit

A new readout architecture for single-bit quanta image sensor (QIS) consisting of a capacitive transimpedance amplifier (CTIA) before a 1-bit quantizer to improve the threshold uniformity of the readout cluster is proposed in this paper. The 1-bit quantizer in the previous single-bit QIS had significant threshold non-uniformity likely caused by the fluctuation of the common-mode voltage of the jot output. To guarantee the stability of the common-mode voltage of input signals fed to the 1-bit quantizer, the CTIA is added before the 1-bit quantizer. A pipeline operation mode is also proposed so the CTIA and 1-bit ADC can work at the same time, thereby reducing the CTIA power consumption. A 2048 × 1024 high-speed test chip was implemented with 45 nm/65 nm stacked backside illuminated (BSI) CMOS image sensor (CIS) process and tested. According to the measured D-log-H results, a good threshold uniformity in the range of 0.3 to 0.8 e- for all readout clusters is demonstrated at 500 frame per second (fps) equivalent timing with 68 mW power consumption.

Low-Cutoff Frequency Reduction in Neural Amplifiers: Analysis and Implementation in CMOS 65 nm

Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μW at 1 V power supply. The measurement results show an input-referred noise of 6.1 μV_rms and occupy 0.04 mm² silicon area.

Low-noise, high-detectivity, polarization-sensitive, room-temperature infrared photodetectors based on Ge quantum dot-decorated Si-on-insulator nanowire field-effect transistors

A CMOS-compatible infrared (IR; 1200-1700 nm) detector based on Ge quantum dots (QDs) decorated on a single Si-nanowire channel on a silicon-on-insulator (SOI) platform with a superior detectivity at room temperature is presented. The spectral response of a single nanowire device measured in a back-gated field-effect transistor geometry displays a very high value of peak detectivity ∼9.33 × 10¹¹Jones at ∼1500 nm with a relatively low dark current (∼20 pA), which is attributed to the fully depleted Si nanowire channel on SOI substrates. The noise power spectrum of the devices exhibits a1/fγ,with the exponent,γshowing two different values of 0.9 and 1.8 owing to mobility fluctuations and generation-recombination of carriers, respectively. Ge QD-decorated nanowire devices exhibit a novel polarization anisotropy with a remarkably high photoconductive gain of ∼10⁴. The superior performance of a Ge QDs/Si nanowire phototransistor in IR wavelengths is potentially attractive to integrate electro-optical devices into Si for on-chip optical communications.

New Risk Situations Related to Low Noise from Electric Vehicles: Perception of Workers as Pedestrians and Other Vehicle Drivers

Sales of electric and hybrid electric vehicles are increasing steadily worldwide, and consequently their presence increases in city areas. At low speeds, the low levels of noise produced by these vehicles could become a new risk factor for road users. However, the magnitude of the risk has not been accurately determined. In addition, its inclusion in the work environment could pose a new risk that should be managed. Thus, in relation to low noise levels of electric and hybrid vehicles, this study aimed to characterise the risk situations and determine the risk perception of workers as pedestrians and internal combustion engine vehicle drivers coming into contact with these vehicles. The data were extracted from 417 questionnaires filled out by the employees of public service companies who come into contact with electric and hybrid vehicles during their working day in the city of Málaga, in the region of Andalusia, Spain. According to the experiences reported, it seems that the risk due to the low noise levels of electric vehicles is moderate and does not reach alarming levels. These risk situations usually occurred in low speed urban areas, particularly when crossing the road, or in semi-pedestrian areas. Almost half the respondents considered that the electric vehicle poses a risk to other road users because it is more difficult to hear, and they believe it likely that other road users could be injured. Despite that risk, pedestrians did not change their way of walking or moving around the parking areas and other areas of the company. Electric and hybrid electric cars are now required to produce sound when travelling at low speeds. Nevertheless, the effectiveness of this measure should be assessed once implemented and future research should explore alternative non-acoustic measures.

A Compliant Ionic Adhesive Electrode with Ultralow Bioelectronic Impedance

Simultaneous implementation of high signal-to-noise ratio (SNR) but low crosstalk is of great importance for weak surface electromyography (sEMG) signals when precisely driving a prosthesis to perform sophisticated activities. However, due to gaps with the curved skin during muscle contraction, many electrodes have poor compliance with skin and suffer from high bioelectrical impedance. This causes serious noise and error in the signals, especially the signals from low-level muscle contractions. Here, the design of a compliant electrode based on an adhesive hydrogel, alginate-polyacrylamide (Alg-PAAm) is reported, which eliminates those large gaps through the strong electrostatic interaction and abundant hydrogen bond with the skin. The obtained compliant electrode, having an ultralow bioelectrical impedance of ≈20 kΩ, can monitor even 2.1% maximal voluntary contraction (MVC) of muscle. Furthermore, benefiting from the high SNR of >5:1 at low-level MVC, the crosstalk from irrelevant muscle is minimized through reducing the electrode size. Finally, a prosthesis is successfully demonstrated to precisely grasp a needle based on a 9 mm² Alg-PAAm compliant electrode. The strategy to design such compliant electrodes provides the potential for improving the quality of dynamically weak sEMG signals to precisely control prosthesis in performing purposefully dexterous activity.

Facile and Ultraclean Graphene-on-Glass Nanopores by Controlled Electrochemical Etching

A wide range of approaches have been explored to meet the challenges of graphene nanostructure fabrication, all requiring complex and high-end nanofabrication platform and suffering from surface contaminations, potentially giving electrical noise and increasing the thickness of the atomically thin graphene membrane. Here, with the use of an electrical pulse on a low-capacitance graphene-on-glass (GOG) membrane, we fabricated clean graphene nanopores on commercially available glass substrates with exceptionally low electrical noise. In situ liquid AFM studies and electrochemical measurements revealed that both graphene nanopore nucleation and growth stem from the electrochemical attack on carbon atoms at defect sites, ensuring the creation of a graphene nanopore. Strikingly, compared to conventional TEM drilled graphene nanopores on SiN supporting membranes, GOG nanopores featured an order-of-magnitude reduced broadband noise, which we ascribed to the electrochemical refreshing of graphene nanopore on mechanically stable glass chips with negligible parasitic capacitance (∼1 pF). Further experiments on double-stranded DNA translocations demonstrated a greatly reduced current noise, and also confirmed the activation of single nanopores. Therefore, the exceptionally low noise and ease of fabrication will facilitate the understanding of the fundamental property and the application of such atomically thin nanopore sensors.

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel †

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than -140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

Noise Optimization Design of Frequency-Domain Air-Core Sensor Based on Capacitor Tuning Technology

In the semi-aviation frequency-domain electromagnetic measurement, the induction air-core coil and the differential pre-amplifier circuit introduce noise, which affects the sensor and results in receiving weak signals and improving the signal-to-noise ratio of the system. In response to this problem, by analyzing the physical structure of the air-core coil sensor and the mechanism of the amplification circuit, combined with the simulation and experimental tests of voltage noise, current noise, resistance noise and other noise components, analyzed that the thermal noise is the main component of the sensor noise in the system frequency band, but directly removing the matching resistor increases the instability of the circuit, causes the coil to work in an underdamped state, and generates a time domain oscillation at the resonant frequency, source impedance analysis and analysis of differential pre-amplifier circuit in the frequency-domain detection method, abandoning the matching resistance scheme and magnetic flux negative feedback scheme. The matching capacitor is added to make the receiver detect the frequency range in the 1–10 kHz range. In normal operation, the noise level reaches 10 nV level, which not only increases the stability of the circuit, but also reduces the noise of the sensor. It has far-reaching significance for the detection of weak frequency signals.

Low-Noise Mid-Infrared Photodetection in BP/h-BN/Graphene van der Waals Heterojunctions

We present a low-noise photodetector based on van der Waals stacked black phosphorus (BP)/boron nitride (h-BN)/graphene tunneling junctions. h-BN acts as a tunneling barrier that significantly blocks dark current fluctuations induced by shallow trap centers in BP. The device provides a high photodetection performance at mid-infrared (mid-IR) wavelengths. While it was found that the photoresponsivity is similar to that in a BP photo-transistor, the noise equivalent power and thus the specific detectivity are nearly two orders of magnitude better. These exemplify an attractive platform for practical applications of long wavelength photodetection, as well as provide a new strategy for controlling flicker noise.

Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

Bioinspired Superdurable Pestle-Loop Mechanical Interlocker with Tunable Peeling Force, Strong Shear Adhesion, and Low Noise

Velcro, the most typical hook-loop interlocker, often suffers from undesirable deformation, breaking, and noise because of the structure of the hook. Inspired by the arrester system of dragonfly, a new mechanical interlocker with a nylon pestle instead of the traditional hook is developed. The pestle-loop mechanical interlocker shows a tunable peeling force from 0.4 ± 0.14 to 6.5 ± 0.72 N and the shear adhesion force of pestle-loop mechanical interlocker is about twice as much as that of velcro. The pestle tape can be separated and fastened with the loop tape up to 30 000 cycles while keeping the original adhesive force and the pestle structure. In comparison, only after 4000 cycles most hooks of the commercial velcro are deformed and even broken, completely losing their adhesive function and their hook structure. These experimental results are further supported by finite element simulitions-the base of pestle mainly bears the separation-caused strain while the middle of hook does. Notably, the sound volume during the separation of pestle-loop mechanical interlocker is merely 49 ± 7.4 dB, much lower than 70 ± 3.5 dB produced by the velcro.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

A Black Phosphorus Carbide Infrared Phototransistor

Photodetectors with broadband detection capability are desirable for sensing applications in the coming age of the internet-of-things. Although 2D layered materials (2DMs) have been actively pursued due to their unique optical properties, by far only graphene and black arsenic phosphorus have the wide absorption spectrum that covers most molecular vibrational fingerprints. However, their reported responsivity and response time are falling short of the requirements needed for enabling simultaneous weak-signal and high-speed detections. Here, a novel 2DM, black phosphorous carbide (b-PC) with a wide absorption spectrum up to 8000 nm is synthesized and a b-PC phototransistor with a tunable responsivity and response time at an excitation wavelength of 2004 nm is demonstrated. The b-PC phototransistor achieves a peak responsivity of 2163 A W^-1 and a shot noise equivalent power of 1.3 fW Hz^-1/2 at 2004 nm. In addition, it is shown that a response time of 0.7 ns is tunable by the gating effect, which renders it versatile for high-speed applications. Under the same signal strength (i.e., excitation power), its performance in responsivity and detectivity in room temperature condition is currently ahead of recent top-performing photodetectors based on 2DMs that operate with a small bias voltage of 0.2 V.

A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure

This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e⁻_rms, low dark current density of 56 pA/cm² at −35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

Recent Enhancements to Interline and Electron Multiplying CCD Image Sensors

This paper describes recent process modifications made to enhance the performance of interline and electron-multiplying charge-coupled-device (EMCCD) image sensors. By use of MeV ion implantation, quantum efficiency in the NIR region of the spectrum was increased by 2×, and image smear was reduced by 6 dB. By reducing the depth of the shallow photodiode (PD) implants, the photodiode-to-vertical-charge-coupled-device (VCCD) transfer gate voltage required for no-lag operation was reduced by 3 V, and the electronic shutter voltage was reduced by 9 V. The thinner, surface pinning layer also resulted in a reduction of smear by 4 dB in the blue portion of the visible spectrum. For EMCCDs, gain aging was eliminated by providing an oxide-only dielectric under its multiplication phase, while retaining the oxide-nitride-oxide (ONO) gate dielectrics elsewhere in the device.

A Multi-Functional Microelectrode Array Featuring 59760 Electrodes, 2048 Electrophysiology Channels, Stimulation, Impedance Measurement and Neurotransmitter Detection Channels

Biological cells are characterized by highly complex phenomena and processes that are, to a great extent, interdependent. To gain detailed insights, devices designed to study cellular phenomena need to enable tracking and manipulation of multiple cell parameters in parallel; they have to provide high signal quality and high spatiotemporal resolution. To this end, we have developed a CMOS-based microelectrode array system that integrates six measurement and stimulation functions, the largest number to date. Moreover, the system features the largest active electrode array area to date (4.48×2.43 mm2) to accommodate 59,760 electrodes, while its power consumption, noise characteristics, and spatial resolution (13.5 μm electrode pitch) are comparable to the best state-of-the-art devices. The system includes: 2,048 action-potential (AP, bandwidth: 300 Hz to 10 kHz) recording units, 32 local-field-potential (LFP, bandwidth: 1 Hz to 300 Hz) recording units, 32 current recording units, 32 impedance measurement units, and 28 neurotransmitter detection units, in addition to the 16 dual-mode voltage-only or current/voltage-controlled stimulation units. The electrode array architecture is based on a switch matrix, which allows for connecting any measurement/stimulation unit to any electrode in the array and for performing different measurement/stimulation functions in parallel.

The α-β circular scanning with large range and low noise

A circular-route scanning method called α-β circular scanning is proposed and realized using sinusoidal signals with a constant phase difference of π/2. Experiments show that the circular scanning range of α-β circular scanning is 57% greater than the rectangular scanning range of raster scanning within an effective optical field of view. Moreover, the scanning speed is improved by 7.8% over raster scanning because the whole sine signal is utilized in α-β circular scanning whereas the flyback area of the saw-tooth signal needs to be discarded in raster scanning. The maximum scanning acceleration decreases by a factor of 44, drastically decreasing the high noise, which should considerably elongate the lifetime of the galvanometers while inhibiting internal vibration. The proposed α-β circular scanning technique could be used in scanning imaging, optical tweezers and laser-beam fabrication.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz.

Low noise, IR-blind organohalide perovskite photodiodes for visible light detection and imaging

Solution-processed organohalide perov-skite photodiodes that have performance metrics matching silicon, but are infrared-blind are reported. The perovskite photodiodes operate in the visible band, have low dark current and noise, high specific detectivity, large linear dynamic range, and fast temporal response. Their properties make them promising candidates for imaging applications.

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm²) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μV_rms in the action-potential band (300 Hz-10 kHz) and 5.4 μV_rms in the local-field-potential band (1 Hz-300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures.

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

A CMOS-Compatible, Low-Noise ISFET Based on High Efficiency Ion-Modulated Lateral-Bipolar Conduction

Ion-sensitive, field-effect transistors (ISFET) have been useful biosensors in many applications. However, the signal-to-noise ratio of the ISFET is limited by its intrinsic, low-frequency noise. This paper presents an ISFET capable of utilizing lateral-bipolar conduction to reduce low-frequency noise. With a particular layout design, the conduction efficiency is further enhanced. Moreover, the ISFET is compatible with the standard CMOS technology. All materials above the gate-oxide are removed by simple, die-level post-CMOS process, allowing ions to modulate the lateral-bipolar current directly. By varying the gate-to-bulk voltage, the operation mode of the ISFET is controlled effectively, so is the noise performance measured and compared. Finally, the biasing conditions preferable for different low-noise applications are identified. Under the identified biasing condition, the signal-to-noise ratio of the ISFET as a pH sensor is proved to be improved by more than five times.