A Low-Cost Measurement Methodology for LiDAR Receiver Integrated Circuits

This paper presents a test methodology to facilitate the measuring processes of LiDAR receiver ICs by avoiding the inherent walk error issue. In a typical LiDAR system, a costly laser diode driver emits narrow light pulses with fast rising edges, and the reflected pulses from targets enter an optical detector followed by an analog front-end (AFE) circuit. Then, the received signals pass through the cascaded amplifiers down to the time-to-digital converter (TDC) that can estimate the detection range. However, this relatively long signal journey leads to the significant decline of rising-edge slopes and the output pulse spreading, thus producing inherent walk errors in LiDAR receiver ICs. Compensation methods requiring complex algorithms and extra chip area have frequently been exploited to lessen the walk errors. In this paper, however, a simpler and lower-cost methodology is proposed to test LiDAR receiver ICs by employing a high-speed buffer and variable delay cells right before the TDC. With these circuits, both START and STOP pulses show very similar pulse shapes, thus effectively avoiding the walk error issue. Additionally, the time interval between two pulses is easily determined by varying the number of the delay cells. Test chips of the proposed receiver IC implemented in a 180-nm CMOS process successfully demonstrate easier and more accurate measurement results.

A Route toward High-Detectivity and Low-Cost Short-Wave Infrared Photodetection: GeSn/Ge Multiple-Quantum-Well Photodetectors with a Dielectric Nanohole Array Metasurface

High-detectivity and low-cost short-wave infrared photodetectors with complementary metal-oxide-semiconductor (CMOS) compatibility are attractive for various applications such as next-generation optical communication, LiDAR, and molecular sensing. Here, GeSn/Ge multiple-quantum-well (MQW) photodetectors with a dielectric nanohole array metasurface were proposed to realize high-detectivity and low-cost SWIR photodetection. The Ge nanohole array metasurface was utilized to enhance the light absorption in the GeSn/Ge MQW active layer. Compared with metallic nanostructures, the dielectric nanohole structure has the advantages of low intrinsic loss and CMOS compatibility. The introduction of metasurface architecture facilitates a 10.5 times enhanced responsivity of 0.232 A/W at 2 μm wavelength while slightly sacrificing the dark current density. Besides, the metasurface GeSn/Ge MQW photodetectors benefit 35% improvement in the 3 dB bandwidth compared to control GeSn/Ge MQW photodetectors, which can be attributed to the reduced RC delay. Due to the high responsivity and low dark current density, the room temperature specific detectivity at 2 μm is as high as 5.34 × 10⁹ cm·Hz^1/2/W, which is the highest among GeSn photodetectors and is better than commercial InSb and PbSe photodetectors operating at the similar wavelength. This work offers a promising approach for achieving low-cost and effective photodetection at 2 μm, contributing to the development of the 2 μm communication band.

CMOS compatible 2T pixel for on-wafer in-situ EUV detection

A novel 2-transistor (2T) pixel EUV detector is proposed and demonstrated by advanced CMOS technology. The proposed 2T detector also exhibits high spectral range (< 267 nm) and spatial resolution (67 μm) with high stability and CMOS Compatibility. The compact 2T EUV detector pixels arranged in a test array are capable of on-wafer recording the 2D EUV flux distribution without any external power. The compact 2T EUV detector pixels arranged in a test array are capable of on-wafer recording the 2D EUV flux distribution without any external power. Through proper initialization process, EUV induced discharging mechanism is fully investigated and an EUV induced electron emission efficiency model is established. Finally, a 2D array for in-situ EUV detection is demonstrated to precisely reflect the pattern projected on the chip/wafer surface.

A Wireless, Mechanically Flexible, 25μm-Thick, 65,536-Channel Subdural Surface Recording and Stimulating Microelectrode Array with Integrated Antennas

This paper presents a fully wireless microelectrode array (MEA) system-on-chip (SoC) with 65,536 electrodes for non-penetrative cortical recording and stimulation, featuring a total sensing area of 6.8mm×7.4mm with a 26.5μm×29μm electrode pitch. Sensing, data telemetry, and powering are monolithically integrated on a single chip, which is made mechanically flexible to conform to the surface of the brain by substrate removal to a total thickness of 25μm allowing it to be contained entirely in the subdural space under the skull.

Monolithic Three-Dimensional Integration of Carbon Nanotube Circuits and Sensors for Smart Sensing Chips

Semiconducting carbon nanotube (CNT) film is a promising material for constructing high-performance complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) and highly sensitive field-effect transistor (FET) bio/chemical sensors. Moreover, CNT logic transistors and sensors can be integrated through a compatible low-temperature fabrication process, providing enough thermal budget to construct monolithic three-dimensional (M3D) systems for smart sensors. However, an M3D sensing chip based on CNT film has not yet been demonstrated. In this work, we develop M3D technology to fabricate CNT CMOS ICs and CNT sensor arrays in two different layers; then, we demonstrate a preliminary M3D sensing system comprising CNT CMOS interfacing ICs in the bottom layer and CNT sensors in the upper layer through interlayer vias as links. As a typical example, a highly sensitive hydrogen sensing IC has been demonstrated to perform in situ sensing and processing functions through upper-layer FET-based hydrogen sensors exposed to the environment and bottom-layer CNT CMOS voltage-controlled oscillator (VCO) interfacing circuits. The M3D CNT sensing ICs convert hydrogen concentration information (8-128 ppm) to digital frequency information (0.78-1.11 GHz) with a sensitivity of 2.75 MHz/ppm. M3D sensing technology is expected to provide a universal sensing system for future smart sensing chips, including multitarget detection and ultralow power sensors.

Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications.

Design and Measurement of Microelectromechanical Three-Axis Magnetic Field Sensors Based on the CMOS Technique

The design, fabrication, and measurement of a microelectromechanical system (MEMS) three-axis magnetic field sensor (MFS) based on the commercial complementary metal oxide semiconductor (CMOS) process are investigated. The MFS is a magnetic transistor type. The performance of the MFS was analyzed employing the semiconductor simulation software, Sentaurus TCAD. In order to decrease the cross-sensitivity of the three-axis MFS, the structure of the MFS is planed to accommodate two independent sensing components, a z-MFS utilized to sense magnetic field (M-F) in the z-direction and a y/x-MFS composed of a y-MFS and a x-MFS to be utilized to sense M-F in the y- and x-directions. The z-MFS incorporates four additional collectors to increase its sensitivity. The commercial 1P6M 0.18 μm CMOS process of the Taiwan Semiconductor Manufacturing Company (TSMC) is utilized to manufacture the MFS. Experiments depict that the MFS has a low cross-sensitivity of less than 3%. The sensitivities of z-, y-, and x-MFS are 237 mV/T, 485 mV/T, and 484 mV/T, respectively.

Measuring and modeling macrophage proliferation in a lab-on-CMOS capacitance sensing microsystem

We report on the use of a lab-on-CMOS biosensor platform for quantitatively tracking the proliferation of RAW 264.7 murine Balb/c macrophages. We show that macrophage proliferation correlates linearly with an average capacitance growth factor resulting from capacitance measurements at a plurality of electrodes dispersed in a sensing area of interest. We further show a temporal model that captures the cell number evolution in the area over long periods (e.g., 30 h). The model links the cell numbers and the average capacitance growth factor to describe the observed cell proliferation.

Classification of nucleic acid amplification on ISFET arrays using spectrogram-based neural networks

The COVID-19 pandemic has highlighted a significant research gap in the field of molecular diagnostics. This has brought forth the need for AI-based edge solutions that can provide quick diagnostic results whilst maintaining data privacy, security and high standards of sensitivity and specificity. This paper presents a novel proof-of-concept method to detect nucleic acid amplification using ISFET sensors and deep learning. This enables the detection of DNA and RNA on a low-cost and portable lab-on-chip platform for identifying infectious diseases and cancer biomarkers. We show that by using spectrograms to transform the signal to the time-frequency domain, image processing techniques can be applied to achieve the reliable classification of the detected chemical signals. Transformation to spectrograms is beneficial as it makes the data compatible with 2D convolutional neural networks and helps gain significant performance improvement over neural networks trained on the time domain data. The trained network achieves an accuracy of 84% with a size of 30kB making it suitable for deployment on edge devices. This facilitates a new wave of intelligent lab-on-chip platforms that combine microfluidics, CMOS-based chemical sensing arrays and AI-based edge solutions for more intelligent and rapid molecular diagnostics.

Automatic Piecewise Extreme Learning Machine-Based Model for S-Parameters of RF Power Amplifier

This paper presents an automatic piecewise (Auto-PW) extreme learning machine (ELM) method for S-parameters modeling radio-frequency (RF) power amplifiers (PAs). A strategy based on splitting regions at the changing points of concave-convex characteristics is proposed, where each region adopts a piecewise ELM model. The verification is carried out with S-parameters measured on a 2.2-6.5 GHz complementary metal oxide semiconductor (CMOS) PA. Compared to the long-short term memory (LSTM), support vector regression (SVR), and conventional ELM modeling methods, the proposed method performs excellently. For example, the modeling speed is two orders of magnitude faster than SVR and LSTM, and the modeling accuracy is more than one order of magnitude higher than ELM.

Room-Temperature CMOS Monolithic Resonant Triple-Band Terahertz Thermal Detector

Multiband terahertz (THz) detectors show great application potential in imaging, spectroscopy, and sensing fields. Thermal detectors have become a promising choice because they could sense THz radiations on the whole spectrum. This paper demonstrates the operation principle, module designs with in-depth theoretical analysis, and experimental validation of a room-temperature CMOS monolithic resonant triple-band THz thermal detector. The detector, which consists of a compact triple-band octagonal ring antenna and a sensitive proportional to absolute temperature (PTAT) sensor, has virtues of room-temperature operation, low cost, easy integration, and mass production. Good experimental results are obtained at 0.91 THz, 2.58 THz, and 4.2 THz with maximum responsivities of 32.6 V/W, 43.2 V/W, and 40 V/W, respectively, as well as NEPs of 1.28 μW/Hz^0.5, 2.19 μW/Hz^0.5, and 2.37 μW/Hz^0.5, respectively, providing great potential for multiband THz sensing and imaging systems.

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design's robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network.

High-Sensitivity CMOS-Integrated Floating Gate-Based UVC Sensors

We report on novel UVC sensors based on the floating gate (FG) discharge principle. The device operation is similar to that of EPROM non-volatile memories UV erasure, but the sensitivity to ultraviolet light is strongly increased by using single polysilicon devices of special design with low FG capacitance and long gate periphery (grilled cells). The devices were integrated without additional masks into a standard CMOS process flow featuring a UV-transparent back end. Low-cost integrated UVC solar blind sensors were optimized for implementation in UVC sterilization systems, where they provided feedback on the radiation dose sufficient for disinfection. Doses of ~10 µJ/cm² at 220 nm could be measured in less than a second. The device can be reprogrammed up to 10,000 times and used to control ~10-50 mJ/cm² UVC radiation doses typically employed for surface or air disinfection. Demonstrators of integrated solutions comprising UV sources, sensors, logics, and communication means were fabricated. Compared with the existing silicon-based UVC sensing devices, no degradation effects that limit the targeted applications were observed. Other applications of the developed sensors, such as UVC imaging, are also discussed.

Combining n-MOS Charge Sensing with p-MOS Silicon Hole Double Quantum Dots in a CMOS platform

Holes in silicon quantum dots are receiving attention due to their potential as fast, tunable, and scalable qubits in semiconductor quantum circuits. Despite this, challenges remain in this material system including difficulties using charge sensing to determine the number of holes in a quantum dot, and in controlling the coupling between adjacent quantum dots. We address these problems by fabricating an ambipolar complementary metal-oxide-semiconductor (CMOS) device using multilayer palladium gates. The device consists of an electron charge sensor adjacent to a hole double quantum dot. We demonstrate control of the spin state via electric dipole spin resonance. We achieve smooth control of the interdot coupling rate over 1 order of magnitude and use the charge sensor to perform spin-to-charge conversion to measure the hole singlet-triplet relaxation time of 11 μs for a known hole occupation. These results provide a path toward improving the quality and controllability of hole spin-qubits.

CMOS Radio Frequency Energy Harvester (RFEH) with Fully On-Chip Tunable Voltage-Booster for Wideband Sensitivity Enhancement

Radio frequency energy harvesting (RFEH) is one form of renewable energy harvesting currently seeing widespread popularity because many wireless electronic devices can coordinate their communications via RFEH, especially in CMOS technology. For RFEH, the sensitivity of detecting low-power ambient RF signals is the utmost priority. The voltage boosting mechanisms at the input of the RFEH are typically applied to enhance its sensitivity. However, the bandwidth in which its sensitivity is maintained is very poor. This work implements a tunable voltage boosting (TVB) mechanism fully on-chip in a 3-stage cross-coupled differential drive rectifier (CCDD). The TVB is designed with an interleaved transformer architecture where the primary winding is implemented to the rectifier, while the secondary winding is connected to a MOSFET switch that tunes the inductance of the network. The TVB enables the sensitivity of the rectifier to be maintained at 1V DC output voltage with a minimum deviation of -2 dBm across a wide bandwidth of 3 to 6 GHz of 5G New Radio frequency (5GNR) bands. A DC output voltage of 1 V and a peak PCE of 83% at 3 GHz for -23 dBm input power are achieved. A PCE of more than 50% can be maintained at the sensitivity point of 1 V with the aid of TVB. The proposed CCDD-TVB mechanism enables the CMOS RFEH to be operated for wideband applications with optimum sensitivity, DC output voltage, and efficiency.

Analysis and Design of a Non-Magnetic Bulk CMOS Passive Circulator Using 25% Duty-Cycle Clock

A circulator, which is a non-reciprocal device, is widely used in full-duplex systems, future communication and sensing networks, and quantum computing, and it is difficult to implement a passive topology on a chip. Based on switch-based spatio-temporal conductivity modulation, in this study, we design and implement a non-magnetic on-chip passive circulator operating at the Ku band in a 90-nm bulk CMOS technology using a 25% duty-cycle I/Q clock signal. With the virtue of the four-phase non-overlapping clock signal, the proposed circulator achieves a 3.9 dB transmitter (TX)-to-antenna (ANT) and a 4.0 dB ANT-to-receiver (RX) insertion loss with a 1-dB bandwidth of 2.7 GHz (21.4%). The TX-to-RX isolation is better than 17.2 dB, and the TX-to-ANT IIP3 and ANT-to-RX IIP3 are 19.7 dBm and 20.0 dBm, respectively, while occupying a die area of 1.55 mm × 1.15 mm. Although low-cost bulk CMOS technology is used, competitive isolation, linearity performance, and isolation bandwidth are achieved in the proposed design.

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks-an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm². The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

Uniformity Correction of CMOS Image Sensor Modules for Machine Vision Cameras

Flat-field correction (FFC) is commonly used in image signal processing (ISP) to improve the uniformity of image sensor pixels. Image sensor nonuniformity and lens system characteristics have been known to be temperature-dependent. Some machine vision applications, such as visual odometry and single-pixel airborne object tracking, are extremely sensitive to pixel-to-pixel sensitivity variations. Numerous cameras, especially in the fields of infrared imaging and staring cameras, use multiple calibration images to correct for nonuniformities. This paper characterizes the temperature and analog gain dependence of the dark signal nonuniformity (DSNU) and photoresponse nonuniformity (PRNU) of two contemporary global shutter CMOS image sensors for machine vision applications. An optimized hardware architecture is proposed to compensate for nonuniformities, with optional parametric lens shading correction (LSC). Three different performance configurations are outlined for different application areas, costs, and power requirements. For most commercial applications, the correction of LSC suffices. For both DSNU and PRNU, compensation with one or multiple calibration images, captured at different gain and temperature settings are considered. For more demanding applications, the effectiveness, external memory bandwidth, power consumption, implementation, and calibration complexity, as well as the camera manufacturability of different nonuniformity correction approaches were compared.

A Direct Feedback FVF LDO for High Precision FMCW Radar Sensors in 65-nm CMOS Technology

A direct feedback flipped voltage follower (FVF) LDO for a high-precision frequency-modulated continuous-wave (FMCW) radar is presented. To minimize the effect of the power supply ripple on the FMCW radar sensor's resolution, a folded cascode error amplifier (EA) was connected to the outer loop of the FVF to increase the open-loop gain. The direct feedback structure enhances the PSRR while minimizing the power supply ripple path and not compromising a transient response. The flipped voltage follower with a super source follower forms a fast feedback loop. The stability and parameter variation sensitivity of the multi-loop FVF LDO were analyzed through the state matrix decomposition. We implemented the FVF LDO in TSMC 65 nm CMOS technology. The fabricated FVF LDO supplied a maximum load current of 20 mA with a 1.2 V power supply. The proposed FVF LDO achieved a full-spectrum PSR with a low-frequency PSRR of 66 dB, unity-gain bandwidth of 469 MHz, and 20 ns transient settling time with a load current step from 1 mA to 20 mA.

A Wideband and Low-Power Distributed Cascode Mixer Using Inductive Feedback

A wideband and low-power distributed cascode mixer is implemented for future mobile communications. The distributed design inspired by the distributed amplifier (DA) enables a mixer to operate in a wide band. In addition, the cascode structure and inductive positive feedback design allow high conversion gain with low-power consumption. The proposed mixer is fabricated using a 130 nm commercial complementary metal-oxide-semiconductor (CMOS) process. It consists of three cascode gain cells and operates with a drain voltage of 1.5 V and a gate voltage of 0.5 to 0.7 V. The fabricated mixer exhibits conversion gain of -2.9 to 3.1 dB at the radio frequencies (RFs) of 4 to 30 GHz and -1.9 to 0.4 dB at RFs of 54 to 66 GHz under the conditions of 8 to 10 dBm of local oscillator (LO) power and 650 MHz of intermediate frequency (IF). The LO-RF isolation is more than 15 dB over the entire measurement band (0.2 to 67 GHz) as the RF and LO signals are applied to different transistors owing to the cascode structure. The total power consumption is only within 12 mW, and the chip size is 0.056 mm², making it possible to implement a compact mixer. The proposed mixer shows broadband characteristics covering from ultra-wideband (UWB) and the 28 GHz fifth-generation (5G) communication band to the 60 GHz wireless gigabit alliance (WiGig) band.

Integrating Microfluidics and Electronics in Point-of-Care Diagnostics: Current and Future Challenges

Point-of-Care (POC) diagnostics have gained increasing attention in recent years due to its numerous advantages over conventional diagnostic approaches. As proven during the recent COVID-19 pandemic, the rapidity and portability of POC testing improves the efficiency of healthcare services and reduces the burden on healthcare providers. There are hundreds of thousands of different applications for POC diagnostics, however, the ultimate requirement for the test is the same: sample-in and result-out. Many technologies have been implemented, such as microfluidics, semiconductors, and nanostructure, to achieve this end. The development of even more powerful POC systems was also enabled by merging multiple technologies into the same system. One successful example is the integration of microfluidics and electronics in POC diagnostics, which has simplified the sample handling process, reduced sample usage, and reduced the cost of the test. This review will analyze the current development of the POC diagnostic systems with the integration of microfluidics and electronics and discuss the future challenges and perspectives that researchers might have.

A 24 GHz CMOS Direct-Conversion RF Receiver with I/Q Mismatch Calibration for Radar Sensor Applications

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer's LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, -35.2 dBm input-referred 1 dB compression power, and 4.8-7.1 dB noise figure across 22.5-26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0-1.5 dB to 0.02-0.19 dB, and from 10.8-23.8 to 1.1-3.2 degrees, respectively.

An Indoor-Monitoring LiDAR Sensor for Patients with Alzheimer Disease Residing in Long-Term Care Facilities

This paper introduces an indoor-monitoring LiDAR sensor for patients with Alzheimer disease residing in long-term care facilities (LTCFs), and this sensor exploits an optoelectronic analog front-end (AFE) to detect light signals from targets by utilizing on-chip avalanche photodiodes (APDs) realized in a 180 nm CMOS process and a neural processing unit (NPU) used for motion detection and decisions, especially for incidents of falls occurring in LTCFs. The AFE consists of an on-chip CMOS P⁺/N-well APD, a linear-mode transimpedance amplifier, a post-amplifier, and a time-to-digital converter, whereas the NPU exploits network sparsity and approximate processing elements for low-power operation. This work provides a potential solution of low-cost, low-power, indoor-monitoring LiDAR sensors for patients with Alzheimer disease in LTCFs.

A CMOS compatible thermoelectric device made of crystalline silicon membranes with nanopores

Herein, we report the use of nanostructured crystalline silicon as a thermoelectric material and its integration into thermoelectric devices. The proof-of-concept relies on the partial suppression of lattice thermal conduction by introducing pores with dimensions scaling between the electron mean free path and the phonon mean free path. In other words, we artificially aimed at the well-known 'electron crystal and phonon glass' trade-off targeted in thermoelectricity. The devices were fabricated using CMOS-compatible processes and exhibited power generation up to 5.5 mW cm^-2under a temperature difference of 280 K. These numbers demonstrate the capability to power autonomous devices with environmental heat sources using silicon chips of centimeter square dimensions. We also report the possibility of using the developed devices for integrated thermoelectric cooling.

A Novel Terahertz Detector Based on Asymmetrical FET Array in 55-nm Standard CMOS Process

This paper reports a novel, one-dimensional dense array of asymmetrical metal-oxide-semiconductor field-effect-transistor (MOSFET) THz detector, which has been fabricated in GlobalFoundries 55-nm CMOS technology. Compared with other technologies, the Si-based complementary metal-oxide-semiconductor (CMOS) dominates in industrial applications, owing to its easier integration and lower cost. However, as the frequency increases, the return loss between the antenna and detector will increase. The proposed THz detector has a short-period grating structure formed by MOSFET fingers in the array, which can serve as an effective antenna to couple incident THz radiation into the FET channels. It not only solved the problem of return loss effectively, but also greatly reduced the detector area. Meanwhile, since the THz signal is rectified at both the source and drain electrodes to generate two current signals with equal amplitude but opposite directions, the source drain voltage is not provided to reduce the power consumption. This leads to a poor performance of the THz detector. Therefore, by using an asymmetric structure for the gate fingers position to replace the source drain voltage, the performance of the detector in the case of zero power consumption can be effectively improved. Compared with the symmetrical MOSFET THz detector, R_v is increased by 183.3% and NEP is decreased by 67.7%.