High Mobility MoS2 Transistor with Low Schottky Barrier Contact by Using Atomic Thick h-BN as a Tunneling Layer

Innovations of metallic contacts on semiconducting 2D transition metal dichalcogenides toward advanced 3D-structured field-effect transistors

2D semiconductors, represented by transition metal dichalcogenides (TMDs), have the potential to be alternative channel materials for advanced 3D field-effect transistors, such as gate-all-around field-effect-transistors (GAAFETs) and complementary field-effect-transistors (C-FETs), due to their inherent atomic thinness, moderate mobility, and short scaling lengths. However, 2D semiconductors encounter several technological challenges, especially the high contact resistance issue between 2D semiconductors and metals. This review provides a comprehensive overview of the high contact resistance issue in 2D semiconductors, including its physical background and the efforts to address it, with respect to their applicability to GAAFET structures.

Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlOx/Al2O3 and a double-gate structure employing high-k dielectric HfO2. Due to the superior subthreshold characteristics, monolayer WS2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage (VDD) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm-1 at VDD = 1 V. In addition, the monolayer WS2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS2 for high-gain and low-power logic circuits and validate the practical application in large areas.

An Ultrafast Multibit Memory Based on the ReS2/h-BN/Graphene Heterostructure

The exponential growth of data in the big data era has made it imperative to improve the data storage density and calculation speed. Therefore, the development of a multibit memory with an ultrafast operational speed is of great significance. In this work, a floating-gate (FG) memory based on the ReS2/h-BN/graphene van der Waals heterostructure is reported. The device exhibits ultrafast and multilevel nonvolatile memory characteristics, notably featuring an exceptionally large memory window of 113.36 V, a substantial erasing/programming current ratio of 107, an ultrafast operational speed of 30 ns, outstanding endurance exceeding 1000 cycles, and retention performance exceeding 1100 s. Furthermore, the device exhibits both electrically and optically tunable multilevel nonvolatile memory behavior. By controlling the voltage and light pulse parameters, the device achieves an electrical memory state of 130 levels (>7 bits) and an optical memory state of 45 levels (>5 bits).

Floating-gate memristor based on a MoS2/h-BN/AuNPs mixed-dimensional heterostructure

Memristors have recently received substantial attention because of their promising and unique emerging applications in neuromorphic computing, which can achieve gains in computation speed by mimicking the topology of the brain in electronic circuits. Traditional memristors made of bulk MoO3and HfO2, for example, suffer from a low switching ratio and poor durability and stability. In this work, a floating-gate memristor is developed based on a mixed-dimensional heterostructure comprising two-dimensional (2D) molybdenum disulfide (MoS2) and zero-dimensional (0D) Au nanoparticles (AuNPs) separated by an insulating hexagonal boron nitride (h-BN) layer (MoS2/h-BN/AuNPs). We find that under the modulation of back-gate voltages, the MoS2/h-BN/AuNPs device operates reliably between a high-resistance state (HRS) and a low-resistance state (LRS) and shows multiple stable LRS states, demonstrating the excellent potential of our memristor in multibit storage applications. The modulation effect can be attributed to electron quantum tunneling between the AuNP charge-trapping layer and the MoS2channel. Our memristor exhibits excellent durability and stability: the HRS and LRS are retained for more than 104s without obvious degradation and the on/off ratio is >104after more than 3000 switching cycles. We also demonstrate frequency-dependent memory properties upon stimulation with electrical and optical pulses.

Controlled Fabrication of Metallic MoO2 Nanosheets towards High-Performance p-Type 2D Transistors

Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDCs) are extensively employed as channel materials in advanced electronic devices. The electrical contacts between electrodes and 2D semiconductors play a crucial role in the development of high-performance transistors. While numerous strategies for electrode interface engineering have been proposed to enhance the performance of n-type 2D transistors, upgrading p-type ones in a similar manner remains a challenge. In this work, significant improvements in a p-type WSe2 transistor are demonstrated by utilizing metallic MoO2 nanosheets as the electrode contact, which are controllably fabricated through physical vapor deposition and subsequent annealing. The MoO2 nanosheets exhibit an exceptional electrical conductivity of 8.4 × 104 S m‒1 and a breakdown current density of 3.3 × 106 A cm‒2. The work function of MoO2 nanosheets is determined to be ≈5.1 eV, making them suitable for contacting p-type 2D semiconductors. Employing MoO2 nanosheets as the electrode contact in WSe2 transistors results in a notable increase in the field-effect mobility to 92.0 cm2 V‒1 s‒1, which is one order of magnitude higher than the counterpart devices with conventional electrodes. This study not only introduces an intriguing 2D metal oxide to improve the electrical contact in p-type 2D transistors, but also offers an effective approach to fabricating all-2D devices.

The Impact of Microwave Annealing on MoS2 Devices Assisted by Neural Network-Based Big Data Analysis

Microwave annealing, an emerging annealing method known for its efficiency and low thermal budget, has established a foundational research base in the annealing of molybdenum disulfide (MoS2) devices. Typically, to obtain high-quality MoS2 devices, mechanical exfoliation is commonly employed. This method's challenge lies in achieving uniform film thickness, which limits the use of extensive data for studying the effects of microwave annealing on the MoS2 devices. In this experiment, we utilized a neural network approach based on the HSV (hue, saturation, value) color space to assist in distinguishing film thickness for the fabrication of numerous MoS2 devices with enhanced uniformity and consistency. This method allowed us to precisely assess the impact of microwave annealing on device performance. We discovered a relationship between the device's electrical performance and the annealing power. By analyzing the statistical data of these electrical parameters, we identified the optimal annealing power for MoS2 devices as 700 W, providing insights and guidance for the microwave annealing process of two-dimensional materials.

Precursor-Confined Chemical Vapor Deposition of 2D Single-Crystalline SexTe1-x Nanosheets for p-Type Transistors and Inverters

Two-dimensional (2D) tellurium (Te) is emerging as a promising p-type candidate for constructing complementary metal-oxide-semiconductor (CMOS) architectures. However, its small bandgap leads to a high leakage current and a low on/off current ratio. Although alloying Te with selenium (Se) can tune its bandgap, thermally evaporated SexTe1-x thin films often suffer from grain boundaries and high-density defects. Herein, we introduce a precursor-confined chemical vapor deposition (CVD) method for synthesizing single-crystalline SexTe1-x alloy nanosheets. These nanosheets, with tunable compositions, are ideal for high-performance field-effect transistors (FETs) and 2D inverters. The preformation of Se-Te frameworks in our developed CVD method plays a critical role in the growth of SexTe1-x nanosheets with high crystallinity. Optimizing the Se composition resulted in a Se0.30Te0.70 nanosheet-based p-type FET with a large on/off current ratio of 4 × 105 and a room-temperature hole mobility of 120 cm2·V-1·s-1, being eight times higher than thermally evaporated SexTe1-x with similar composition and thickness. Moreover, we successfully fabricated an inverter based on p-type Se0.30Te0.70 and n-type MoS2 nanosheets, demonstrating a typical voltage transfer curve with a gain of 30 at an operation voltage of Vdd = 3 V.

Identification of exfoliated monolayer hexagonal boron nitride films with a digital color camera under white light illumination

Optical microscopy with white light illumination has been employed when obtaining exfoliated monolayer hexagonal boron nitride (1L hBN) films from a large number of randomly placed films on a substrate. However, real-time observation of 1L hBN using a color camera under white light illumination remains challenging since hBN is transparent in the visible wavelength range. The poor optical constant of 1L hBN films in microphotographs is significantly improved using a Si substrate coated with a SiNxthin-film (SiNx/Si). When observing hBN thin films on SiNx/Si using a color digital camera in an optical microscope under white light illumination, the clarity of the captured color images depends on the thickness of the SiNxfilm (d). For real-time direct observation, thedwas optimized based on quantitative chromatic studies tailored to Bayer filters of a color image sensor. Through image simulation, it was determined that the color difference between 1L hBN and the bare substrate is maximized atd= 59 or 70 nm, which was experimentally verified. The SiNx/Si with optimizeddvalues visualized 1L hBN films without requiring significant contrast enhancement via image processing under white light illumination in real-time. Furthermore, the captured color photographs facilitate the reliable determination of the number of layers in few-layer hBN films using the contrast of the green channel of the images.

Electronic Devices Based on Heterostructures of 2D Materials and Self-Assembled Monolayers

2D materials (2DMs), known for their atomically ultrathin structure, exhibit remarkable electrical and optical properties. Similarly, molecular self-assembled monolayers (SAMs) with comparable atomic thickness show an abundance of designable structures and properties. The strategy of constructing electronic devices through unique heterostructures formed by van der Waals assembly between 2DMs and molecular SAMs not only enables device miniaturization, but also allows for convenient adjustment of their structures and functions. In this review, the fundamental structures and fabrication methods of three different types of electronic devices dominated by 2DM-SAM heterojunctions with varying architectures are timely elaborated. Based on these heterojunctions, their fundamental functionalities and characteristics, as well as the regulation of their performance by external stimuli, are further discussed.

Van der Waals Schottky Junction Photodetector with Ultrahigh Rectifying Ratio and Switchable Photocurrent Generation

Metal-semiconductor junctions play an important role in the development of electronic and optoelectronic devices. A Schottky junction photodetector based on two-dimensional (2D) materials is promising for self-powered photodetection with fast response speed and large signal-to-noise ratio. However, it usually suffers from an uncontrolled Schottky barrier due to the Fermi level pinning effect arising from the interface states. In this work, all-2D Schottky junctions with near-ideal Fermi level depinning are realized, attributed to the high-quality interface between 2D semimetals and semiconductors. We further demonstrate asymmetric diodes based on multilayer graphene/MoS2/PtSe2 with a current rectification ratio exceeding 105 and an ideality factor of 1.2. Scanning photocurrent mapping shows that the photocurrent generation mechanism in the heterostructure switches from photovoltaic effect to photogating effect at varying drain biases, indicating both energy conversion and optical sensing are realized in a single device. In the photovoltaic mode, the photodetector is self-powered with a response time smaller than 100 μs under the illumination of a 405 nm laser. In the photogating mode, the photodetector exhibits a high responsivity up to 460 A/W originating from a high photogain. Finally, the photodetector is employed for single-pixel imaging, demonstrating its high-contrast photodetection ability. This work provides insight into the development of high-performance self-powered photodetectors based on 2D Schottky junctions.

Hydrogen-Bonding Integrated Low-Dimensional Flexible Electronics Beyond the Limitations of van der Waals Contacts

Van der Waals (vdW) integration enables clean contacts for low-dimensional electronic devices. The limitation remains; however, that an additional tunneling contact resistance occurs owing to the inherent vdW gap between the metal and the semiconductor. Here, it is demonstrated from theoretical calculations that stronger non-covalent hydrogen-bonding interactions facilitate electron tunneling and significantly reduce the contact resistance; thus, promising to break the limitations of the vdW contact. π-plane hydrogen-bonding contacts in surface-engineered MXene/carbon nanotube metal/semiconductor heterojunctions are realized, and an anomalous temperature-dependent tunneling resistance is observed. Low-dimensional flexible thin-film transistors integrated by hydrogen-bonding contacts exhibit both excellent flexibility and carrier mobility orders of magnitude higher than their counterparts with vdW contacts. This strategy demonstrates a scalable solution for realizing high-performance and low-power flexible electronics beyond vdW contacts.

Impact of Rh, Ru, and Pd Leads and Contact Topologies on Performance of WSe2 FETs: A First Comparative Ab Initio Study

2D field-effect transistors (FETs) fabricated with transition metal dichalcogenide (TMD) materials are a potential replacement for the silicon-based CMOS. However, the lack of advancement in p-type contact is also a key factor hindering TMD-based CMOS applications. The less investigated path towards improving electrical characteristics based on contact geometries with low contact resistance (RC) has also been established. Moreover, finding contact metals to reduce the RC is indeed one of the significant challenges in achieving the above goal. Our research provides the first comparative analysis of the three contact configurations for a WSe2 monolayer with different noble metals (Rh, Ru, and Pd) by employing ab initio density functional theory (DFT) and non-equilibrium Green's function (NEGF) methods. From the perspective of the contact topologies, the RC and minimum subthreshold slope (SSMIN) of all the conventional edge contacts are outperformed by the novel non-van der Waals (vdW) sandwich contacts. These non-vdW sandwich contacts reveal that their RC values are below 50 Ω∙μm, attributed to the narrow Schottky barrier widths (SBWs) and low Schottky barrier heights (SBHs). Not only are the RC values dramatically reduced by such novel contacts, but the SSMIN values are lower than 68 mV/dec. The new proposal offers the lowest RC and SSMIN, irrespective of the contact metals. Further considering the metal leads, the WSe2/Rh FETs based on the non-vdW sandwich contacts show a meager RC value of 33 Ω∙μm and an exceptional SSMIN of 63 mV/dec. The two calculated results present the smallest-ever values reported in our study, indicating that the non-vdW sandwich contacts with Rh leads can attain the best-case scenario. In contrast, the symmetric convex edge contacts with Pd leads cause the worst-case degradation, yielding an RC value of 213 Ω∙μm and an SSMIN value of 95 mV/dec. While all the WSe2/Ru FETs exhibit medium performances, the minimal shift in the transfer curves is interestingly advantageous to the circuit operation. Conclusively, the low-RC performances and the desirable SSMIN values are a combination of the contact geometries and metal leads. This innovation, achieved through noble metal leads in conjunction with the novel contact configurations, paves the way for a TMD-based CMOS with ultra-low RC and rapid switching speeds.

Reliable wafer-scale integration of two-dimensional materials and metal electrodes with van der Waals contacts

Since the first report on single-layer MoS2 based transistor, rapid progress has been achieved in two-dimensional (2D) material-based atomically thin electronics, providing an alternative approach to solve the bottleneck in silicon device miniaturization. In this scenario, reliable contact between the metal electrodes and the subnanometer-thick 2D materials becomes crucial in determining the device performance. Here, utilizing the quasi-van der Waals (vdW) epitaxy of metals on fluorophlogopite mica, we demonstrate an all-stacking method for the fabrication of 2D devices with high-quality vdW contacts by mechanically transferring pre-deposited metal electrodes. This technique is applicable for complex device integration with sizes up to the wafer scale and is also capable of tuning the electric characteristics of the interfacial junctions by transferring selective metals. Our results provide an efficient, scalable, and low-cost technique for 2D electronics, allowing high-density device integration as well as a handy tool for fundamental research in vdW materials.

Adjustment methods of Schottky barrier height in one- and two-dimensional semiconductor devices

The Schottky contact which is a crucial interface between semiconductors and metals is becoming increasingly significant in nano-semiconductor devices. A Schottky barrier, also known as the energy barrier, controls the depletion width and carrier transport across the metal-semiconductor interface. Controlling or adjusting Schottky barrier height (SBH) has always been a vital issue in the successful operation of any semiconductor device. This review provides a comprehensive overview of the static and dynamic adjustment methods of SBH, with a particular focus on the recent advancements in nano-semiconductor devices. These methods encompass the work function of the metals, interface gap states, surface modification, image-lowering effect, external electric field, light illumination, and piezotronic effect. We also discuss strategies to overcome the Fermi-level pinning effect caused by interface gap states, including van der Waals contact and 1D edge metal contact. Finally, this review concludes with future perspectives in this field.

Enhancing Carrier Mobility in Monolayer MoS2 Transistors with Process-Induced Strain

Two-dimensional electronic materials are a promising candidate for beyond-silicon electronics due to their favorable size scaling of electronic performance. However, a major challenge is the heterogeneous integration of 2D materials with CMOS processes while maintaining their excellent properties. In particular, there is a knowledge gap in how thin film deposition and processes interact with 2D materials to alter their strain and doping, both of which have a drastic impact on device properties. In this study, we demonstrate how to utilize process-induced strain, a common technique extensively applied in the semiconductor industry, to enhance the carrier mobility in 2D material transistors. We systematically varied the tensile strain in monolayer MoS2 transistors by iteratively depositing thin layers of high-stress MgOx stressor. At each thickness, we combined Raman spectroscopy and transport measurements to unravel and correlate the changes in strain and doping within each transistor with their performance. The transistors displayed uniform strain distributions across their channels for tensile strains of up to 0.48 ± 0.05%, at 150 nm of stressor thickness. At higher thicknesses, mechanical instability occurred, leading to nonuniform strains. The transport characteristics systematically varied with strain, with enhancement in electron mobility at a rate of 130 ± 40% per % strain and enhancement of the channel saturation current density of 52 ± 20%. This work showcases how established CMOS technologies can be leveraged to tailor the transport in 2D transistors, accelerating the integration of 2D electronics into a future computing infrastructure.

Monolayer Vacancy-Induced MXene Memory for Write-Verify-Free Programming

The fundamental logic states of 1 and 0 in Complementary Metal-Oxide-Semiconductor (CMOS) are essential for modern high-speed non-volatile solid-state memories. However, the accumulated storage signal in conventional physical components often leads to data distortion after multiple write operations. This necessitates a write-verify operation to ensure proper values within the 0/1 threshold ranges. In this work, a non-gradual switching memory with two distinct stable resistance levels is introduced, enabled by the asymmetric vertical structure of monolayer vacancy-induced oxidized Ti3C2Tx MXene for efficient carrier trapping and releasing. This non-cumulative resistance effect allows non-volatile memories to attain valid 0/1 logic levels through direct reprogramming, eliminating the need for a write-verify operation. The device exhibits superior performance characteristics, including short write/erase times (100 ns), a large switching ratio (≈3 × 104), long cyclic endurance (>104 cycles), extended retention (>4 × 106 s), and highly resistive stability (>104 continuous write operations). These findings present promising avenues for next-generation resistive memories, offering faster programming speed, exceptional write performance, and streamlined algorithms.

One-pot solvothermal preparation of the porous NiS2//MoS2 composite catalyst with enhanced low-temperature hydrodesulfurization activity

The simple preparation of mesoporous NiS2//MoS2 composite catalyst through a one-pot solvothermal method is presented. The improvement of the specific surface area (220 m2/g) and the construction of the porous structure are realized by this method in the case of no support. The organics acts as a microscopic binder contribute to uniform stacking of MoS2 with NiS2 clusters. The composite structure including NiS2 and MoS2 was obtained (proved by XRD, XPS, TEM, IR, UV-vis and RAMAN) and changed the microelectronic environment of the active metal surface (DFT calculation). The mesoporous NiS2//MoS2 catalyst (Ni1Mo1-200) showed an excellent hydrodesulfurization performance of dibenzothiophene (DBT conversion: 78 % at 260 °C) and a high ratio of direct desulfurization pathway (SDDS/HYD = 16.6) at a low reaction temperature. By combining the characterization and theoretical calculation results, the advantages of this NiS2//MoS2 composite structure in synergistic catalysis was further confirmed.

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Silicon transistors are approaching their physical limit, calling for the emergence of a technological revolution. As the acknowledged ultimate version of transistor channels, 2D semiconductors are of interest for the development of post-Moore electronics due to their useful properties and all-in-one potentials. Here, the promise and current status of 2D semiconductors and transistors are reviewed, from materials and devices to integrated applications. First, we outline the evolution and challenges of silicon-based integrated circuits, followed by a detailed discussion on the properties and preparation strategies of 2D semiconductors and van der Waals heterostructures. Subsequently, the significant progress of 2D transistors, including device optimization, large-scale integration, and unconventional devices, are presented. We also examine 2D semiconductors for advanced heterogeneous and multifunctional integration beyond CMOS. Finally, the key technical challenges and potential strategies for 2D transistors and integrated circuits are also discussed. We envision that the field of 2D semiconductors and transistors could yield substantial progress in the upcoming years and hope this review will trigger the interest of scientists planning their next experiment.

Reducing contact resistance of MoS2-based field effect transistors through uniform interlayer insertion via atomic layer deposition

Molybdenum disulfide (MoS2), a semiconducting two-dimensional layered transition metal dichalcogenide (2D TMDC), with attractive properties enables the opening of a new electronics era beyond Si. However, the notoriously high contact resistance (RC) regardless of the electrode metal has been a major challenge in the practical applications of MoS2-based electronics. Moreover, it is difficult to lower RC because the conventional doping technique is unsuitable for MoS2 due to its ultrathin nature. Therefore, the metal-insulator-semiconductor (MIS) architecture has been proposed as a method to fabricate a reliable and stable contact with low RC. Herein, we introduce a strategy to fabricate MIS contact based on atomic layer deposition (ALD) to dramatically reduce the RC of single-layer MoS2 field effect transistors (FETs). We utilize ALD Al2O3 as an interlayer for the MIS contact of bottom-gated MoS2 FETs. Based on the Langmuir isotherm, the uniformity of ALD Al2O3 films on MoS2 can be increased by modulating the precursor injection pressures even at low temperatures of 150 °C. We discovered, for the first time, that film uniformity critically affects RC without altering the film thickness. Additionally, we can add functionality to the uniform interlayer by adopting isopropyl alcohol (IPA) as an oxidant. Tunneling resistance across the MIS contact is lowered by n-type doping of MoS2 induced by IPA as the oxidant in the ALD process. Through a highly uniform interlayer combined with strong doping, the contact resistance is improved by more than two orders of magnitude compared to that of other MoS2 FETs fabricated in this study.

van der Waals Contact for Two-Dimensional Transition Metal Dichalcogenides

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as highly promising candidates for next-generation electronics owing to their atomically thin structures and surfaces devoid of dangling bonds. However, establishing high-quality metal contacts with TMDs presents a critical challenge, primarily attributed to their ultrathin bodies and delicate lattices. These distinctive characteristics render them susceptible to physical damage and chemical reactions when conventional metallization approaches involving "high-energy" processes are implemented. To tackle this challenge, the concept of van der Waals (vdW) contacts has recently been proposed as a "low-energy" alternative. Within the vdW geometry, metal contacts can be physically laminated or gently deposited onto the 2D channel of TMDs, ensuring the formation of atomically clean and electronically sharp contact interfaces while preserving the inherent properties of the 2D TMDs. Consequently, a considerable number of vdW contact devices have been extensively investigated, revealing unprecedented transport physics or exceptional device performance that was previously unachievable. This review presents recent advancements in vdW contacts for TMD transistors, discussing the merits, limitations, and prospects associated with each device geometry. By doing so, our purpose is to offer a comprehensive understanding of the current research landscape and provide insights into future directions within this rapidly evolving field.

Investigation on Contact Properties of 2D van der Waals Semimetallic 1T-TiS2/MoS2 Heterojunctions

Two-dimensional transition metal dichalcogenides (2D TMDCs) are considered promising alternatives to Si as channel materials because of the possibility of retaining their superior electronic transport properties even at atomic body thicknesses. However, the realization of high-performance 2D TMDC field-effect transistors remains a challenge owing to Fermi-level pinning (FLP) caused by gap states and the inherent high Schottky barrier height (SBH) within the metal contact and channel layer. This study demonstrates that high-quality van der Waals (vdW) heterojunction-based contacts can be formed by depositing semimetallic TiS2 onto monolayer (ML) MoS2. After confirming the successful formation of a TiS2/ML MoS2 heterojunction, the contact properties of vdW semimetal TiS2 were thoroughly investigated. With clean interfaces of the TiS2/ML MoS2 heterojunctions, atomic-layer-deposited TiS2 can induce gap-state saturation and suppress FLP. Consequently, compared with conventional evaporated metal electrodes, the TiS2/ML MoS2 heterojunctions exhibit a lower SBH of 8.54 meV and better contact properties. This, in turn, substantially improves the overall performance of the device, including its on-current, subthreshold swing, and threshold voltage. Furthermore, we believe that our proposed strategy for vdW-based contact formation will contribute to the development of 2D materials used in next-generation electronics.

Contacts at the Nanoscale and for Nanomaterials

Contact scaling is a major challenge in nano complementary metal-oxide-semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current-voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The difficulties, such as the limited doping level and choices of metal for band alignment, Fermi-level pinning, and van der Waals gap, in achieving transparent ohmic contacts with emerging two-dimensional materials are also examined. Finally, various methods for improving ohmic contacts' characteristics, such as two-dimensional/metal van der Waals contacts and hybrid contacts, junction doping technology, phase and bandgap modification effects, buffer layers, are highlighted.

Ultrashort channel MoSe2transistors with selenium atoms replaced at the interface: first-principles quantum-transport study

Realizing n- and p-type transition metal dichalcogenide (TMD)-based field-effect transistors for nanoscale complementary metal oxide semiconductor (CMOS) applications remains challenging owing to undesirable contact resistance. Quantumtransport calculations were performed by replacing single-sided Se atoms of TMD near the interface with As or Br atoms to further improve the contact resistance. Here, partial selenium replacement produced a novel interface with a segment of metamaterial MoSeX (Pt/MoSeX/MoSe2; X = As, Br). Such stable metamaterials exhibit semi-metallicity, and the contact resistance can be thus lowered. Our findings provide insights into the potential of MoSe2-based nano-CMOS logic devices.

Wafer-scale synthesis of two-dimensional ultrathin films

Two-dimensional (2D) materials, consisting of atomically thin layered crystals, have attracted tremendous interest due to their outstanding intrinsic properties and diverse applications in electronics, optoelectronics, and catalysis. The large-scale growth of high-quality ultrathin 2D films and their utilization in the facile fabrication of devices, easily adoptable in industrial applications, have been extensively sought after during the last decade; however, it remains a challenge to achieve these goals. Herein, we introduce three key concepts: (i) the microwave assisted quick (∼1 min) synthesis of wafer-scale (6-inch) anisotropic conducting ultrathin (∼1 nm) amorphous carbon and 2D semiconducting metal chalcogenide atomically thin films, (ii) a polymer-assisted deposition process for the synthesis of wafer-scale (6-inch) 2D metal chalcogenide and pyrolyzed carbon thin films, and (iii) the surface diffusion and epitaxial self-planarization induced synthesis of wafer-scale (2-inch) single crystal 2D binary and large-grain 2D ferromagnetic ternary metal chalcogenide thin films. The proposed synthesis concepts can pave a new way for the manufacture of wafer-scale high quality 2D ultrathin films and their utilization in the facile fabrication of devices.

In-Depth Analysis on Self Alignment Effect of the Fermi-Level Using Graphene on Both n- and p-Type Semiconductors

Optimizing the contact structure while reducing the contact resistance in advanced transistors has become an extremely challenging problem. Because the existing techniques are limited to controlling only one semiconductor type, either n- or p-type, owing to their work function differences, significant challenges are encountered in the integration of a contact structure and metal suitable for both n- and p-type semiconductors. This is a formidable drawback of the complementary metal-oxide-semiconductor (CMOS) technology. In this paper, we demonstrate the effectiveness of a metal/graphene/semiconductor (MGrS) as a universal source/drain contact structure for both n- and p-type transistors. The MGrS contact structure significantly enhanced the reverse current density (JR) and reduced the Schottky barrier height (SBH) for both semiconductor types. From the analysis of the SBH values and their relationship with the metal work function, which refers to the S-parameter, the van der Waals contact of graphene (Gr) effectively alleviated the Fermi level (FL) pinning for both semiconductor types, reducing the metal-induced gap states (MIGS) at the Gr/semiconductor interface. Furthermore, Gr effectively modulated the work function of the contact metal to yield a position favorable for each semiconductor type. Consequently, a single MGrS contact structure on a Si substrate resulted in excellent Ohmic contacts in both n- and p-type Si, with SBH values reduced to 0.012 and 0.024 eV for n- and p-type Si, respectively. This new approach for integrating the contact structures of semiconductor types will lead to extended capabilities for high-performance device applications and CMOS logical circuitry.

Quaternary, layered, 2D chalcogenide, Mo1-xWxSSe: thickness dependent transport properties

Highly oriented, single crystalline, quaternary alloy chalcogenide crystal, MoxW1-xS2ySe2(1-y), is synthesized using a high temperature chemical vapor transport technique and its transport properties studied over a wide temperature range. Field effect transistors (FET) with bottom gated configuration are fabricated using Mo0.5W0.5SSe flakes of different thicknesses, from a single layer to bulk. The FET characteristics are thickness tunable, with thin flakes (1-4 layers) exhibiting n-type transport behaviour while ambipolar transfer characteristics are observed for thicker flakes (>90 layers). Ambipolar behavior with the dominance of n-type over p-type transport is noted for devices fabricated with layers between 9 and 90. The devices with flake thickness ∼9 layers exhibit a maximum electron mobility 63 ± 4 cm2V-1s-1and anION/IOFFratio >108. A maximum hole mobility 10.3 ± 0.4 cm2V-1s-1is observed for the devices with flake thickness ∼94 layers withION/IOFFratio >102-103observed for the hole conduction. A maximumION/IOFFfor hole conduction, 104is obtained for the devices fabricated with flakes of thickness ∼7-19 layers. The electron Schottky barrier height values are determined to be ∼23.3 meV and ∼74 meV for 2 layer and 94 layers flakes respectively, as measured using low temperature measurements. This indicates that an increase in hole current with thickness is likely to be due to lowering of the band gap as a function of thickness. Furthermore, the contact resistance (Rct) is evaluated using transmission line model (TLM) and is found to be 14 kohm.μm. These results suggest that quaternary alloys of Mo0.5W0.5SSe are potential candidates for various electronic/optoelectronic devices where properties and performance can be tuned within a single composition.

Approaching Ohmic Contacts for Ideal Monolayer MoS2 Transistors Through Sulfur-Vacancy Engineering

Field-effect transistors (FETs) made of monolayer 2D semiconductors (e.g., MoS2 ) are among the basis of the future modern wafer chip industry. However, unusually high contact resistances at the metal-semiconductor interfaces have seriously limited the improvement of monolayer 2D semiconductor FETs so far. Here, a high-scale processable strategy is reported to achieve ohmic contact between the metal and monolayer MoS2 with a large number of sulfur vacancies (SVs) by using simple sulfur-vacancy engineering. Due to the successful doping of the contact regions by introducing SVs, the contact resistance of monolayer MoS2 FET is as low as 1.7 kΩ·µm. This low contact resistance enables high-performance MoS2 FETs with ultrahigh carrier mobility of 153 cm2 V-1 s-1 , a large on/off ratio of 4 × 109 , and high saturation current of 342 µA µm-1 . With the comprehensive investigation of different SV concentrations by adjusting the plasma duration, it is also demonstrated that the SV-increased electron doping, with its resulting reduced Schottky barrier, is the dominant factor driving enhanced electrical performance. The work provides a simple method to promote the development of industrialized atomically thin integrated circuits.

Negative Capacitance Field Effect Transistors based on Van der Waals 2D Materials

Steep subthreshold swing (SS) is a decisive index for low energy consumption devices. However, the SS of conventional field effect transistors (FETs) has suffered from Boltzmann Tyranny, which limits the scaling of SS to sub-60 mV dec-1 at room temperature. Ferroelectric gate stack with negative capacitance (NC) is proved to reduce the SS effectively by the amplification of the gate voltage. With the application of 2D ferroelectric materials, the NC FETs can be further improved in performance and downscaled to a smaller dimension as well. This review introduces some related concepts for in-depth understanding of NC FETs, including the NC, internal gate voltage, SS, negative drain-induced barrier lowering, negative differential resistance, single-domain state, and multi-domain state. Meanwhile, this work summarizes the recent advances of the 2D NC FETs. Moreover, the electrical characteristics of some high-performance NC FETs are expressed as well. The factors which affect the performance of the 2D NC FETs are also presented in this paper. Finally, this work gives a brief summary and outlook for the 2D NC FETs.

Origins of Fermi Level Pinning for Ni and Ag Metal Contacts on Tungsten Dichalcogenides

Tungsten transition metal dichalcogenides (W-TMDs) are intriguing due to their properties and potential for application in next-generation electronic devices. However, strong Fermi level (EF) pinning manifests at the metal/W-TMD interfaces, which could tremendously restrain the carrier injection into the channel. In this work, we illustrate the origins of EF pinning for Ni and Ag contacts on W-TMDs by considering interface chemistry, band alignment, impurities, and imperfections of W-TMDs, contact metal adsorption mechanism, and the resultant electronic structure. We conclude that the origins of EF pinning at a covalent contact metal/W-TMD interface, such as Ni/W-TMDs, can be attributed to defects, impurities, and interface reaction products. In contrast, for a van der Waals contact metal/TMD system such as Ag/W-TMDs, the primary factor responsible for EF pinning is the electronic modification of the TMDs resulting from the defects and impurities with the minor impact of metal-induced gap states. The potential strategies for carefully engineering the metal deposition approach are also discussed. This work unveils the origins of EF pinning at metal/TMD interfaces experimentally and theoretically and provides guidance on further enhancing and improving the device performance.

Drift velocity saturation in field-effect transistors based on single CdSe nanowires

Field-effect transistors (FETs) based on semiconductor nanowires (NWs) have been extensively investigated and used for constructing novel nanoelectronic and optoelectronic devices in the past two decades. High electric field transport characteristics in FETs are of significance in both physics and applications. However, some specific physics phenomena at high electric field, such as drift velocity saturation, have rarely been reported in semiconductor NW FETs. In this work, the high electric field transport characteristics in FETs based on CdSe NWs were investigated. In the output characteristic curves, the current saturation phenomenon at high electric field caused by drift velocity saturation was observed. Typical values of saturation drift velocity and low electric field mobility in CdSe NW FETs were obtained. The low electric field mobility is in the range of 265.2 to 388.0 cm2 V-1 s-1. The saturation drift velocity is in the range of 5.1 × 105 to 7.0 × 105 cm s-1 and decreases monotonically with the increase of charge density, indicating that the electron-phonon scattering mechanism dominates at high electric field. Saturation drift velocity is an important figure-of-merit which characterizes the high electric field transport performance in FETs. As far as we know, this is the first experimental report on saturation drift velocity in CdSe NW FETs, which may provide valuable guidance for the design of nanoelectronic and optoelectronic devices based on CdSe NWs in the future.

Optically Active MXenes in Van der Waals Heterostructures

The vertical integration of distinct 2D materials in van der Waals (vdW) heterostructures provides the opportunity for interface engineering and modulation of electronic as well as optical properties. However, scarce experimental studies reveal many challenges for vdW heterostructures, hampering the fine-tuning of their electronic and optical functionalities. Optically active MXenes, the most recent member of the 2D family, with excellent hydrophilicity, rich surface chemistry, and intriguing optical properties, are a novel 2D platform for optoelectronics applications. Coupling MXenes with various 2D materials into vdW heterostructures can open new avenues for the exploration of physical phenomena of novel quantum-confined nanostructures and devices. Therefore, the fundamental basis and recent findings in vertical vdW heterostructures composed of MXenes as a primary component and other 2D materials as secondary components are examined. Their robust designs and synthesis approaches that can push the boundaries of light-harvesting, transition, and utilization are discussed, since MXenes provide a unique playground for pursuing an extraordinary optical response or unusual light conversion features/functionalities. The recent findings are finally summarized, and a perspective for the future development of next-generation vdW multifunctional materials enriched by MXenes is provided.

ZrTe2 Compound Dirac Semimetal Contacts for High-Performance MoS2 Transistors

Recent investigations reveal elemental semimetal (Bi and Sb) contacts fabricated with conventional deposition processes exhibit a remarkable capacity of approaching the quantum limit in two-dimensional (2D) semiconductor contacts, implying it might be an optimal option to solve the contact issue of 2D semiconductor electronics. Here, we demonstrate novel compound Dirac semimetal ZrTe2 contacts to MoS2 constructed by a nondestructive van der Waals (vdW) transfer process, exhibiting excellent ohmic contact characteristics with a negligible Schottky barrier. The band hybridization between ZrTe2 and MoS2 was verified. The bilayer MoS2 transistor with a 250 nm channel length on a 20 nm thick hexagonal boron nitride (h-BN) exhibits an ION/IOFF current ratio over 105 and an on-state current of 259 μA μm-1. The current results reveal that 2D compound semimetals with vdW contacts can offer a diverse selection of proper semimetals with adjustable work functions for the next-generation 2D-based beyond-silicon electronics.

Integration of Self-Passivated Topological Electrodes for Advanced 2D Optoelectronic Devices

With the rapid development of two-dimensional semiconductor technology, the inevitable chemical disorder at a typical metal-semiconductor interface has become an increasingly serious problem that degrades the performance of 2D semiconductor optoelectronic devices. Herein, defect-free van der Waals contacts have been achieved by utilizing topological Bi₂ Se₃ as the electrodes. Such clean and atomically sharp contacts avoid the consumption of photogenerated carriers at the interface, enabling a markedly boosted sensitivity as compared to counterpart devices with directly deposited metal electrodes. Typically, the device with 2D WSe₂ channel realizes a high responsivity of 20.5 A W^-1 , an excellent detectivity of 2.18 × 10¹²  Jones, and a fast rise/decay time of 41.66/38.81 ms. Furthermore, high-resolution visible-light imaging capability of the WSe₂ device is demonstrated, indicating its promising application prospect in future optoelectronic systems. More inspiringly, the topological electrodes are universally applicable to other 2D semiconductor channels, including WS₂ and InSe, suggesting its broad applicability. These results open fascinating opportunities for the development of high-performance electronics and optoelectronics.

Perforated Carbon Nanotube Film Assisted Growth of Uniform Monolayer MoS2

Scaling up the chemical vapor deposition (CVD) of monolayer transition metal dichalcogenides (TMDCs) is in high demand for practical applications. However, for CVD-grown TMDCs on a large scale, there are many existing factors that result in their poor uniformity. In particular, gas flow, which usually leads to inhomogeneous distributions of precursor concentrations, has yet to be well controlled. In this work, the growth of uniform monolayer MoS₂ on a large scale by the delicate control of gas flows of precursors, which is realized by vertically aligning a well-designed perforated carbon nanotube (p-CNT) film face-to-face with the substrate in a horizontal tube furnace, is achieved. The p-CNT film releases gaseous Mo precursor from the solid part and allows S vapor to pass through the hollow part, resulting in uniform distributions of both gas flow rate and precursor concentrations near the substrate. Simulation results further verify that the well-designed p-CNT film guarantees a steady gas flow and a uniform spatial distribution of precursors. Consequently, the as-grown monolayer MoS₂ shows quite good uniformity in geometry, density, structure, and electrical properties. This work provides a universal pathway for the synthesis of large-scale uniform monolayer TMDCs, and will advance their applications in high-performance electronic devices.

Schottky barrier height engineering on MoS2 field-effect transistors using a polymer surface modifier on a contact electrode

Two-dimensional (2D) materials are highly sought after for their superior semiconducting properties, making them promising candidates for next-generation electronic and optoelectronic devices. Transition-metal dichalcogenides (TMDCs), such as molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂), are promising alternative 2D materials. However, the devices based on these materials experience performance deterioration due to the formation of a Schottky barrier between metal contacts and semiconducting TMDCs. Here, we performed experiments to reduce the Schottky barrier height of MoS₂ field-effect transistors (FETs) by lowering the work function (Ф_m = E_vacuum - E_F,metal) of the contact metal. We chose polyethylenimine (PEI), a polymer containing simple aliphatic amine groups (-NH₂), as a surface modifier of the Au (Ф_Au = 5.10 eV) contact metal. PEI is a well-known surface modifier that lowers the work function of various conductors such as metals and conducting polymers. Such surface modifiers have thus far been utilized in organic-based devices, including organic light-emitting diodes, organic solar cells, and organic thin-film transistors. In this study, we used the simple PEI coating to tune the work function of the contact electrodes of MoS₂ FETs. The proposed method is rapid, easy to implement under ambient conditions, and effectively reduces the Schottky barrier height. We expect this simple and effective method to be widely used in large-area electronics and optoelectronics due to its numerous advantages.

Triboelectric Nanogenerators Based on 2D Materials: From Materials and Devices to Applications

Recently, there has been an increasing consumption of fossil fuels such as oil and natural gas in both industrial production and daily life. This high demand for non-renewable energy sources has prompted researchers to investigate sustainable and renewable energy alternatives. The development and production of nanogenerators provide a promising solution to address the energy crisis. Triboelectric nanogenerators, in particular, have attracted significant attention due to their portability, stability, high energy conversion efficiency, and compatibility with a wide range of materials. Triboelectric nanogenerators (TENGs) have many potential applications in various fields, such as artificial intelligence (AI) and the Internet of Things (IoT). Additionally, by virtue of their remarkable physical and chemical properties, two-dimensional (2D) materials, such as graphene, transition metal dichalcogenides (TMDs), hexagonal boron nitride (h-BN), MXenes, and layered double hydroxides (LDHs), have played a crucial role in the advancement of TENGs. This review summarizes recent research progress on TENGs based on 2D materials, from materials to their practical applications, and provides suggestions and prospects for future research.

Emerging 2D Metal Oxides: From Synthesis to Device Integration

2D metal oxides have aroused increasing attention in the field of electronics and optoelectronics due to their intriguing physical properties. In this review, an overview of recent advances on synthesis of 2D metal oxides and their electronic applications is presented. First, the tunable physical properties of 2D metal oxides that relate to the structure (various oxidation-state forms, polymorphism, etc.), crystallinity and defects (anisotropy, point defects, and grain boundary), and thickness (quantum confinement effect, interfacial effect, etc.) are discussed. Then, advanced synthesis methods for 2D metal oxides besides mechanical exfoliation are introduced and classified into solution process, vapor-phase deposition, and native oxidation on a metal source. Later, the various roles of 2D metal oxides in widespread applications, i.e., transistors, inverters, photodetectors, piezotronics, memristors, and potential applications (solar cell, spintronics, and superconducting devices) are discussed. Finally, an outlook of existing challenges and future opportunities in 2D metal oxides is proposed.

All-Transfer Electrode Interface Engineering Toward Harsh-Environment-Resistant MoS2 Field-Effect Transistors

Nanoscale electronic devices that can work in harsh environments are in high demand for wearable, automotive, and aerospace electronics. Clean and defect-free interfaces are of vital importance for building nanoscale harsh-environment-resistant devices. However, current nanoscale devices are subject to failure in these environments, especially at defective electrode-channel interfaces. Here, harsh-environment-resistant MoS₂ transistors are developed by engineering electrode-channel interfaces with an all-transfer of van der Waals electrodes. The delivered defect-free, graphene-buffered electrodes keep the electrode-channel interfaces intact and robust. As a result, the as-fabricated MoS₂ devices have reduced Schottky barrier heights, leading to a very large on-state current and high carrier mobility. More importantly, the defect-free, hydrophobic graphene buffer layer prevents metal diffusion from the electrodes to MoS₂ and the intercalation of water molecules at the electrode-MoS₂ interfaces. This enables high resistances of MoS₂ devices with all-transfer electrodes to various harsh environments, including humid, oxidizing, and high-temperature environments, surpassing the devices with other kinds of electrodes. The work deepens the understanding of the roles of electrode-channel interfaces in nanoscale devices and provides a promising interface engineering strategy to build nanoscale harsh-environment-resistant devices.

Hardware and Information Security Primitives Based on 2D Materials and Devices

Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon-based complementary metal-oxide-semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon-based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D-materials-based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large-scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

A critical review of fabrication challenges and reliability issues in top/bottom gated MoS2field-effect transistors

The voyage of semiconductor industry to decrease the size of transistors to achieve superior device performance seems to near its physical dimensional limitations. The quest is on to explore emerging material systems that offer dimensional scaling to match the silicon- based technologies. The discovery of atomic flat two-dimensional materials has opened up a completely new avenue to fabricate transistors at sub-10 nanometer level which has the potential to compete with modern silicon-based semiconductor devices. Molybdenum disulfide (MoS₂) is a two-dimensional layered material with novel semiconducting properties at atomic level seems like a promising candidate that can possibly meet the expectation of Moore's law. This review discusses the various 'fabrication challenges' in making MoS₂based electronic devices from start to finish. The review outlines the intricate challenges of substrate selection and various synthesis methods of mono layer and few-layer MoS₂. The review focuses on the various techniques and methods to minimize interface defect density at substrate/MoS₂interface for optimum MoS₂-based device performance. The tunable band-gap of MoS₂with varying thickness presents a unique opportunity for contact engineering to mitigate the contact resistance issue using different elemental metals. In this work, we present a comprehensive overview of different types of contact materials with myriad geometries that show a profound impact on device performance. The choice of different insulating/dielectric gate oxides on MoS₂in co-planar and vertical geometry is critically reviewed and the physical feasibility of the same is discussed. The experimental constraints of different encapsulation techniques on MoS₂and its effect on structural and electronic properties are extensively discussed.

Diverse field-effect characteristics and negative differential transconductance in a graphene/WS2/Au phototransistor with a Ge back gate

We propose an infrared-sensitive negative differential transconductance (NDT) phototransistor based on a graphene/WS₂/Au double junction with a SiO₂/Ge gate. By changing the drain bias, diverse field-effect characteristics can be achieved. Typical p-type and n-type behavior is obtained under negative and positive drain bias, respectively. And NDT behavior is observed in the transfer curves under positive drain bias. It is believed to originate from competition between the top and bottom channel currents in stepped layers of WS₂ at different gate voltages. Moreover, this phototransistor shows a gate-modulated rectification ratio of 0.03 to 88.3. In optoelectronic experiments, the phototransistor exhibits a responsivity of 2.76 A/W under visible light at 532 nm. By contrast, an interesting negative responsivity of -29.5 µA/W is obtained and the NDT vanishes under illumination by infrared light at 1550 nm. A complementary inverter based on two proposed devices of the same structure is constructed. The maximum voltage gain of the complementary inverter reaches 0.79 at a supply voltage of 1.5 V. These results demonstrate a new method of realizing next-generation two- and three-dimensional electronic and optoelectronic multifunctional devices.

Layer-Structured Anisotropic Metal Chalcogenides: Recent Advances in Synthesis, Modulation, and Applications

The unique electronic and catalytic properties emerging from low symmetry anisotropic (1D and 2D) metal chalcogenides (MCs) have generated tremendous interest for use in next generation electronics, optoelectronics, electrochemical energy storage devices, and chemical sensing devices. Despite many proof-of-concept demonstrations so far, the full potential of anisotropic chalcogenides has yet to be investigated. This article provides a comprehensive overview of the recent progress made in the synthesis, mechanistic understanding, property modulation strategies, and applications of the anisotropic chalcogenides. It begins with an introduction to the basic crystal structures, and then the unique physical and chemical properties of 1D and 2D MCs. Controlled synthetic routes for anisotropic MC crystals are summarized with example advances in the solution-phase synthesis, vapor-phase synthesis, and exfoliation. Several important approaches to modulate dimensions, phases, compositions, defects, and heterostructures of anisotropic MCs are discussed. Recent significant advances in applications are highlighted for electronics, optoelectronic devices, catalysts, batteries, supercapacitors, sensing platforms, and thermoelectric devices. The article ends with prospects for future opportunities and challenges to be addressed in the academic research and practical engineering of anisotropic MCs.

Revealing the Modulation Effects on the Electronic Band Structures and Exciton Properties by Stacking Graphene/h-BN/MoS2 Schottky Heterostructures

Stacking two dimensional tunneling heterostructures has always been an important strategy to improve the optoelectronic device performance. However, there are still many disputes about the blocking ability of monolayer (1L-) h-BN on the interlayer coupling. Graphene/h-BN/MoS₂ optoelectronic devices have been reported for superior device results. In this study, starting with graphene/h-BN/MoS₂ heterostructures, we report experimental evidence of 1L-h-BN barrier layer modulation effects about the electronic band structures and exciton properties. We find that 1L-h-BN insertion only partially blocks the interlayer carrier transfer. In the meantime, the 1L-h-BN barrier layer weakens the interlayer coupling effect, by decreasing the efficient dielectric screening and releasing the quantum confinement. Consequently, the optical conductivity and plasmon excitation slightly improve, and the electronic band structures remain unchanged in graphene/h-BN/MoS₂, explaining their fascinating optoelectronic responses. Moreover, the excitonic binding energies of graphene/h-BN/MoS₂ redshift with respect to the graphene/MoS₂ counterparts. Our results, as well as the broadband optical constants, will help better understand the h-BN barrier layers, facilitating the developing progress of h-BN-based tunneling optoelectronic devices.

Charge-Gradient-Induced Ferroelectricity with Robust Polarization Reversal

Developing a ferroelectric tunnel junction with a robust polarization reversal is essential for errorless data storage, but it remains challenging since the second-order phase transition dominates the reversal and introduces intermediate states. This investigation has proposed a charge-gradient-induced ferroelectricity, which is featured with the first-order phase transition. As an order parameter, a charge-gradient-induced polarization is achieved by modulation of stoichiometric oxygen along the Bi₂O₂Se/Bi₂Se₃O₉ bilayer during pulsed laser deposition. At room temperature, this polarity points out-of-plane and shows an abrupt reversal in the ferroelectric hysteresis loop. The coercive field only increases by 0.04 V/nm after 300 reversals. Fabricated into the ferroelectric tunnel junction, the bilayer ferroelectric exhibits a comparable electroresistance of 100. The ON/OFF state can be switched repeatedly or after a 360 s retention. Characterizations of scanning capacitance microscopy and the current-voltage relation demonstrate that the ON/OFF switching is based on an injection exchange between the tunnelling and the thermionic emission.

Modifying the Power and Performance of 2-Dimensional MoS2 Field Effect Transistors

Over the past 60 years, the semiconductor industry has been the core driver for the development of information technology, contributing to the birth of integrated circuits, Internet, artificial intelligence, and Internet of Things. Semiconductor technology has been evolving in structure and material with co-optimization of performance-power-area-cost until the state-of-the-art sub-5-nm node. Two-dimensional (2D) semiconductors are recognized by the industry and academia as a hopeful solution to break through the quantum confinement for the future technology nodes. In the recent 10 years, the key issues on 2D semiconductors regarding material, processing, and integration have been overcome in sequence, making 2D semiconductors already on the verge of application. In this paper, the evolution of transistors is reviewed by outlining the potential of 2D semiconductors as a technological option beyond the scaled metal oxide semiconductor field-effect transistors. We mainly focus on the optimization strategies of mobility (μ), equivalent oxide thickness (EOT), and contact resistance (R_C ), which enables high ON current (I_on ) with reduced driving voltage (V_dd ). Finally, we prospect the semiconductor technology roadmap by summarizing the technological development of 2D semiconductors over the past decade.

Approaching the quantum limit in two-dimensional semiconductor contacts

The development of next-generation electronics requires scaling of channel material thickness down to the two-dimensional limit while maintaining ultralow contact resistance^1,2. Transition-metal dichalcogenides can sustain transistor scaling to the end of roadmap, but despite a myriad of efforts, the device performance remains contact-limited^3-12. In particular, the contact resistance has not surpassed that of covalently bonded metal-semiconductor junctions owing to the intrinsic van der Waals gap, and the best contact technologies are facing stability issues^3,7. Here we push the electrical contact of monolayer molybdenum disulfide close to the quantum limit by hybridization of energy bands with semi-metallic antimony ([Formula: see text]) through strong van der Waals interactions. The contacts exhibit a low contact resistance of 42 ohm micrometres and excellent stability at 125 degrees Celsius. Owing to improved contacts, short-channel molybdenum disulfide transistors show current saturation under one-volt drain bias with an on-state current of 1.23 milliamperes per micrometre, an on/off ratio over 10⁸ and an intrinsic delay of 74 femtoseconds. These performances outperformed equivalent silicon complementary metal-oxide-semiconductor technologies and satisfied the 2028 roadmap target. We further fabricate large-area device arrays and demonstrate low variability in contact resistance_, threshold voltage, subthreshold swing, on/off ratio, on-state current and transconductance¹³. The excellent electrical performance, stability and variability make antimony ([Formula: see text]) a promising contact technology for transition-metal-dichalcogenide-based electronics beyond silicon.

A "Click" Reaction to Engineer MoS2 Field-Effect Transistors with Low Contact Resistance

Two-dimensional (2D) materials with the atomically thin thickness have attracted great interest in the post-Moore's Law era because of their tremendous potential to continue transistor downscaling and offered advances in device performance at the atomic limit. However, the metal-semiconductor contact is the bottleneck in field-effect transistors (FETs) integrating 2D semiconductors as channel materials. A robust and tunable doping method at the source and drain region of 2D transistors to minimize the contact resistance is highly sought after. Here we report a stable carrier doping method via the mild covalent grafting of maleimides on the surface of 2D transition metal dichalcogenides. The chemisorbed interaction contributes to the efficient carrier doping without degrading the high-performance carrier transport. Density functional theory results further illustrate that the molecular functionalization leads to the mild hybridization and the negligible impact on the conduction bands of monolayer MoS₂, avoiding the random scattering from the dopants. Differently from reported molecular treatments, our strategy displays high thermal stability (above 300 °C) and it is compatible with micro/nano processing technology. The contact resistance of MoS₂ FETs can be greatly reduced by ∼12 times after molecular functionalization. The Schottky barrier of 44 meV is achieved on monolayer MoS₂ FETs, demonstrating efficient charge injection between metal and 2D semiconductor. The mild covalent functionalization of molecules on 2D semiconductors represents a powerful strategy to perform the carrier doping and the device optimization.

Improvement of Visible Photodetection of Chemical Vapor Deposition-Grown MoS2 Devices via Graphene/Au Contacts

Two-dimensional (2D) molybdenum disulfide (MoS₂) is a promising material for constructing high-performance visible photosensor arrays because of its high mobility and scale-up process. These distinct properties enable the construction of practical optoelectrical sensor arrays. However, contact engineering for MoS₂ films is not still optimized. In this work, we inserted a graphene interlayer between the MoS₂ films and Au contacts (graphene/Au) via the wet-transfer method to boost the device performance. Using graphene/Au contacts, outstanding electrical properties, namely field-effect mobility of 12.06 cm²/V∙s, on/off current ratio of 1.0 × 10⁷, and responsivity of 610 A/W under illumination at 640 nm, were achieved. These favorable results were from the Fermi-level depinning effect induced by the graphene interlayer. Our results may help to construct large-area photonic sensor arrays based on 2D materials.

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. The different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

The Road for 2D Semiconductors in the Silicon Age

Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high-performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon-compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all-in-one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer-scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.