A low-power 32-channel digitally programmable neural recording integrated circuit

A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates

Intracortical brain-machine interfaces have shown promise for restoring function to people with paralysis, but their translation to portable and implantable devices is hindered by their high power consumption. Recent devices have drastically reduced power consumption compared to standard experimental brain-machine interfaces, but still require wired or wireless connections to computing hardware for feature extraction and inference. Here, we introduce a Neural Recording And Decoding (NeuRAD) application specific integrated circuit (ASIC) in 180 nm CMOS that can extract neural spiking features and predict two-dimensional behaviors in real-time. To reduce amplifier and feature extraction power consumption, the NeuRAD has a hardware accelerator for extracting spiking band power (SBP) from intracortical spiking signals and includes an M0 processor with a fixed-point Matrix Acceleration Unit (MAU) for efficient and flexible decoding. We validated device functionality by recording SBP from a nonhuman primate implanted with a Utah microelectrode array and predicting the one- and two-dimensional finger movements the monkey was attempting to execute in closed-loop using a steady-state Kalman filter (SSKF). Using the NeuRAD's real-time predictions, the monkey achieved 100% success rate and 0.82 s mean target acquisition time to control one-dimensional finger movements using just 581 μW. To predict two-dimensional finger movements, the NeuRAD consumed 588 μW to enable the monkey to achieve a 96% success rate and 2.4 s mean acquisition time. By employing SBP, ASIC brain-machine interfaces can close the gap to enable fully implantable therapies for people with paralysis.

A 1024-Channel 10-Bit 36- μW/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping

This paper presents a 1024-channel neural read-out integrated circuit (ROIC) for solution-gated GFET sensing probes in massive μECoG brain mapping. The proposed time-domain multiplexing of GFET-only arrays enables low-cost and scalable hybrid headstages. Low-power CMOS circuits are presented for the GFET analog frontend, including a CDS mechanism to improve preamplifier noise figures and 10-bit 10-kS/s A/D conversion. The 1024-channel ROIC has been fabricated in a standard 1.8-V 0.18- μm CMOS technology with 0.012 mm ² and 36 μ W per channel. An automated methodology for the in-situ calibration of each GFET sensor is also proposed. Experimental ROIC tests are reported using a custom FPGA-based μECoG headstage with 16×32 and 32×32 GFET probes in saline solution and agar substrate. Compared to state-of-art neural ROICs, this work achieves the largest scalability in hybrid platforms and it allows the recording of infra-slow neural signals.

Recording Strategies for High Channel Count, Densely Spaced Microelectrode Arrays

Neuroscience research into how complex brain functions are implemented at an extra-cellular level requires in vivo neural recording interfaces, including microelectrodes and read-out circuitry, with increased observability and spatial resolution. The trend in neural recording interfaces toward employing high-channel-count probes or 2D microelectrodes arrays with densely spaced recording sites for recording large neuronal populations makes it harder to save on resources. The low-noise, low-power requirement specifications of the analog front-end usually requires large silicon occupation, making the problem even more challenging. One common approach to alleviating this consumption area burden relies on time-division multiplexing techniques in which read-out electronics are shared, either partially or totally, between channels while preserving the spatial and temporal resolution of the recordings. In this approach, shared elements have to operate over a shorter time slot per channel and active area is thus traded off against larger operating frequencies and signal bandwidths. As a result, power consumption is only mildly affected, although other performance metrics such as in-band noise or crosstalk may be degraded, particularly if the whole read-out circuit is multiplexed at the analog front-end input. In this article, we review the different implementation alternatives reported for time-division multiplexing neural recording systems, analyze their advantages and drawbacks, and suggest strategies for improving performance.

A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain-machine interfaces

The large power requirement of current brain-machine interfaces is a major hindrance to their clinical translation. In basic behavioural tasks, the downsampled magnitude of the 300-1,000 Hz band of spiking activity can predict movement similarly to the threshold crossing rate (TCR) at 30 kilo-samples per second. However, the relationship between such a spiking-band power (SBP) and neural activity remains unclear, as does the capability of using the SBP to decode complicated behaviour. By using simulations of recordings of neural activity, here we show that the SBP is dominated by local single-unit spikes with spatial specificity comparable to or better than that of the TCR, and that the SBP correlates better with the firing rates of lower signal-to-noise-ratio units than the TCR. With non-human primates, in an online task involving the one-dimensional decoding of the movement of finger groups and in an offline two-dimensional cursor-control task, the SBP performed equally well or better than the TCR. The SBP may enhance the decoding performance of neural interfaces while enabling substantial cuts in power consumption.

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, low-power Delta-Sigma analog-to-digital converter (ADC) and a real-time spike processor based on one exponential component-polynomial component (EC-PC) algorithm. High-precision data conversion with low power consumption and small chip area is achieved by employing several techniques, such as opamp-sharing, multi-bit successive approximation (SAR) quantizer, two-step summation, and ultra-low distortion data weighted averaging (DWA). The on-chip EC-PC engine enables low latency, automatic detection, and extraction of spiking activities, thus supporting closed-loop control, real-time data compression and /or neural information decoding. The prototype chip was fabricated in a 0.13  μm CMOS process and verified in both bench-top and In-Vivo experiments. Bench-top measurement results indicate the designed ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 91.8 dB and a dynamic range of 93.0 dB over a 10 kHz bandwidth, where the total power consumption of the modulator is only 20  μW at 1.0 V supply, corresponding to a figure-of-merit (FOM) of 31.4fJ /conversion-step. In In-Vivo experiments, the proposed DAQ system has been demonstrated to obtain high-quality neural activities from a rat's motor cortex and also greatly reduce recovery time from system saturation due to electrical microstimulation.

An Integrated Multi-Channel Biopotential Recording Analog Front-End IC With Area-Efficient Driven-Right-Leg Circuit

A multi-channel biopotential recording analog front-end (AFE) with a fully integrated area-efficient driven-right-leg (DRL) circuit is presented in this paper. The proposed AFE includes 10 channels of low-noise capacitive coupled instrumentation amplifier (CCIA), one shared 10-bit SAR ADC and a fully integrated DRL to enhance the system-level common-mode rejection ratio (CMRR). The proposed DRL circuit senses the common-mode at the CCIA output so that the AFE gain is reused as the DRL loop gain. Therefore, area efficient unit-gain buffer with small averaging capacitors can be used in DRL circuit to reduce the circuit area significantly. The proposed AFE has been implemented in a standard 0.18-μm CMOS process. The DRL circuit achieved more than 85% chip area reduction compared to the state-of-art on-chip DRL circuits and maximum 60 dB enhancement to system-level CMRR. Measurement results show high/low AFE gain of 60 dB/54 dB respectively with 1 μA/channel current consumption under 1.0 V power supply. The measured AFE input-referred noise in 1 Hz - 10k Hz range is 4.2 μV_rms and the maximum system-level CMRR is 110 dB.

A 2.64- μW 71-dB SNDR Discrete-Time Signal-Folding Amplifier for Reducing ADC's Resolution Requirement in Wearable ECG Acquisition Systems

This paper presents the design of a low-power discrete-time signal-folding amplifier intended for use in place of programmable-gain amplifiers (PGA) in electrocardiogram (ECG) acquisition systems. The amplifier provides a fixed high gain while preventing output signal saturation even with rail-to-rail inputs, thanks to the proposed discrete-time signal folding technique; the fixed gain eliminates the need of gain-control circuitry while the high gain helps relax the resolution requirement of the analog-to-digital converter (ADC) that follows, thus resulting in lower power consumption and design complexity for the ADC. Fabricated in a standard 0.18- μm CMOS process, the amplifier occupies an active area of 0.254 mm² and consumes 2.64  μW from a 1.2-V supply voltage. While amplifying a rail-to-rail input (2.4 V_pp differential) with a gain of 17.8 V/V, the amplifier achieves a signal-to-noise-plus-distortion ratio (SNDR) of 71 dB, thus making it very attractive for high-fidelity ECG recording amid large input interferences.

Can One Concurrently Record Electrical Spikes from Every Neuron in a Mammalian Brain?

The classic approach to measure the spiking response of neurons involves the use of metal electrodes to record extracellular potentials. Starting over 60 years ago with a single recording site, this technology now extends to ever larger numbers and densities of sites. We argue, based on the mechanical and electrical properties of existing materials, estimates of signal-to-noise ratios, assumptions regarding extracellular space in the brain, and estimates of heat generation by the electronic interface, that it should be possible to fabricate rigid electrodes to concurrently record from essentially every neuron in the cortical mantle. This will involve fabrication with existing yet nontraditional materials and procedures. We further emphasize the need to advance materials for improved flexible electrodes as an essential advance to record from neurons in brainstem and spinal cord in moving animals.

Human motor decoding from neural signals: a review

Many people suffer from movement disability due to amputation or neurological diseases. Fortunately, with modern neurotechnology now it is possible to intercept motor control signals at various points along the neural transduction pathway and use that to drive external devices for communication or control. Here we will review the latest developments in human motor decoding. We reviewed the various strategies to decode motor intention from human and their respective advantages and challenges. Neural control signals can be intercepted at various points in the neural signal transduction pathway, including the brain (electroencephalography, electrocorticography, intracortical recordings), the nerves (peripheral nerve recordings) and the muscles (electromyography). We systematically discussed the sites of signal acquisition, available neural features, signal processing techniques and decoding algorithms in each of these potential interception points. Examples of applications and the current state-of-the-art performance were also reviewed. Although great strides have been made in human motor decoding, we are still far away from achieving naturalistic and dexterous control like our native limbs. Concerted efforts from material scientists, electrical engineers, and healthcare professionals are needed to further advance the field and make the technology widely available in clinical use.

Design and testing of a 96-channel neural interface module for the Networked Neuroprosthesis system

Background

The loss of motor functions resulting from spinal cord injury can have devastating implications on the quality of one’s life. Functional electrical stimulation has been used to help restore mobility, however, current functional electrical stimulation (FES) systems require residual movements to control stimulation patterns, which may be unintuitive and not useful for individuals with higher level cervical injuries. Brain machine interfaces (BMI) offer a promising approach for controlling such systems; however, they currently still require transcutaneous leads connecting indwelling electrodes to external recording devices. While several wireless BMI systems have been designed, high signal bandwidth requirements limit clinical translation. Case Western Reserve University has developed an implantable, modular FES system, the Networked Neuroprosthesis (NNP), to perform combinations of myoelectric recording and neural stimulation for controlling motor functions. However, currently the existing module capabilities are not sufficient for intracortical recordings.

Methods

Here we designed and tested a 1 × 4 cm, 96-channel neural recording module prototype to fit within the specifications to mate with the NNP. The neural recording module extracts power between 0.3–1 kHz, instead of transmitting the raw, high bandwidth neural data to decrease power requirements.

Results

The module consumed 33.6 mW while sampling 96 channels at approximately 2 kSps. We also investigated the relationship between average spiking band power and neural spike rate, which produced a maximum correlation of R = 0.8656 (Monkey N) and R = 0.8023 (Monkey W).

Conclusion

Our experimental results show that we can record and transmit 96 channels at 2ksps within the power restrictions of the NNP system and successfully communicate over the NNP network. We believe this device can be used as an extension to the NNP to produce a clinically viable, fully implantable, intracortically-controlled FES system and advance the field of bioelectronic medicine.

A Sub- μW/Ch Analog Front-End for ∆-Neural Recording With Spike-Driven Data Compression

We present a fully implantable neural recording IC with a spike-driven data compression scheme to improve the power efficiency and preserve crucial data for monitoring brain activities. A difference between two consecutive neural signals, ∆-neural signal, is sampled in each channel to reduce the full dynamic range and the required resolution of an analog-to-digital converter (ADC), enabling the whole analog chain to be operated at a 0.5-V supply. A set of multiple ∆-signals are stored in analog memory to extract the magnitude and frequency features of the incoming neural signals, which are utilized to discriminate spikes in these signals instantaneously after the acquisition in the analog domain. The energy- and area-efficient successive approximation ADC is implemented and only converts detected spikes, decreasing the power dissipation and the amount of neural data. A prototype 16-channel neural interface IC was fabricated using a 0.18-μm CMOS process, and each component in the analog front-end was fully characterized. We successfully demonstrated precise spike detection through both in vitro and in vivo acquisition of the neural signal. The prototype chip consumed 0.88 μW/channel at a 0.5-V supply for the recording and compressed about 89% of neural data, saving the power consumption and bandwidth in the system.

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

Towards miniaturized closed-loop optogenetic stimulation devices

OBJECTIVE

Electrical brain stimulation provides therapeutic benefits for patients with drug-resistant neurological disorders. It, however, has restricted access to cell-type selectivity which limits its treatment effectiveness. Optogenetics, in contrast, enables precise targeting of a specific cell type which can address the issue with electrical brain stimulation. It, nonetheless, disregards real-time brain responses in delivering optimized stimulation to target cells. Closed-loop optogenetics, on the other hand, senses the difference between normal and abnormal states of the brain, and modulates stimulation parameters to achieve the desired stimulation outcome. Current review articles on closed-loop optogenetics have focused on its theoretical aspects and potential benefits. A review of the recent progress in miniaturized closed-loop optogenetic stimulation devices is thus needed.

APPROACH

This paper presents a comprehensive study on the existing miniaturized closed-loop optogenetic stimulation devices and their internal components.

MAIN RESULTS

Hardware components of closed-loop optogenetic stimulation devices including electrode, light-guiding mechanism, optical source, neural recorder, and optical stimulator are discussed. Next, software modules of closed-loop optogenetic stimulation devices including feature extraction, classification, control, and stimulation parameter modulation are described. Then, the existing devices are categorized into open-loop and closed-loop groups, and the combined operation of their neural recorder, optical stimulator, and control approach is discussed. Finally, the challenges in the design and implementation of closed-loop optogenetic stimulation devices are presented, suggestions on how to tackle these challenges are given, and future directions for closed-loop optogenetics are stated.

SIGNIFICANCE

A generic architecture for closed-loop optogenetic stimulation devices involving both hardware and software perspectives is devised. A comprehensive investigation into the most current miniaturized and tetherless closed-loop optogenetic stimulation devices is given. A detailed comparison of the closed-loop optogenetic stimulation devices is presented.

A 64-Channel Versatile Neural Recording SoC With Activity-Dependent Data Throughput

Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low-noise (2.1 V), low-power (23  W per analogue channel) neural recording system-on-chip (SoC). This features individually configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth, and sampling rate settings can be independently configured to extract local field potentials at a low data-rate and/or action potentials (APs) at a higher data rate. The sampled data are streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve 2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting coprocessor to provide a real-time (low latency) output. The system has been implemented in a commercially available 0.35-m CMOS technology occupying a silicon area of 19.1 mm (0.3 mm gross per channel), demonstrating a low-power and efficient architecture that could be further optimized by aggressive technology and supply voltage scaling.

Wireless induction coils embedded in diamond for power transfer in medical implants

Wireless power and data transfer to medical implants is a research area where improvements in current state-of-the-art technologies are needed owing to the continuing efforts for miniaturization. At present, lithographical patterning of evaporated metals is widely used for miniature coil fabrication. This method produces coils that are limited to low micron or nanometer thicknesses leading to high impedance values and thus limiting their potential quality. In the present work we describe a novel technique, whereby trenches were milled into a diamond substrate and filled with silver active braze alloy, enabling the manufacture of small, high cross-section, low impedance microcoils capable of transferring up to 10 mW of power up to a distance of 6 mm. As a substitute for a metallic braze line used for hermetic sealing, a continuous metal loop when placed parallel and close to the coil surface reduced power transfer efficiency by 43%, but not significantly, when placed perpendicular to the microcoil surface. Encapsulation of the coil by growth of a further layer of diamond reduced the quality factor by an average of 38%, which can be largely avoided by prior oxygen plasma treatment. Furthermore, an accelerated ageing test after encapsulation showed that these coils are long lasting. Our results thus collectively highlight the feasibility of fabricating a high-cross section, biocompatible and long lasting miniaturized microcoil that could be used in either a neural recording or neuromuscular stimulation device.

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor

This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

A Bidirectional Neural Interface IC With Chopper Stabilized BioADC Array and Charge Balanced Stimulator

We present a bidirectional neural interface with a 4-channel biopotential analog-to-digital converter (bioADC) and a 4-channel current-mode stimulator in 180 nm CMOS. The bioADC directly transduces microvolt biopotentials into a digital representation without a voltage-amplification stage. Each bioADC channel comprises a continuous-time first-order ∆Σ modulator with a chopper-stabilized OTA input and current feedback, followed by a second-order comb-filter decimator with programmable oversampling ratio. Each stimulator channel contains two independent digital-to-analog converters for anodic and cathodic current generation. A shared calibration circuit matches the amplitude of the anodic and cathodic currents for charge balancing. Powered from a 1.5 V supply, the analog and digital circuits in each recording channel draw on average [Formula: see text] and [Formula: see text] of supply current, respectively. The bioADCs achieve an SNR of [Formula: see text] and a SFDR of [Formula: see text] , for better than 9-b ENOB. Intracranial EEG recordings from an anesthetized rat are shown and compared to simultaneous recordings from a commercial reference system to validate performance in-vivo . Additionally, we demonstrate bidirectional operation by recording cardiac modulation induced through vagus nerve stimulation, and closed-loop control of cardiac rhythm. The micropower operation, direct digital readout, and integration of electrical stimulation circuits make this interface ideally suited for closed-loop neuromodulation applications.

An ultra low-power front-end IC for wearable health monitoring system

This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

A 200-Channel Area-Power-Efficient Chemical and Electrical Dual-Mode Acquisition IC for the Study of Neurodegenerative Diseases

Microelectrode array (MEA) can be used in the study of neurodegenerative diseases by monitoring the chemical neurotransmitter release and the electrical potential simultaneously at the cellular level. Currently, the MEA technology is migrating to more electrodes and higher electrode density, which raises power and area constraints on the design of acquisition IC. In this paper, we report the design of a 200-channel dual-mode acquisition IC with highly efficient usage of power and area. Under the constraints of target noise and fast settling, the current channel design saves power by including a novel current buffer biased in discrete time (DT) before the TIA (transimpedance amplifier). The 200 channels are sampled at 20 kS/s and quantized by column-wise SAR ADCs. The prototype IC was fabricated in a 0.18 μm CMOS process. Silicon measurements show the current channel has 21.6 pArms noise with cyclic voltammetry (CV) and 0.48 pArms noise with constant amperometry (CA) while consuming 12.1 μW . The voltage channel has 4.07 μVrms noise in the bandwidth of 100 kHz and 0.2% nonlinearity while consuming 9.1 μW. Each channel occupies 0.03 mm(2) area, which is among the smallest.

A real-time spike classification method based on dynamic time warping for extracellular enteric neural recording with large waveform variability

BACKGROUND

Computationally efficient spike recognition methods are required for real-time analysis of extracellular neural recordings. The enteric nervous system (ENS) is important to human health but less well-understood with few appropriate spike recognition algorithms due to large waveform variability.

NEW METHOD

Here we present a method based on dynamic time warping (DTW) with high tolerance to variability in time and magnitude. Adaptive temporal gridding for "fastDTW" in similarity calculation significantly reduces the computational cost. The automated threshold selection allows for real-time classification for extracellular recordings.

RESULTS

Our method is first evaluated on synthesized data at different noise levels, improving both classification accuracy and computational complexity over the conventional cross-correlation based template-matching method (CCTM) and PCA+k-means clustering without time warping. Our method is then applied to analyze the mouse enteric neural recording with mechanical and chemical stimuli. Successful classification of biphasic and monophasic spikes is achieved even when the spike variability is larger than millisecond in width and millivolt in magnitude.

COMPARISON WITH EXISTING METHOD(S)

In comparison with conventional template matching and clustering methods, the fastDTW method is computationally efficient with high tolerance to waveform variability.

CONCLUSIONS

We have developed an adaptive fastDTW algorithm for real-time spike classification of ENS recording with large waveform variability against colony motility, ambient changes and cellular heterogeneity.

Active C4 Electrodes for Local Field Potential Recording Applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

Enabling Low-Power, Multi-Modal Neural Interfaces Through a Common, Low-Bandwidth Feature Space

Brain-Machine Interfaces (BMIs) have shown great potential for generating prosthetic control signals. Translating BMIs into the clinic requires fully implantable, wireless systems; however, current solutions have high power requirements which limit their usability. Lowering this power consumption typically limits the system to a single neural modality, or signal type, and thus to a relatively small clinical market. Here, we address both of these issues by investigating the use of signal power in a single narrow frequency band as a decoding feature for extracting information from electrocorticographic (ECoG), electromyographic (EMG), and intracortical neural data. We have designed and tested the Multi-modal Implantable Neural Interface (MINI), a wireless recording system which extracts and transmits signal power in a single, configurable frequency band. In prerecorded datasets, we used the MINI to explore low frequency signal features and any resulting tradeoff between power savings and decoding performance losses. When processing intracortical data, the MINI achieved a power consumption 89.7% less than a more typical system designed to extract action potential waveforms. When processing ECoG and EMG data, the MINI achieved similar power reductions of 62.7% and 78.8%. At the same time, using the single signal feature extracted by the MINI, we were able to decode all three modalities with less than a 9% drop in accuracy relative to using high-bandwidth, modality-specific signal features. We believe this system architecture can be used to produce a viable, cost-effective, clinical BMI.

A Neuromorphic Event-Based Neural Recording System for Smart Brain-Machine-Interfaces

Neural recording systems are a central component of Brain-Machince Interfaces (BMIs). In most of these systems the emphasis is on faithful reproduction and transmission of the recorded signal to remote systems for further processing or data analysis. Here we follow an alternative approach: we propose a neural recording system that can be directly interfaced locally to neuromorphic spiking neural processing circuits for compressing the large amounts of data recorded, carrying out signal processing and neural computation to extract relevant information, and transmitting only the low-bandwidth outcome of the processing to remote computing or actuating modules. The fabricated system includes a low-noise amplifier, a delta-modulator analog-to-digital converter, and a low-power band-pass filter. The bio-amplifier has a programmable gain of 45-54 dB, with a Root Mean Squared (RMS) input-referred noise level of 2.1 μV, and consumes 90 μW . The band-pass filter and delta-modulator circuits include asynchronous handshaking interface logic compatible with event-based communication protocols. We describe the properties of the neural recording circuits, validating them with experimental measurements, and present system-level application examples, by interfacing these circuits to a reconfigurable neuromorphic processor comprising an array of spiking neurons with plastic and dynamic synapses. The pool of neurons within the neuromorphic processor was configured to implement a recurrent neural network, and to process the events generated by the neural recording system in order to carry out pattern recognition.

A new architecture for neural signal amplification in implantable brain machine interfaces

This paper reports a new architecture for variable gain-bandwidth amplification of neural signals to be used in implantable multi-channel recording systems. The two most critical requirements in such a front-end circuit are low power consumption and chip area, especially as number of channels increases. The presented architecture employs a single super-performing amplifier, with tunable gain and bandwidth, combined with several low-key preamplifiers and multiplexors for multi-channel recordings. This is in contrast to using copies of high performing amplifier for each channel as is typically reported in earlier literature. The resulting circuits consume lower power and require smaller area as compared to existing designs. Designed in 0.5 µmCMOS, the 8-channel prototype can simultaneously record Local Field Potentials and neural spikes, with an effective power consumption of 3.5 µW per channel and net core area of 0.407 mm(2).

A High Performance Delta-Sigma Modulator for Neurosensing

Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-μm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 μW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor

This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency = 90%).The low-voltage amplifier together with its power management circuitry is implemented in a standard 0.18 μm CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor (NEF=1.74) and power efficiency factor (PEF=1.05). Experiments show that the amplifier core can provide a noise level of 0.34 μVrms in a 0.7 to 182 Hz band, consuming 1.17 μW power. The amplifier together with its power management circuitry consumes 1.56 μW, achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements.

Wireless gigabit data telemetry for large-scale neural recording

Implantable wireless neural recording from a large ensemble of simultaneously acting neurons is a critical component to thoroughly investigate neural interactions and brain dynamics from freely moving animals. Recent researches have shown the feasibility of simultaneously recording from hundreds of neurons and suggested that the ability of recording a larger number of neurons results in better signal quality. This massive recording inevitably demands a large amount of data transfer. For example, recording 2000 neurons while keeping the signal fidelity ( > 12 bit, > 40 KS/s per neuron) needs approximately a 1-Gb/s data link. Designing a wireless data telemetry system to support such (or higher) data rate while aiming to lower the power consumption of an implantable device imposes a grand challenge on neuroscience community. In this paper, we present a wireless gigabit data telemetry for future large-scale neural recording interface. This telemetry comprises of a pair of low-power gigabit transmitter and receiver operating at 60 GHz, and establishes a short-distance wireless link to transfer the massive amount of neural signals outward from the implanted device. The transmission distance of the received neural signal can be further extended by an externally rendezvous wireless transceiver, which is less power/heat-constraint since it is not at the immediate proximity of the cortex and its radiated signal is not seriously attenuated by the lossy tissue. The gigabit data link has been demonstrated to achieve a high data rate of 6 Gb/s with a bit-error-rate of 10(-12) at a transmission distance of 6 mm, an applicable separation between transmitter and receiver. This high data rate is able to support thousands of recording channels while ensuring a low energy cost per bit of 2.08 pJ/b.

A compact and autoclavable system for acute extracellular neural recording and brain pressure monitoring for humans

One of the most difficult tasks for the surgeon during the removal of low-grade gliomas is to identify as precisely as possible the borders between functional and non-functional brain tissue with the aim of obtaining the maximal possible resection which allows to the patient the longer survival. For this purpose, systems for acute extracellular recordings of single neuron and multi-unit activity are considered promising. Here we describe a system to be used with 16 microelectrodes arrays that consists of an autoclavable headstage, a built-in inserter for precise electrode positioning and a system that measures and controls the pressure exerted by the headstage on the brain with a twofold purpose: to increase recording stability and to avoid disturbance of local perfusion which would cause a degradation of the quality of the recording and, eventually, local ischemia. With respect to devices where only electrodes are autoclavable, our design permits the reduction of noise arising from long cable connections preserving at the same time the flexibility and avoiding long-lasting gas sterilization procedures. Finally, size is much smaller and set up time much shorter compared to commercial systems currently in use in surgery rooms, making it easy to consider our system very useful for intra-operatory mapping operations.

An integrated power, area and noise efficient AFE for large scale multichannel neural recording systems

A wideband, low-power, low-noise and area-efficient analog front-end (AFE) for acquiring neural signals is described. The AFE builds upon existing architectures but uses block-wise optimization to achieve superior performance when used in a multichannel system with scalable channel count. The AFE is also the first of its kind to enable acquisition from extended neural bandwidths greater than 10 kHz. The AFE is designed in 65 nm CMOS technology and consumes 11.3 μW of power while occupying 0.06 mm(2) per channel and delivering an NEF of 2.92.

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm²) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μV_rms in the action-potential band (300 Hz-10 kHz) and 5.4 μV_rms in the local-field-potential band (1 Hz-300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures.

A frequency shaping neural recorder with 3 pF input capacitance and 11 plus 4.5 bits dynamic range

This paper presents a frequency-shaping (FS) neural recording architecture and its implementation in a 0.13 μ m CMOS process. Compared with its conventional counterpart, the proposed architecture inherently rejects electrode offset, increases input impedance 5-10 fold, compresses neural data dynamic range (DR) by 4.5-bit, simultaneously records local field potentials (LFPs) and extracellular spikes, and is more suitable for long-term recording experiments. Measured at a 40 kHz sampling clock and ± 0.6 V supply, the recorder consumes 50 μW/ch, of which 22 μW per FS amplifier, 24 μ W per buffer, 4 μ W per 11-bit successive approximation register analog-to-digital converter (SAR ADC). The input-referred noise for LFPs and extracellular spikes are 13 μ Vrms and 7 μVrms, respectively, which are sufficient to achieve high-fidelity full-spectrum neural data. In addition, the designed recorder has a 3 pF input capacitance and allows " 11+4.5"-bit neural data DR without system saturation, where the extra 4.5-bit owes to the FS technique. Its figure-of-merit (FOM) based on data DR reaches 36.0 fJ/conversion-step.

Minimum requirements for accurate and efficient real-time on-chip spike sorting

BACKGROUND

Extracellular recordings are performed by inserting electrodes in the brain, relaying the signals to external power-demanding devices, where spikes are detected and sorted in order to identify the firing activity of different putative neurons. A main caveat of these recordings is the necessity of wires passing through the scalp and skin in order to connect intracortical electrodes to external amplifiers. The aim of this paper is to evaluate the feasibility of an implantable platform (i.e., a chip) with the capability to wirelessly transmit the neural signals and perform real-time on-site spike sorting.

NEW METHOD

We computationally modelled a two-stage implementation for online, robust, and efficient spike sorting. In the first stage, spikes are detected on-chip and streamed to an external computer where mean templates are created and sent back to the chip. In the second stage, spikes are sorted in real-time through template matching.

RESULTS

We evaluated this procedure using realistic simulations of extracellular recordings and describe a set of specifications that optimise performance while keeping to a minimum the signal requirements and the complexity of the calculations.

COMPARISON WITH EXISTING METHODS

A key bottleneck for the development of long-term BMIs is to find an inexpensive method for real-time spike sorting. Here, we simulated a solution to this problem that uses both offline and online processing of the data.

CONCLUSIONS

Hardware implementations of this method therefore enable low-power long-term wireless transmission of multiple site extracellular recordings, with application to wireless BMIs or closed-loop stimulation designs.

A 515 nW, 0-18 dB Programmable Gain Analog-to-Digital Converter for In-Channel Neural Recording Interfaces

This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter (PG-ADC) suitable for in-channel neural recording applications. The PG-ADC uses a novel implementation of the binary search algorithm that is complemented with adaptive biasing techniques for power saving. It has been fabricated in a standard CMOS 130 nm technology and only occupies 0.0326 mm(2). The PG-ADC has been optimized to operate under two different sampling modes, 27 kS/s and 90 kS/s. The former is tailored for raw data conversion of neural activity, whereas the latter is used for the on-the-fly feature extraction of neural spikes. Experimental results show that, under a voltage supply of 1.2 V, the PG-ADC obtains an ENOB of 7.56 bit (8-bit output) for both sampling modes, regardless of the gain setting. The amplification gain can be programmed from 0 to 18 dB. The power consumption of the PG-ADC at 90 kS/s is 1.52 μW with a FoM of 89.49 fJ/conv, whereas at 27 kS/s it consumes 515 nW and obtains a FoM of 98.31 fJ/conv .

A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants

This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

An analogue front-end model for developing neural spike sorting systems

In spike sorting systems, front-end electronics is a crucial pre-processing step that not only has a direct impact on detection and sorting accuracy, but also on power and silicon area. In this work, a behavioural front-end model is proposed to assess the impact of the design parameters (including signal-to-noise ratio, filter type/order, bandwidth, converter resolution/rate) on subsequent spike processing. Initial validation of the model is provided by applying a test stimulus to a hardware platform and comparing the measured circuit response to the expected from the behavioural model. Our model is then used to demonstrate the effect of the Analogue Front-End (AFE) on subsequent spike processing by testing established spike detection and sorting methods on a selection of systems reported in the literature. It is revealed that although these designs have a wide variation in design parameters (and thus also circuit complexity), the ultimate impact on spike processing performance is relatively low (10-15%). This can be used to inform the design of future systems to have an efficient AFE whilst also maintaining good processing performance.

Data compression in brain-machine/computer interfaces based on the Walsh-Hadamard transform

This paper reports on the application of the Walsh-Hadamard transform (WHT) for data compression in brain-machine/brain-computer interfaces. Using the proposed technique, the amount of the neural data transmitted off the implant is compressed by a factor of at least 63 at the expense of as low as 4.66% RMS error between the signal reconstructed on the external host and the original neural signal on the implant side. Based on the proposed idea, a 128-channel WHT processor was designed in a 0.18- μm CMOS process occupying 1.64 mm(2) of silicon area. The circuit consumes 81 μW (0.63 μW per channel) from a 1.8-V power supply at 250 kHz. A prototype of the proposed processor was implemented and successfully tested using prerecorded neural signals.

A 0.45 V 100-channel neural-recording IC with sub- μW/channel consumption in 0.18 μm CMOS

Neural prosthetics and personal healthcare have increasing need of high channel density low noise low power neural sensor interfaces. The input referred noise and quantization resolution are two essential factors which prevent conventional neural sensor interfaces from simultaneously achieving a good noise efficiency factor and low power consumption. In this paper, a neural recording architecture with dynamic range folding and current reuse techniques is proposed and dedicated to solving the noise and dynamic range trade-off under low voltage low power operation. Measured results from the silicon prototype show that the proposed design achieves 3.2 μVrms input referred noise and 8.27 effective number of bits at only 0.45 V supply and 0.94 μW/channel power consumption.

Design and implementation of a wireless in-ovo EEG/EMG recorder

The developmental origins of sleep and brain activity rhythms in higher vertebrate animals (birds and mammals) are currently unknown. In order to create an experimental system in which these could be better elucidated, we designed, built and tested a system for recording EEG and EMG signals in-ovo from chicken embryos incubated for 16-21 days. This system can remain attached to the individual subject through the process of hatching and continue to be worn post-natally. Electrode wires surgically implanted on the head of the embryo are connected to a battery-operated ultraportable transmitter which can either be attached to the eggshell or worn on the back. The transmitter processes up to 6 channels of data with a maximum sampling frequency of 500 Hz and a resolution of 12 bits. The radio link uses a carrier frequency of 4 MHz, and has a maximum transfer rate of 500 kbit/s; receiving antennas compatible with both in-egg recordings and post-natal recordings from freely-moving birds were produced. A receiver connected with one USB port of a PC transmits the data for digital storage. This system is based on discrete, off-the-shelf components, can provide a few days of continuous operation with a single lithium coin battery, and has a noise floor level of 0.35 μV. The transmitter dimensions are 16 × 13 × 1.5 mm and the weight without the battery is 0.7 g. The microprocessor allows flexible operation modes not usually made available in other small multichannel acquisition systems implemented by means of ad hoc mixed signal chips.

15-nW Biopotential LPFs in 0.35- μm CMOS using subthreshold-source-follower Biquads with and without gain compensation

Most biopotential readout front-ends rely on the g m- C lowpass filter (LPF) for forefront signal conditioning. A small g m realizes a large time constant ( τ = C / g m) suitable for ultra-low-cutoff filtering, saving both power and area. Yet, the noise and linearity can be compromised, given that each g m cell can involve one or several noisy and nonlinear V- I conversions originated from the active devices. This paper proposes the subthreshold-source-follower (SSF) Biquad as a prospective alternative. It features: 1) a very small number of active devices reducing the noise and nonlinearity footsteps; 2) No explicit feedback in differential implementation, and 3) extension of filter order by cascading. This paper presents an in-depth treatment of SSF Biquad in the nW-power regime, analyzing its power and area tradeoffs with gain, linearity and noise. A gain-compensation (GC) scheme addressing the gain-loss problem of NMOS-based SSF Biquad due to the body effect is also proposed. Two 100-Hz 4th-order Butterworth LPFs using the SSF Biquads with and without GC were fabricated in 0.35- μm CMOS. Measurement results show that the non-GC (GC) LPF can achieve a DC gain of -3.7 dB (0 dB), an input-referred noise of 36 μV rms (29 μV rms ), a HD3@60 Hz of -55.2 dB ( - 60.7 dB) and a die size of 0.11 mm² (0.08 mm²). Both LPFs draw 15 nW at 3 V. The achieved figure-of-merits (FoMs) are favorably comparable with the state-of-the-art.

A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

Efficient universal computing architectures for decoding neural activity

The ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain– machine interfaces (BMIs). Such systems require input from tens to hundreds of brain-implanted recording electrodes in order to deliver robust and accurate performance; in serving that primary function they should also minimize power dissipation in order to avoid damaging neural tissue; and they should transmit data wirelessly in order to minimize the risk of infection associated with chronic, transcutaneous implants. Electronic architectures for brain– machine interfaces must therefore minimize size and power consumption, while maximizing the ability to compress data to be transmitted over limited-bandwidth wireless channels. Here we present a system of extremely low computational complexity, designed for real-time decoding of neural signals, and suited for highly scalable implantable systems. Our programmable architecture is an explicit implementation of a universal computing machine emulating the dynamics of a network of integrate-and-fire neurons; it requires no arithmetic operations except for counting, and decodes neural signals using only computationally inexpensive logic operations. The simplicity of this architecture does not compromise its ability to compress raw neural data by factors greater than . We describe a set of decoding algorithms based on this computational architecture, one designed to operate within an implanted system, minimizing its power consumption and data transmission bandwidth; and a complementary set of algorithms for learning, programming the decoder, and postprocessing the decoded output, designed to operate in an external, nonimplanted unit. The implementation of the implantable portion is estimated to require fewer than 5000 operations per second. A proof-of-concept, 32-channel field-programmable gate array (FPGA) implementation of this portion is consequently energy efficient. We validate the performance of our overall system by decoding electrophysiologic data from a behaving rodent.