TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Semiconductor devices used in radiation environment are more prone to degradation in device performance. Junctionless Tunnel Field Effect Transistor (JLTFET) is one of the most potential candidates which overcomes the short channel effects and fabrication difficulties. In this work, 20 nm JLTFET is proposed with Silicon in the drain/channel region whereas source uses different materials, Silicon Germanium (SiGe), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Indium Arsenide (InAs). The device performance is examined by subjecting it to heavy ion radiation at a lower and higher dose of linear energy transfer (LET) values. It can be seen that the most sensitive location is the source/channel (S/C) interface for SiGe, GaN and GaAs whereas the drain/channel (D/C) interface for InAs. Further analysis is carried out at these vulnerable regions by matching ION of all materials. The parameters, transient peak current (Ipeak), collected charge (QC), threshold voltage shift (ΔVth) and bipolar gain (β) are extracted using transient simulations. It is observed that for a lower dose of LET, Ipeak of SiGe is 27% lesser than InAs and for higher dose of LET, SiGe shows 56% lesser Ipeak than InAs. SiGe is less sensitive at lower and higher dose of LET due to reduced ΔVth, tunneling and electron density.

A 77 GHz Power Amplifier with 19.1 dBm Peak Output Power in 130 nm SiGe Process

This article reports a two-stage differential structure power amplifier based on a 130 nm SiGe process operating at 77 GHz. By introducing a tunable capacitor for amplitude and phase balance at the center tap of the secondary coil of the traditional Marchand balun, the balun achieves amplitude imbalance less than 0.5 dB and phase imbalance less than 1 degree within the operating frequency range of 70-85 GHz, which enables the power amplifier to exhibit comparable output power over a wide operating frequency band. The power amplifier, based on a designed 3-bit digital analog convertor (DAC)-controlled base bias current source, exhibits small signal gain fluctuation of less than 5 dB and saturation output power fluctuation of less than 2 dB near the 80 GHz frequency point when the ambient temperature varies in the range of -40 °C to 125 °C. Benefiting from the aforementioned design, the tested single-path differential power amplifier exhibits a small signal gain exceeding 16 dB, a saturation output power exceeding 18 dBm, and a peak saturation output power of 19.1 dBm in the frequency band of 70-85 GHz.

A 40-50 GHz RF Front-End with Integrated Local Oscillator Leakage Calibration

This article presents a transmitter (TX) front-end operating at frequencies covering 40-50 GHz, including a differential quadrature mixer with integrated amplitude and phase imbalance tuning, a power amplifier, and a detection mixer (DM) that supports local oscillator (LO) leakage signal or image signal calibration. Benefiting from the amplitude and phase imbalance tuning network of the in-phase quadrature (IQ) signal generator at the LO input, the TX exhibits more than 30 dBc image signal rejection over the full frequency band without any post-calibration. Based on the LO leakage signal fed back by the DM integrated at the RF output, the LO leakage of the TX has been improved by more than 10 dB through the LO leakage calibration module integrated in the quadrature mixer. When the intermediate frequency (IF) signal is fixed at 1 GHz, the TX's 1 dB compressed output power (OP1 dB) is higher than 13.5 dBm over the operating band. Thanks to the LO leakage signal calibration unit and the IQ signal generator, the TX is compliant with the error vector magnitude (EVM) requirement of the IEEE 802.11aj standard up to the 64-quadrature amplitude modulation (QAM) operating mode.

Bilateral sidewall engineering Si1-xGexiTFET for low power display application. Nanotechnology 2023;34:505202. [PMID: 37708870 DOI: 10.1088/1361-6528/acf9ab] [Citation(s) in RCA: 0] [Impact Index Per Article: 0]

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve theION, resulting in a lower subthreshold swing average (S.Savg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that theS.Savgis improved to 21.5 mV dec-1with anION/IOFFratio of 106 atVD= 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec-1has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

A 17.8-20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers

This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use in receive phased arrays for the gateways of major low Earth orbit (LEO) constellations that operate in the 17.8 to 20.2 GHz frequency range. The proposed architecture uses four variable gain amplifiers (VGA) that are active at any given time and are switched to generate the four quadrants. Compared to conventional architectures, this structure is more compact and produces double the output amplitude. The design offers 6-bit phase control for 360°, and the total root mean square (RMS) phase and gain errors are 2.36° and 1.46 dB, respectively. The design occupies an area of 1309.4 μm × 1783.8 μm (including pads).

High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET

This research presents the optimization and proposal of P- and N-type 3-stacked Si_0.8Ge_0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si_0.8Ge_0.2 FinFET, and Si_0.8Ge_0.2/Si SL FinFET, were comprehensively compared with HfO₂ = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si_0.8Ge_0.2/Si SL FinFET exhibited the lowest average subthreshold slope (SS_avg) of 88 mV/dec, the highest maximum transconductance (G_{m, max}) of 375.2 μS/μm, and the highest ON-OFF current ratio (I_ON/I_OFF), approximately 10⁶ at V_OV = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal-oxide-semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si_0.8Ge_0.2/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si_0.8Ge_0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.

Engineering of dense arrays of Vertical Si1-xGexnanostructures

Vertical nanostructure technologies are becoming more important for the down scaling of nanoelectronic devices such as logic transistors or memories. Such devices require dense vertical nanostructured channel arrays (VNCA) that can be fabricated through a top-down approach based on group IV materials. We present progresses on the top-down fabrication of highly anisotropic and ultra-dense Si_1-xGe_x(x= 0, 0.2, 0.5) VNCAs. Dense nanowire and nanosheet patterns were optimized through high resolution lithography and transferred onto Si_1-xGe_xsubstrates by anisotropic reactive ion etching with a fluorine chemistry. The right gas mixtures for a given Ge content resulted in perfectly vertical and dense arrays. Finally we fabricated oxide shell/SiGe core heterostructures by dry- and wet-thermal oxidation and evaluated their applicability for nanostructure size engineering, as already established for silicon nanowires. The impact of the nanostructured shape (wire or sheet), size and Ge content on the oxide growth were investigated and analysed in detail through transmission electron microscopy.

Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET)

We have demonstrated the method of threshold voltage (V_T) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET. Single WFM shared gate N1 CFET was used to study and emphasize the V_T tunability of the proposed Ge content method. The result reveals that the Ge mole fraction influences V_TP of 5 mV/Ge%, and a close result can also be obtained from the energy band configuration of Si_1-xGe_x. Additionally, the single WFM shared gate N1 CFET inverter with V_T adjusted by the Ge content method presents a well-designed voltage transfer curve, and its inverter transient response is also presented. Furthermore, the designed CFET inverter is used to construct a well-behaved 6T-SRAM with a large SNM of ~120 mV at V_DD of 0.5 V.

Hexagonal silicon-germanium nanowire branches with tunable composition

Hexagonal SiGe-2H has been recently shown to have a direct bandgap, and holds the promise to be compatible with silicon technology. Hexagonal Si and Ge have been grown on an epitaxial lattice matched template consisting of wurtzite GaP and GaAs, respectively. Here, we present the growth of hexagonal Si and SiGe nanowire branches grown from a wurtzite stem by the vapor-liquid-solid growth mode, which is substantiated byin situtransmission electron microscopy. We show that the composition can be tuned through the whole range of stoichiometry from Si to Ge, and the possibility to realize Si and SiGe heterostructures in these branches.

The Diffusion Mechanism of Ge During Oxidation of Si/SiGe Nanofins

A recently discovered, enhanced Ge diffusion mechanism along the oxidizing interface of Si/SiGe nanostructures has enabled the formation of single-crystal Si nanowires and quantum dots embedded in a defect-free, single-crystal SiGe matrix. Here, we report oxidation studies of Si/SiGe nanofins aimed at gaining a better understanding of this novel diffusion mechanism. A superlattice of alternating Si/Si_0.7Ge_0.3 layers was grown and patterned into fins. After oxidation of the fins, the rate of Ge diffusion down the Si/SiO₂ interface was measured through the analysis of HAADF-STEM images. The activation energy for the diffusion of Ge down the sidewall was found to be 1.1 eV, which is less than one-quarter of the activation energy previously reported for Ge diffusion in bulk Si. Through a combination of experiments and DFT calculations, we propose that the redistribution of Ge occurs by diffusion along the Si/SiO₂ interface followed by a reintroduction into substitutional positions in the crystalline Si.

Advanced preparation of plan-view specimens on a MEMS chip for in situ TEM heating experiments

In situ transmission electron microscopy (TEM) is a powerful tool for advanced material characterization. It allows real-time observation of structural evolution at the atomic level while applying different stimuli such as heat. However, the validity of analysis strongly depends on the quality of the specimen, which has to be prepared by thinning the bulk material to electron transparency while maintaining the pristine properties. To address this challenge, a novel method of TEM samples preparation in plan-view geometry was elaborated based on the combination of the wedge polishing technique and an enhanced focused ion beam (FIB) workflow. It involves primary mechanical thinning of a broad sample area from the backside followed by FIB-assisted installation on the MEMS-based sample carrier. The complete step-by-step guide is provided, and the method's concept is discussed in detail making it easy to follow and adapt for diverse equipment. The presented approach opens the world of in situ TEM heating experiments for a vast variety of fragile materials. The principle and significant advantage of the proposed method are demonstrated by new insights into the stability and thermal-induced strain relaxation of Ge Stranski-Krastanov islands on Si during in situ TEM heating.

SUPPLEMENTARY INFORMATION

The online version contains supplementary material available at 10.1557/s43577-021-00255-5.

Thermally propagated Al contacts on SiGe nanowires characterized by electron beam induced current in a scanning transmission electron microscope

Here, we use electron beam induced current (EBIC) in a scanning transmission electron microscope to characterize the structure and electronic properties of Al/SiGe and Al/Si-rich/SiGe axial nanowire heterostructures fabricated by thermal propagation of Al in a SiGe nanowire. The two heterostructures behave as Schottky contacts with different barrier heights. From the sign of the beam induced current collected at the contacts, the intrinsic semiconductor doping is determined to be n-type. Furthermore, we find that the silicon-rich double interface presents a lower barrier height than the atomically sharp SiGe/Al interface. With an applied bias, the Si-rich region delays the propagation of the depletion region and presents a reduced free carrier diffusion length with respect to the SiGe nanowire. This behaviour could be explained by a higher residual doping in the Si-rich area. These results demonstrate that scanning transmission electron microscopy EBIC is a powerful method for mapping and quantifying electric fields in micrometer- and nanometer-scale devices.

Process Steps for High Quality Si-Based Epitaxial Growth at Low Temperature via RPCVD

The key process steps for growing high-quality Si-based epitaxial films via reduced pressure chemical vapor deposition (RPCVD) are investigated herein. The quality of the epitaxial films is largely affected by the following steps in the epitaxy process: ex-situ cleaning, in-situ bake, and loading conditions such as the temperature and gaseous environment. With respect to ex-situ cleaning, dry cleaning is found to be more effective than wet cleaning in 1:200 dilute hydrofluoric acid (DHF), while wet cleaning in 1:30 DHF is the least effective. However, the best results of all are obtained via a combination of wet and dry cleaning. With respect to in-situ hydrogen bake in the presence of H₂ gas, the level of impurities is gradually decreased as the temperature increases from 700 °C to a maximum of 850 °C, at which no peaks of O and F are observed. Further, the addition of a hydrogen chloride (HCl) bake step after the H₂ bake results in effective in-situ bake even at temperatures as low as 700 °C. In addition, the effects of temperature and environment (vacuum or gas) at the time of loading the wafers into the process chamber are compared. Better quality epitaxial films are obtained when the samples are loaded into the process chamber at low temperature in a gaseous environment. These results indicate that the epitaxial conditions must be carefully tuned and controlled in order to achieve high-quality epitaxial growth.

Study of the Cross-Influence between III-V and IV Elements Deposited in the Same MOVPE Growth Chamber

We have deposited Ge, SiGe, SiGeSn, AlAs, GaAs, InGaP and InGaAs based structures in the same metalorganic vapor phase epitaxy (MOVPE) growth chamber, in order to study the effect of the cross influence between groups IV and III-V elements on the growth rate, background doping and morphology. It is shown that by adopting an innovative design of the MOVPE growth chamber and proper growth condition, the IV elements growth rate penalization due to As "carry over" can be eliminated and the background doping level in both IV and III-V semiconductors can be drastically reduced. In the temperature range 748-888 K, Ge and SiGe morphologies do not degrade when the semiconductors are grown in a III-V-contaminated MOVPE growth chamber. Critical morphology aspects have been identified for SiGeSn and III-Vs, when the MOVPE deposition takes place, respectively, in a As or Sn-contaminated MOVPE growth chamber. III-Vs morphologies are influenced by substrate type and orientation. The results are promising in view of the monolithic integration of group-IV with III-V compounds in multi-junction solar cells.

Numerical Study of the Coupling of Sub-Terahertz Radiation to n-Channel Strained-Silicon MODFETs

This paper reports on a study of the response of a T-gate strained-Si MODFETs (modulation-doped field-effect transistor) under continuous-wave sub-THz excitation. The sub-THz response was measured using a two-tones solid-state source at 0.15 and 0.30 THz. The device response in the photovoltaic mode was non-resonant, in agreement with the Dyakonov and Shur model for plasma waves detectors. The maximum of the photoresponse was clearly higher under THz illumination at 0.15 THz than at 0.3 THz. A numerical study was conducted using three-dimensional (3D) electromagnetic simulations to delve into the coupling of THz radiation to the channel of the transistor. 3D simulations solving the Maxwell equations using a time-domain solver were performed. Simulations considering the full transistor structure, but without taking into account the bonding wires used to contact the transistor pads in experiments, showed an irrelevant role of the gate length in the coupling of the radiation to the device channel. Simulations, in contradiction with measurements, pointed to a better response at 0.3 THz than under 0.15 THz excitation in terms of the normalized electric field inside the channel. When including four 0.25 mm long bonding wires connected to the contact pads on the transistor, the normalized internal electric field induced along the transistor channel by the 0.15 THz beam was increased in 25 dB, revealing, therefore, the important role played by the bonding wires at this frequency. As a result, the more intense response of the transistor at 0.15 THz than at 0.3 THz experimentally found, must be attributed to the bonding wires.

Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon-Germanium Multilayers Structures for Vertical Transistors Application

Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si_0.93Ge_0.07 spacers on both sides of P-doped Si layers, and substituting SiH₄ by SiH₂Cl₂ (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si_0.93Ge_0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

Transient Electrical and Optical Characteristics of Electron and Proton Irradiated SiGe Detectors

The particle detector degradation mainly appears through decrease of carrier recombination lifetime and manifestation of carrier trapping effects related to introduction of carrier capture and emission centers. In this work, the carrier trap spectroscopy in Si_1−xGe_x structures, containing either 1 or 5% of Ge, has been performed by combining the microwave probed photoconductivity, pulsed barrier capacitance transients and spectra of steady-state photo-ionization. These characteristics were examined in pristine, 5.5 MeV electron and 1.6 MeV proton irradiated Si and SiGe diodes with n⁺p structure.

High-Ge-Content SiGe Alloy Single Crystals Using the Nanomembrane Platform

The growth of single crystals of Ge-rich SiGe alloys in an extended composition range is demonstrated using the nanomembrane (NM) platform and III-V growth substrates. Thin films of high-Ge-content SiGe films are grown on GaAs(001) to below the kinetic critical thickness and released from the growth substrate by selectively etching a release layer to relax the strain. The resulting crystalline nanomembranes at the natural lattice constant of the alloy are transferred to a new host and epitaxially overgrown at similar compositions to make a thicker single crystal. Straightforward critical-thickness calculations demonstrate that a very wide range of group IV alloys, including those involving Sn, can be fabricated using the NM platform and the proper choice of III-V substrate. Motivations for making new group IV alloys center on band gap engineering for the development of novel group IV optoelectronic structures and devices.

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

Examining the Effect of Evaporation Field on Boron Measurements in SiGe: Insights into Improving the Relationship Between APT and SIMS Measurements of Boron

Understanding and resolving discrepancies between atom probe tomography (APT) and secondary ion mass spectrometry (SIMS) measurements of B dopants in Si-based materials has long been a problem for those in the semiconductor community who wish to measure B within the source/drain SiGe of a device. APT data collection of Si-based materials is typically optimized for Si, which is logical, but perhaps not ideal for field evaporation of B. Increasing the evaporation field well beyond the typically used 28Si2+:28Si+ ratio of approximately 10:1 up to a ratio of ~200:1 is demonstrated to improve B detection while retaining well-matched Si and Ge concentrations with respect to those measured by SIMS. A range of evaporation conditions are examined from a very low field with high laser energy to an extremely high field with extremely low laser energy demonstrating problems at both far ends of the spectrum and a sweet spot when the operating conditions used produce a 28Si2+:28Si+ ratio of approximately 200:1 (in terms of total counts of each ionization state), which is more than an order of magnitude higher than normally used conditions and results in nicely matched B, Si, and Ge APT measurements with those of SIMS.

Emerging Transistor Technologies Capable of Terahertz Amplification: A Way to Re-Engineer Terahertz Radar Sensors

This paper reviews the state of emerging transistor technologies capable of terahertz amplification, as well as the state of transistor modeling as required in terahertz electronic circuit research. Commercial terahertz radar sensors of today are being built using bulky and expensive technologies such as Schottky diode detectors and lasers, as well as using some emerging detection methods. Meanwhile, a considerable amount of research effort has recently been invested in process development and modeling of transistor technologies capable of amplifying in the terahertz band. Indium phosphide (InP) transistors have been able to reach maximum oscillation frequency (fmax) values of over 1 THz for around a decade already, while silicon-germanium bipolar complementary metal-oxide semiconductor (BiCMOS) compatible heterojunction bipolar transistors have only recently crossed the fmax = 0.7 THz mark. While it seems that the InP technology could be the ultimate terahertz technology, according to the fmax and related metrics, the BiCMOS technology has the added advantage of lower cost and supporting a wider set of integrated component types. BiCMOS can thus be seen as an enabling factor for re-engineering of complete terahertz radar systems, for the first time fabricated as miniaturized monolithic integrated circuits. Rapid commercial deployment of monolithic terahertz radar chips, furthermore, depends on the accuracy of transistor modeling at these frequencies. Considerations such as fabrication and modeling of passives and antennas, as well as packaging of complete systems, are closely related to the two main contributions of this paper and are also reviewed here. Finally, this paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terahertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.

Variability Predictions for the Next Technology Generations of n-type SixGe1-x Nanowire MOSFETs

Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on SixGe1−x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from sp3d5s∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.

The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability

In this paper, a new nanoscale double-gate junctionless tunneling field-effect transistor (DG-JL TFET) based on a Si_1-x Ge _x /Si/Ge heterojunction (HJ) structure is proposed to achieve an improved electrical performance. The effect of introducing the Si_1-x Ge _x material at the source side on improving the subthreshold behavior of the DG-JL TFET and on suppressing ambipolar conduction is investigated. Moreover, the impact of the Ge mole fraction in the proposed Si_1-x Ge _x source region on the electrical figures of merit (FoMs) of the transistor, including the swing factor and the I_ON/I_OFF ratio is analyzed. It is found that the optimized design with 60 atom % of Ge offers improved switching behavior and enhanced derived current capability at the nanoscale level, with a swing factor of 42 mV/dec and an I_ON/I_OFF ratio of 115 dB. Further, the scaling capability of the proposed Si_1-x Ge _x /Si/Ge DG-HJ-JL TFET structure is investigated and compared to that of a conventional Ge-DG-JL TFET design, where the optimized design exhibits an improved switching behavior at the nanoscale level. These results make the optimized device suitable for designing digital circuit for high-performance nanoelectronic applications.

Sub-THz Imaging Using Non-Resonant HEMT Detectors

Plasma waves in gated 2-D systems can be used to efficiently detect THz electromagnetic radiation. Solid-state plasma wave-based sensors can be used as detectors in THz imaging systems. An experimental study of the sub-THz response of II-gate strained-Si Schottky-gated MODFETs (Modulation-doped Field-Effect Transistor) was performed. The response of the strained-Si MODFET has been characterized at two frequencies: 150 and 300 GHz: The DC drain-to-source voltage transducing the THz radiation (photovoltaic mode) of 250-nm gate length transistors exhibited a non-resonant response that agrees with theoretical models and physics-based simulations of the electrical response of the transistor. When imposing a weak source-to-drain current of 5 μA, a substantial increase of the photoresponse was found. This increase is translated into an enhancement of the responsivity by one order of magnitude as compared to the photovoltaic mode, while the NEP (Noise Equivalent Power) is reduced in the subthreshold region. Strained-Si MODFETs demonstrated an excellent performance as detectors in THz imaging.

Tailoring Strain and Morphology of Core-Shell SiGe Nanowires by Low-Temperature Ge Condensation

Selective oxidation of the silicon element of silicon germanium (SiGe) alloys during thermal oxidation is a very important and technologically relevant mechanism used to fabricate a variety of microelectronic devices. We develop here a simple integrative approach involving vapor-liquid-solid (VLS) growth followed by selective oxidation steps to the construction of core-shell nanowires and higher-level ordered systems with scalable configurations. We examine the selective oxidation/condensation process under nonequilibrium conditions that gives rise to spontaneous formation of core-shell structures by germanium condensation. We contrast this strategy that uses reaction-diffusion-segregation mechanisms to produce coherently strained structures with highly configurable geometry and abrupt interfaces with growth-based processes which lead to low strained systems with nonuniform composition, three-dimensional morphology, and broad core-shell interface. We specially focus on SiGe core-shell nanowires and demonstrate that they can have up to 70% Ge-rich shell and 2% homogeneous strain with core diameter as small as 14 nm. Key elements of the building process associated with this approach are identified with regard to existing theoretical models. Moreover, starting from results of ab initio calculations, we discuss the electronic structure of these novel nanostructures as well as their wide potential for advanced device applications.

Strain measurement of 3D structured nanodevices by EBSD

We present a new methodology to accurately measure strain magnitudes from 3D nanodevices using Electron Backscatter Diffraction (EBSD). Because the dimensions of features on these devices are smaller than the interaction volume for backscattered electrons, EBSD patterns from 3D nanodevices will frequently be the superposition of patterns from multiple material regions simultaneously. The effect of this superposition on EBSD strain measurement is demonstrated, along with an approach to separate EBSD patterns from these devices via subtraction. The subtraction procedure is applied to 33 nm wide SiGe lines, and it provides accurate strain magnitudes where the traditional EBSD strain analysis method undervalues the strain magnitude by an order of magnitude. The approach provides a strain measurement technique for nanoscale 3D structures that is high spatial resolution, nondestructive, and accurate.

X-ray absorption in pillar shaped transmission electron microscopy specimens

The dependence of the X-ray absorption on the position in a pillar shaped transmission electron microscopy specimen is modeled for X-ray analysis with single and multiple detector configurations and for different pillar orientations relative to the detectors. Universal curves, applicable to any pillar diameter, are derived for the relative intensities between weak and medium or strongly absorbed X-ray emission. For the configuration as used in 360° X-ray tomography, the absorption correction for weak and medium absorbed X-rays is shown to be nearly constant along the pillar diameter. Absorption effects in pillars are about a factor 3 less important than in planar specimens with thickness equal to the pillar diameter. A practical approach for the absorption correction in pillar shaped samples is proposed and its limitations discussed. The modeled absorption dependences are verified experimentally for pillars with HfO₂ and SiGe stacks.

Strain mapping in a nanoscale-triangular SiGe pattern by dark-field electron holography with medium magnification mode

Recent years have seen a great deal of progress in the development of transmission electron microscopy-based techniques for strain measurement. Dark-field electron holography (DFEH) is a new technique offering configuration of the off-axis principle. Using this technique with medium magnification (Holo-M), we carried out strain measurements in nanoscale-triangular SiGe/(001) Si with (004), (2^-20) and (^-111) diffraction spots. The reconstruction of holograms and interpretation of strain maps in term of strain precision were discussed and the strain distributions in the SiGe/(001) Si patterns were visualized. Based on linear anisotropic elastic theory for strain simulation, the simulated results obtained by the finite element method compared with the experimental results acquired by DFEH. The strain values were found to be 0.9-1.0%, 1.1-1.2% and 1.0-1.1%, for the (004), (2^-20) and (^-111) diffracted beams, respectively, and the strain precisions were determined to be ~2.1 × 10^-3, 3.2 × 10^-3 and 9.1 × 10^-3 for the corresponding diffraction spots. As a result, DFEH is highlighted as a powerful technique for strain measurement, offering high-strain precision, high-spatial resolution and a large field of view.

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.

Highly Mismatched, Dislocation-Free SiGe/Si Heterostructures

Defect-free mismatched heterostructures on Si substrates are produced by an innovative strategy. The strain relaxation is engineered to occur elastically rather than plastically by combining suitable substrate patterning and vertical crystal growth with compositional grading. Its validity is proven both experimentally and theoretically for the pivotal case of SiGe/Si(001).

Density-Functional Theory Molecular Dynamics Simulations and Experimental Characterization of a-Al₂O₃/SiGe Interfaces

Density-functional theory molecular dynamics simulations were employed to investigate direct interfaces between a-Al2O3 and Si0.50Ge0.50 with Si- and Ge-terminations. The simulated stacks revealed mixed interfacial bonding. While Si-O and Ge-O bonds are unlikely to be problematic, bonding between Al and Si or Ge could result in metallic bond formation; however, the internal bonds of a-Al2O3 are sufficiently strong to allow just weak Al bonding to the SiGe surface thereby preventing formation of metallic-like states but leave dangling bonds. The oxide/SiGe band gaps were unpinned and close to the SiGe bulk band gap. The interfaces had SiGe dangling bonds, but they were sufficiently filled that they did not produce midgap states. Capacitance-voltage (C-V) spectroscopy and angle-resolved X-ray photoelectron spectroscopy experimentally confirmed formation of interfaces with low interface trap density via direct bonding between a-Al2O3 and SiGe.

Carrier Mobility Enhancement of Tensile Strained Si and SiGe Nanowires via Surface Defect Engineering

Changes in the carrier mobility of tensile strained Si and SiGe nanowires (NWs) were examined using an electrical push-to-pull device (E-PTP, Hysitron). The changes were found to be closely related to the chemical structure at the surface, likely defect states. As tensile strain is increased, the resistivity of SiGe NWs deceases in a linear manner. However, the corresponding values for Si NWs increased with increasing tensile strain, which is closely related to broken bonds induced by defects at the NW surface. Broken bonds at the surface, which communicate with the defect state of Si are critically altered when Ge is incorporated in Si NW. In addition, the number of defects could be significantly decreased in Si NWs by incorporating a surface passivated Al2O3 layer, which removes broken bonds, resulting in a proportional decrease in the resistivity of Si NWs with increasing strain. Moreover, the presence of a passivation layer dramatically increases the extent of fracture strain in NWs, and a significant enhancement in mobility of about 2.6 times was observed for a tensile strain of 5.7%.

Burgers Vector Analysis of Vertical Dislocations in Ge Crystals by Large-Angle Convergent Beam Electron Diffraction

By transmission electron microscopy with extended Burgers vector analyses, we demonstrate the edge and screw character of vertical dislocations (VDs) in novel SiGe heterostructures. The investigated pillar-shaped Ge epilayers on prepatterned Si(001) substrates are an attempt to avoid the high defect densities of lattice mismatched heteroepitaxy. The Ge pillars are almost completely strain-relaxed and essentially defect-free, except for the rather unexpected VDs. We investigated both pillar-shaped and unstructured Ge epilayers grown either by molecular beam epitaxy or by chemical vapor deposition to derive a general picture of the underlying dislocation mechanisms. For the Burgers vector analysis we used a combination of dark field imaging and large-angle convergent beam electron diffraction (LACBED). With LACBED simulations we identify ideally suited zeroth and second order Laue zone Bragg lines for an unambiguous determination of the three-dimensional Burgers vectors. By analyzing dislocation reactions we confirm the origin of the observed types of VDs, which can be efficiently distinguished by LACBED. The screw type VDs are formed by a reaction of perfect 60° dislocations, whereas the edge types are sessile dislocations that can be formed by cross-slips and climbing processes. The understanding of these origins allows us to suggest strategies to avoid VDs.

Formation of Nanopits in Si Capping Layers on SiGe Quantum Dots

In-situ annealing at a high temperature of 640°C was performed for a low temperature grown Si capping layer, which was grown at 300°C on SiGe self-assembled quantum dots with a thickness of 50 nm. Square nanopits, with a depth of about 8 nm and boundaries along 〈110〉, are formed in the Si capping layer after annealing. Cross-sectional transmission electron microscopy observation shows that each nanopit is located right over one dot with one to one correspondence. The detailed migration of Si atoms for the nanopit formation is revealed by in-situ annealing at a low temperature of 540°C. The final well-defined profiles of the nanopits indicate that both strain energy and surface energy play roles during the nanopit formation, and the nanopits are stable at 640°C. A subsequent growth of Ge on the nanopit-patterned surface results in the formation of SiGe quantum dot molecules around the nanopits.

Alloying and Strain Relaxation in SiGe Islands Grown on Pit-Patterned Si(001) Substrates Probed by Nanotomography

The three-dimensional composition profiles of individual SiGe/Si(001) islands grown on planar and pit-patterned substrates are determined by atomic force microscopy (AFM)-based nanotomography. The observed differences in lateral and vertical composition gradients are correlated with the island morphology. This approach allowed us to employ AFM to simultaneously gather information on the composition and strain of SiGe islands. Our quantitative analysis demonstrates that for islands with a fixed aspect ratio, a modified geometry of the substrate provides an enhancement of the relaxation, finally leading to a reduced intermixing.