Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory

Data-centric applications are pushing the limits of energy-efficiency in today's computing systems, including those based on phase-change memory (PCM). This technology must achieve low-power and stable operation at nanoscale dimensions to succeed in high-density memory arrays. Here we use a novel combination of phase-change material superlattices and nanocomposites (based on Ge4Sb6Te7), to achieve record-low power density ≈ 5 MW/cm2 and ≈ 0.7 V switching voltage (compatible with modern logic processors) in PCM devices with the smallest dimensions to date (≈ 40 nm) for a superlattice technology on a CMOS-compatible substrate. These devices also simultaneously exhibit low resistance drift with 8 resistance states, good endurance (≈ 2 × 108 cycles), and fast switching (≈ 40 ns). The efficient switching is enabled by strong heat confinement within the superlattice materials and the nanoscale device dimensions. The microstructural properties of the Ge4Sb6Te7 nanocomposite and its high crystallization temperature ensure the fast-switching speed and stability in our superlattice PCM devices. These results re-establish PCM technology as one of the frontrunners for energy-efficient data storage and computing.

Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors

Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current (IMIN) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of IMIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.

Area-Selective Atomic Layer Deposition for Resistive Random-Access Memory Devices

Resistive random-access memory (RRAM) is a promising technology for data storage and neuromorphic computing; however, cycle-to-cycle and device-to-device variability limits its widespread adoption and high-volume manufacturability. Improving the structural accuracy of RRAM devices during fabrication can reduce these variabilities by minimizing the filamentary randomness within a device. Here, we studied area-selective atomic layer deposition (AS-ALD) of the HfO2 dielectric for the fabrication of RRAM devices with higher reliability and accuracy. Without requiring photolithography, first we demonstrated ALD of HfO2 patterns uniformly and selectively on Pt bottom electrodes for RRAM but not on the underlying SiO2/Si substrate. RRAM devices fabricated using AS-ALD showed significantly narrower operating voltage range (2.6 × improvement) and resistance states than control devices without AS-ALD, improving the overall reliability of RRAM. Irrespective of device size (1 × 1, 2 × 2, and 5 × 5 μm2), we observed similar improvement, which is an inherent outcome of the AS-ALD technique. Our demonstration of AS-ALD for improved RRAM devices could further encourage the adoption of such techniques for other data storage technologies, including phase-change, magnetic, and ferroelectric RAM.

Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Probing the Melting Transitions in Phase-Change Superlattices via Thin Film Nanocalorimetry

Phase-change superlattices with nanometer thin sublayers are promising for low-power phase-change memory (PCM) on rigid and flexible platforms. However, the thermodynamics of the phase transition in such nanoscale superlattices remain unexplored, especially at ultrafast scanning rates, which is crucial for our fundamental understanding of superlattice-based PCM. Here, we probe the phase transition of Sb₂Te₃ (ST)/Ge₂Sb₂Te₅ (GST) superlattices using nanocalorimetry with a monolayer sensitivity (∼1 Å) and a fast scanning rate (10⁵ K/s). For a 2/1.8 nm/nm Sb₂Te₃/GST superlattice, we observe an endothermic melting transition with an ∼240 °C decrease in temperature and an ∼8-fold decrease in enthalpy compared to those for the melting of GST, providing key thermodynamic insights into the low-power switching of superlattice-based PCM. Nanocalorimetry measurements for Sb₂Te₃ alone demonstrate an intrinsic premelting similar to the unique phase transition of superlattices, thus revealing a critical role of the Sb₂Te₃ sublayer within our superlattices. These results advance our understanding of superlattices for energy-efficient data storage and computing.

Nanocrystallite Seeding of Metastable Ferroelectric Phase Formation in Atomic Layer-Deposited Hafnia-Zirconia Alloys

Hafnia-based ferroelectric thin films are promising for semiconductor memory and neuromorphic computing applications. Amorphous, as-deposited, thin-film binary alloys of HfO₂ and ZrO₂ transform to the metastable, orthorhombic ferroelectric phase during post-deposition annealing and cooling. This transformation is generally thought to involve formation of a tetragonal precursor phase that distorts into the orthorhombic phase during cooling. In this work, we systematically study the effects of atomic layer deposition (ALD) temperature on the ferroelectricity of post-deposition-annealed Hf_0.5Zr_0.5O₂ (HZO) thin films. Seed crystallites having interplanar spacings consistent with the polar orthorhombic phase are observed by a plan-view transmission electron microscope in HZO thin films deposited at an elevated ALD temperature. After ALD under conditions that promote formation of these nanocrystallites, high-polarization (P_r > 18 μC/cm²) ferroelectric switching is observed after rapid thermal annealing (RTA) at low temperature (350 °C). These results indicate the presence of minimal non-ferroelectric phases retained in the films after RTA when the ALD process forms nanocrystalline particles that seed subsequent formation of the polar orthorhombic phase.

Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2

Scaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS₂ FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.

Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance

Superlattice (SL) phase change materials have shown promise to reduce the switching current and resistance drift of phase change memory (PCM). However, the effects of internal SL interfaces and intermixing on PCM performance remain unexplored, although these are essential to understand and ensure reliable memory operation. Here, using nanometer-thin layers of Ge₂Sb₂Te₅ and Sb₂Te₃ in SL-PCM, we uncover that both switching current density (J_reset) and resistance drift coefficient (v) decrease as the SL period thickness is reduced (i.e., higher interface density); however, interface intermixing within the SL increases both. The signatures of distinct versus intermixed interfaces also show up in transmission electron microscopy, X-ray diffraction, and thermal conductivity measurements of our SL films. Combining the lessons learned, we simultaneously achieve low J_reset ≈ 3-4 MA/cm² and ultralow v ≈ 0.002 in mushroom-cell SL-PCM with ∼110 nm bottom contact diameter, thus advancing SL-PCM technology for high-density storage and neuromorphic applications.

A compute-in-memory chip based on resistive random-access memory

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

Ultralow-switching current density multilevel phase-change memory on a flexible substrate

[Figure: see text].

Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS₂ films at 560 °C in 50 min, within the 450-to-600 °C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ∼140 μA/μm at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS₂ grown below 600 °C using solid-source precursors. The effective mobility from transfer length method test structures is 29 ± 5 cm² V^-1 s^-1 at 6.1 × 10¹² cm^-2 electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

Electrical tuning of phase-change antennas and metasurfaces

The success of semiconductor electronics is built on the creation of compact, low-power switching elements that offer routing, logic and memory functions. The availability of nanoscale optical switches could have a similarly transformative impact on the development of dynamic and programmable metasurfaces, optical neural networks and quantum information processing. Phase-change materials are uniquely suited to enable their creation as they offer high-speed electrical switching between amorphous and crystalline states with notably different optical properties. Their high refractive index has already been harnessed to fashion them into compact optical antennas. Here, we take the next important step, by showing electrically-switchable phase-change antennas and metasurfaces that offer strong, reversible, non-volatile, multi-phase switching and spectral tuning of light scattering in the visible and near-infrared spectral ranges. Their successful implementation relies on a careful joint thermal and optical optimization of the antenna elements that comprise a silver strip that simultaneously serves as a plasmonic resonator and a miniature heating stage. Our metasurface affords electrical modulation of the reflectance by more than fourfold at 755 nm.

Ultrathin Three-Monolayer Tunneling Memory Selectors

High-density memory arrays require selector devices, which enable selection of a specific memory cell within a memory array by suppressing leakage current through unselected cells. Such selector devices must have highly nonlinear current-voltage characteristics and excellent endurance; thus selectors based on a tunneling mechanism present advantages over those based on the physical motion of atoms or ions. Here, we use two-dimensional (2D) materials to build an ultrathin (three-monolayer-thick) tunneling-based memory selector. Using a sandwich of h-BN, MoS₂, and h-BN monolayers leads to an "H-shaped" energy barrier in the middle of the heterojunction, which nonlinearly modulates the tunneling current when the external voltage is varied. We experimentally demonstrate that tuning the MoS₂ Fermi level can improve the device nonlinearity from 10 to 25. These results provide a fundamental understanding of the tunneling process through atomically thin 2D heterojunctions and lay the foundation for developing high endurance selectors with 2D heterojunctions, potentially enabling high-density non-volatile memory systems.

Localized Triggering of the Insulator-Metal Transition in VO2 Using a Single Carbon Nanotube

Vanadium dioxide (VO₂) has been widely studied for its rich physics and potential applications, undergoing a prominent insulator-metal transition (IMT) near room temperature. The transition mechanism remains highly debated, and little is known about the IMT at nanoscale dimensions. To shed light on this problem, here we use ∼1 nm-wide carbon nanotube (CNT) heaters to trigger the IMT in VO₂. Single metallic CNTs switch the adjacent VO₂ at less than half the voltage and power required by control devices without a CNT, with switching power as low as ∼85 μW at 300 nm device lengths. We also obtain potential and temperature maps of devices during operation using Kelvin probe microscopy and scanning thermal microscopy. Comparing these with three-dimensional electrothermal simulations, we find that the local heating of the VO₂ by the CNT plays a key role in the IMT. These results demonstrate the ability to trigger IMT in VO₂ using nanoscale heaters and highlight the significance of thermal engineering to improve device behavior.

Gate Quantum Capacitance Effects in Nanoscale Transistors

As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (C_Q). We demonstrate the impact of gate C_Q and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. We experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.

Fast Spiking of a Mott VO2-Carbon Nanotube Composite Device

The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO₂ film with a metallic carbon nanotube as a nanoscale heater, without using an external capacitor. Compared with VO₂-only devices, adding the nanotube heater dramatically decreases the transient duration and pulse energy, and increases the spiking frequency, by up to 3 orders of magnitude. This is caused by heating and cooling of the VO₂ across its insulator-metal transition being localized to a nanoscale conduction channel in an otherwise bulk medium. This result provides an important component of energy-efficient neuromorphic computing systems and a lithography-free technique for energy-scaling of electronic devices that operate via bulk mechanisms.

Optoelectronic resistive random access memory for neuromorphic vision sensors

Neuromorphic visual systems have considerable potential to emulate basic functions of the human visual system even beyond the visible light region. However, the complex circuitry of artificial visual systems based on conventional image sensors, memory and processing units presents serious challenges in terms of device integration and power consumption. Here we show simple two-terminal optoelectronic resistive random access memory (ORRAM) synaptic devices for an efficient neuromorphic visual system that exhibit non-volatile optical resistive switching and light-tunable synaptic behaviours. The ORRAM arrays enable image sensing and memory functions as well as neuromorphic visual pre-processing with an improved processing efficiency and image recognition rate in the subsequent processing tasks. The proof-of-concept device provides the potential to simplify the circuitry of a neuromorphic visual system and contribute to the development of applications in edge computing and the internet of things.

Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes

Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for flexible and wearable electronics. However, it usually suffers from low semiconducting tube purity, low device yield, and the mismatch between p- and n-type TFTs. Here, we report low-voltage and high-performance digital and analog CNT TFT circuits based on high-yield (19.9%) and ultrahigh purity (99.997%) polymer-sorted semiconducting CNTs. Using high-uniformity deposition and pseudo-CMOS design, we demonstrated CNT TFTs with good uniformity and high performance at low operation voltage of 3 V. We tested forty-four 2-µm channel 5-stage ring oscillators on the same flexible substrate (1,056 TFTs). All worked as expected with gate delays of 42.7 ± 13.1 ns. With these high-performance TFTs, we demonstrated 8-stage shift registers running at 50 kHz and the first tunable-gain amplifier with 1,000 gain at 20 kHz. These results show great potentials of using solution-processed CNT TFTs for large-scale flexible electronics.

Spatial Separation of Carrier Spin by the Valley Hall Effect in Monolayer WSe2 Transistors

We investigate the valley Hall effect (VHE) in monolayer WSe₂ field-effect transistors using optical Kerr rotation measurements at 20 K. While studies of the VHE have so far focused on n -doped MoS₂, we observe the VHE in WSe₂ in both the n - and p -doping regimes. Hole doping enables access to the large spin-splitting of the valence band of this material. The Kerr rotation measurements probe the spatial distribution of the valley carrier imbalance induced by the VHE. Under current flow, we observe distinct spin-valley polarization along the edges of the transistor channel. From analysis of the magnitude of the Kerr rotation, we infer a spin-valley density of 44 spins/μm, integrated over the edge region in the p -doped regime. Assuming a spin diffusion length less than 0.1 μm, this corresponds to a spin-valley polarization of the holes exceeding 1%.

Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at V_DS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of R_C from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent R_C variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of R_C in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high  R_C, even on correlated CNFETs.

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Universal Selective Dispersion of Semiconducting Carbon Nanotubes from Commercial Sources Using a Supramolecular Polymer

Selective extraction of semiconducting carbon nanotubes is a key step in the production of high-performance, solution-processed electronics. Here, we describe the ability of a supramolecular sorting polymer to selectively disperse semiconducting carbon nanotubes from five commercial sources with diameters ranging from 0.7 to 2.2 nm. The sorting purity of the largest-diameter nanotubes (1.4 to 2.2 nm; from Tuball) was confirmed by short channel measurements to be 97.5%. Removing the sorting polymer by acid-induced disassembly increased the transistor mobility by 94 and 24% for medium-diameter and large-diameter carbon nanotubes, respectively. Among the tested single-walled nanotube sources, the highest transistor performance of 61 cm²/V·s and on/off ratio >10⁴ were realized with arc discharge carbon nanotubes with a diameter range from 1.2 to 1.7 nm. The length and quality of nanotubes sorted from different sources is compared using measurements from atomic force microscopy and Raman spectroscopy. The transistor mobility is found to correlate with the G/D ratio extracted from the Raman spectra.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

Real-Time Observation of the Electrode-Size-Dependent Evolution Dynamics of the Conducting Filaments in a SiO2 Layer

Conducting bridge random access memory (CBRAM) is one of the most promising candidates for future nonvolatile memories. It is important to understand the scalability and retention of CBRAM cells to realize better memory performance. Here, we directly observe the switching dynamics of Cu tip/SiO₂/W cells with various active electrode sizes using in situ transmission electron microscopy. Conducting filaments (CFs) grow from the active electrode (Cu tip) to inert electrode (W) during the SET operations. The size of the Cu tip affects the electric-field distribution, the amount of the cation injection into electrolyte, and the dimension of the CF. This study provides helpful understanding on the relationship between power consumption and retention of CBRAM cells. We also construct a theoretical model to explain the electrode-size-dependent CF growth in SET operations, showing good agreement with our experimental results.

Engineering a Large Scale Indium Nanodot Array for Refractive Index Sensing

In this work, we developed a simple method to fabricate 12 × 4 mm² large scale nanostructure arrays and investigated the feasibility of indium nanodot (ND) array with different diameters and periods for refractive index sensing. Absorption resonances at multiple wavelengths from the visible to the near-infrared range were observed for various incident angles in a variety of media. Engineering the ND array with a centered square lattice, we successfully enhanced the sensitivity by 60% and improved the figure of merit (FOM) by 190%. The evolution of the resonance dips in the reflection spectra, of square lattice and centered square lattice, from air to water, matches well with the results of Lumerical FDTD simulation. The improvement of sensitivity is due to the enhancement of local electromagnetic field (E-field) near the NDs with centered square lattice, as revealed by E-field simulation at resonance wavelengths. The E-field is enhanced due to coupling between the two square ND arrays with [Formula: see text]x period at phase matching. This work illustrates an effective way to engineer and fabricate a refractive index sensor at a large scale. This is the first experimental demonstration of poor-metal (indium) nanostructure array for refractive index sensing. It also demonstrates a centered square lattice for higher sensitivity and as a better basic platform for more complex sensor designs.

Distinctive in-Plane Cleavage Behaviors of Two-Dimensional Layered Materials

Mechanical exfoliation from bulk layered crystal is widely used for preparing two-dimensional (2D) layered materials, which involves not only out-of-plane interlayer cleavage but also in-plane fracture. Through a statistical analysis on the exfoliated 2D flakes, we reveal the in-plane cleavage behaviors of six representative layered materials, including graphene, h-BN, 2H phase MoS2, 1T phase PtS2, FePS3, and black phosphorus. In addition to the well-known interlayer cleavage, these 2D layered materials show a distinctive tendency to fracture along certain in-plane crystallography orientations. With theoretical modeling and analysis, these distinct in-plane cleavage behaviors can be understood as a result of the competition between the release of the elastic energy and the increase of the surface energy during the fracture process. More importantly, these in-plane cleavage behaviors provide a fast and noninvasive method using optical microscopy to identify the lattice direction of mechanical exfoliated 2D layered materials.

High Current Density and Low Thermal Conductivity of Atomically Thin Semimetallic WTe2

Two-dimensional (2D) semimetals beyond graphene have been relatively unexplored in the atomically thin limit. Here, we introduce a facile growth mechanism for semimetallic WTe2 crystals and then fabricate few-layer test structures while carefully avoiding degradation from exposure to air. Low-field electrical measurements of 80 nm to 2 μm long devices allow us to separate intrinsic and contact resistance, revealing metallic response in the thinnest encapsulated and stable WTe2 devices studied to date (3-20 layers thick). High-field electrical measurements and electrothermal modeling demonstrate that ultrathin WTe2 can carry remarkably high current density (approaching 50 MA/cm(2), higher than most common interconnect metals) despite a very low thermal conductivity (of the order ∼3 Wm(-1) K(-1)). These results suggest several pathways for air-stable technological viability of this layered semimetal.

Picosecond Electric-Field-Induced Threshold Switching in Phase-Change Materials

Many chalcogenide glasses undergo a breakdown in electronic resistance above a critical field strength. Known as threshold switching, this mechanism enables field-induced crystallization in emerging phase-change memory. Purely electronic as well as crystal nucleation assisted models have been employed to explain the electronic breakdown. Here, picosecond electric pulses are used to excite amorphous Ag_{4}In_{3}Sb_{67}Te_{26}. Field-dependent reversible changes in conductivity and pulse-driven crystallization are observed. The present results show that threshold switching can take place within the electric pulse on subpicosecond time scales-faster than crystals can nucleate. This supports purely electronic models of threshold switching and reveals potential applications as an ultrafast electronic switch.

Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array

Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

High-Performance p-Type Black Phosphorus Transistor with Scandium Contact

A record high current density of 580 μA/μm is achieved for long-channel, few-layer black phosphorus transistors with scandium contacts after 400 K vacuum annealing. The annealing effectively improves the on-state current and Ion/Ioff ratio by 1 order of magnitude and the subthreshold swing by ∼2.5×, whereas Al2O3 capping significantly degrades transistor performances, resulting in 5× lower on-state current and 3× lower Ion/Ioff ratio. The influences of moisture on black phosphorus metal contacts are elucidated by analyzing the hysteresis of 3-20 nm thick black phosphorus transistors with scandium and gold contacts under different conditions: as-fabricated, after vacuum annealing, and after Al2O3 capping. The optimal black phosphorus film thickness for transistors with scandium contacts is found to be ∼10 nm. Moreover, p-type performance is shown in all transistors with scandium contacts, suggesting that the Fermi level is pinned closer to the valence band regardless of the flake thickness.

Statistical Study on the Schottky Barrier Reduction of Tunneling Contacts to CVD Synthesized MoS2

Creating high-quality, low-resistance contacts is essential for the development of electronic applications using two-dimensional (2D) layered materials. Many previously reported methods for lowering the contact resistance rely on volatile chemistry that either oxidize or degrade in ambient air. Nearly all reported efforts have been conducted on only a few devices with mechanically exfoliated flakes which is not amenable to large scale manufacturing. In this work, Schottky barrier heights of metal-MoS2 contacts to devices fabricated from CVD synthesized MoS2 films were reduced by inserting a thin tunneling Ta2O5 layer between MoS2 and metal contacts. Schottky barrier height reductions directly correlate with exponential reductions in contact resistance. Over two hundred devices were tested and contact resistances extracted for large scale statistical analysis. As compared to metal-MoS2 Schottky contacts without an insulator layer, the specific contact resistivity has been lowered by up to 3 orders of magnitude and current values increased by 2 orders of magnitude over large area (>4 cm(2)) films.

In Situ Tuning of Switching Window in a Gate-Controlled Bilayer Graphene-Electrode Resistive Memory Device

A resistive random access memory (RRAM) device with a tunable switching window is demonstrated for the first time. The SET voltage can be continuously tuned from 0.27 to 4.5 V by electrical gating from -10 to +35 V. The gate-controlled bilayer graphene-electrode RRAM can function as 1D1R and potentially increase the RRAM density.

Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier

Phase-change memory (PCM) is an important class of data storage, yet lowering the programming current of individual devices is known to be a significant challenge. Here we improve the energy-efficiency of PCM by placing a graphene layer at the interface between the phase-change material, Ge2Sb2Te5 (GST), and the bottom electrode (W) heater. Graphene-PCM (G-PCM) devices have ∼40% lower RESET current compared to control devices without the graphene. This is attributed to the graphene as an added interfacial thermal resistance which helps confine the generated heat inside the active PCM volume. The G-PCM achieves programming up to 10(5) cycles, and the graphene could further enhance the PCM endurance by limiting atomic migration or material segregation at the bottom electrode interface.

Metal oxide-resistive memory using graphene-edge electrodes

The emerging paradigm of ‘abundant-data' computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors. Todays computing technology, however, cannot scale to satisfy such big data applications with the required throughput and energy efficiency. The next technology frontier will be monolithically integrated chips with three-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene edge to assemble a resistive memory (∼3 Å thick) stacked in a vertical three-dimensional structure. We report some of the lowest power and energy consumption among the emerging non-volatile memories due to an extremely thin electrode with unique properties, low programming voltages, and low current. Circuit analysis of the three-dimensional architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

Increasing memory performance and density will require new breakthroughs in atomic-scale technology and three-dimensional device architectures. Here, the authors demonstrate a memory just 3 Å thick that can be stacked by exploiting the atomically thin edge of monolayer graphene.

Large-area assembly of densely aligned single-walled carbon nanotubes using solution shearing and their application to field-effect transistors

Dense alignment of single-walled carbon nanotubes over a large area is demonstrated using a novel solution-shearing technique. A density of 150-200 single-walled carbon nanotubes per micro-meter is achieved with a current density of 10.08 μA μm(-1) at VDS = -1 V. The on-current density is improved by a factor of 45 over that of random-network single-walled carbon nanotubes.

A general design strategy for block copolymer directed self-assembly patterning of integrated circuits contact holes using an alphabet approach

Directed self-assembly (DSA) is a promising lithography candidate for technology nodes beyond 14 nm. Researchers have shown contact hole patterning for random logic circuits using DSA with small physical templates. This paper introduces an alphabet approach that uses a minimal set of small physical templates to pattern all contacts configurations on integrated circuits. We illustrate, through experiments, a general and scalable template design strategy that links the DSA material properties to the technology node requirements.

Continuous wireless pressure monitoring and mapping with ultra-small passive sensors for health monitoring and critical care

Continuous monitoring of internal physiological parameters is essential for critical care patients, but currently can only be practically achieved via tethered solutions. Here we report a wireless, real-time pressure monitoring system with passive, flexible, millimetre-scale sensors, scaled down to unprecedented dimensions of 1 × 1 × 0.1 cubic millimeters. This level of dimensional scaling is enabled by novel sensor design and detection schemes, which overcome the operating frequency limits of traditional strategies and exhibit insensitivity to lossy tissue environments. We demonstrate the use of this system to capture human pulse waveforms wirelessly in real time as well as to monitor in vivo intracranial pressure continuously in proof-of-concept mice studies using sensors down to 2.5 × 2.5 × 0.1 cubic millimeters. We further introduce printable wireless sensor arrays and show their use in real-time spatial pressure mapping. Looking forward, this technology has broader applications in continuous wireless monitoring of multiple physiological parameters for biomedical research and patient care.

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance.

Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems

Neuromorphic computing is an attractive computation paradigm that complements the von Neumann architecture. The salient features of neuromorphic computing are massive parallelism, adaptivity to the complex input information, and tolerance to errors. As one of the most crucial components in a neuromorphic system, the electronic synapse requires high device integration density and low-energy consumption. Oxide-based resistive switching devices have been shown to be a promising candidate to realize the functions of the synapse. However, the intrinsic variation increases significantly with the reduced spike energy due to the reduced number of oxygen vacancies in the conductive filament region. The large resistance variation may degrade the accuracy of neuromorphic computation. In this work, we develop an oxide-based electronic synapse to suppress the degradation caused by the intrinsic resistance variation. The synapse utilizes a three-dimensional vertical structure including several parallel oxide-based resistive switching devices on the same nanopillar. The fabricated three-dimensional electronic synapse exhibits the potential for low fabrication cost, high integration density, and excellent performances, such as low training energy per spike, gradual resistance transition under identical pulse training scheme, and good repeatability. A pattern recognition computation is simulated based on a well-known neuromorphic visual system to quantify the feasibility of the three-dimensional vertical structured synapse for the application of neuromorphic computation systems. The simulation results show significantly improved recognition accuracy from 65 to 90% after introducing the three-dimensional synapses.

Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology

Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications.

Ultrafast characterization of phase-change material crystallization properties in the melt-quenched amorphous phase

Phase change materials are widely considered for application in nonvolatile memories because of their ability to achieve phase transformation in the nanosecond time scale. However, the knowledge of fast crystallization dynamics in these materials is limited because of the lack of fast and accurate temperature control methods. In this work, we have developed an experimental methodology that enables ultrafast characterization of phase-change dynamics on a more technologically relevant melt-quenched amorphous phase using practical device structures. We have extracted the crystallization growth velocity (U) in a functional capped phase change memory (PCM) device over 8 orders of magnitude (10(-10) < U < 10(-1) m/s) spanning a wide temperature range (415 < T < 580 K). We also observed direct evidence of non-Arrhenius crystallization behavior in programmed PCM devices at very high heating rates (>10(8) K/s), which reveals the extreme fragility of Ge2Sb2Te5 in its supercooled liquid phase. Furthermore, these crystallization properties were studied as a function of device programming cycles, and the results show degradation in the cell retention properties due to elemental segregation. The above experiments are enabled by the use of an on-chip fast heater and thermometer called as microthermal stage (MTS) integrated with a vertical phase change memory (PCM) cell. The temperature at the PCM layer can be controlled up to 600 K using MTS and with a thermal time constant of 800 ns, leading to heating rates ∼10(8) K/s that are close to the typical device operating conditions during PCM programming. The MTS allows us to independently control the electrical and thermal aspects of phase transformation (inseparable in a conventional PCM cell) and extract the temperature dependence of key material properties in real PCM devices.

Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations

Precise electrical manipulation of nanoscale defects such as vacancy nano-filaments is highly desired for the multi-level control of ReRAM. In this paper we present a systematic investigation on the pulse-train operation scheme for reliable multi-level control of conductive filament evolution. By applying the pulse-train scheme to a 3 bit per cell HfO2 ReRAM, the relative standard deviations of resistance levels are improved up to 80% compared to the single-pulse scheme. The observed exponential relationship between the saturated resistance and the pulse amplitude provides evidence for the gap-formation model of the filament-rupture process.

Carbon nanotube circuit integration up to sub-20 nm channel lengths

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

VLSI-compatible carbon nanotube doping technique with low work-function metal oxides

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.

Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory

The vertical scaling for the multi-layer stacked 3D vertical resistive random access memory (RRAM) cross-point array is investigated. The thickness of the multi-layer stack for a 3D RRAM is a key factor for determining the storage density. A vertical RRAM cell with plane electrode thickness (tm) scaled down to 5 nm, aiming to minimize 3D stack height, is experimentally demonstrated. An improvement factor of 5 in device density can be achieved as compared to a previous demonstration using a 22 nm thick plane electrode. It is projected that 37 layers can be stacked for a lithographic half-pitch (F) = 26 nm and total thickness of one stack (T) = 21 nm, delivering a bit density of 72.8 nm(2)/cell.

Stochastic learning in oxide binary synaptic device for neuromorphic computing

Hardware implementation of neuromorphic computing is attractive as a computing paradigm beyond the conventional digital computing. In this work, we show that the SET (off-to-on) transition of metal oxide resistive switching memory becomes probabilistic under a weak programming condition. The switching variability of the binary synaptic device implements a stochastic learning rule. Such stochastic SET transition was statistically measured and modeled for a simulation of a winner-take-all network for competitive learning. The simulation illustrates that with such stochastic learning, the orientation classification function of input patterns can be effectively realized. The system performance metrics were compared between the conventional approach using the analog synapse and the approach in this work that employs the binary synapse utilizing the stochastic learning. The feasibility of using binary synapse in the neurormorphic computing may relax the constraints to engineer continuous multilevel intermediate states and widens the material choice for the synaptic device design.

Synaptic electronics: materials, devices and applications

In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing. Performance metrics desirable for large-scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented.

Atomic layer deposition of high-k dielectrics on single-walled carbon nanotubes: a Raman study

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, to realize a carbon nanotube field effect transistor (CNTFET) with excellent gate control, the high-k dielectrics between the CNT and the metal gate must have superb electrical properties and extremely high uniformity. Thus it is essential to understand the interactions between high-k materials and the SWCNTs to effectively control the transistor characteristics. In this study, we investigate the effects of atomic layer deposited (ALD) high-k dielectrics (Al2O3 and HfO2) on SWCNTs using Raman spectroscopy. We subjected the SWCNTs to various ALD cycles and studied the nucleation and growth of ALD dielectrics at defect sites using scanning electron microscopy and transmission electron microscopy images. We analyzed these samples using Raman spectroscopy and x-ray photoelectron spectroscopy. The Raman peak shifts of the G-peak and the 2D (G') peaks suggest doping and stress induced effects on the CNTs by the surrounding high-k oxide environment. Trends in the G-peak FWHM and G/D-peak ratios were identified and compared between Al2O3 and HfO2. We confirmed the ALD-deposited HfO2 is polycrystalline using x-ray diffraction and analyzed dielectric-CNT bonding states using XPS measurements. This study provides insights on the effects of ALD high-k materials on SWCNTs for future high-speed transistor applications.