High-Performance Wafer-Scale MoS2 Transistors toward Practical Application

Large-Area Epitaxial Growth of Transition Metal Dichalcogenides

Over the past decade, research on atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) has expanded rapidly due to their unique properties such as high carrier mobility, significant excitonic effects, and strong spin-orbit couplings. Considerable attention from both scientific and industrial communities has fully fueled the exploration of TMDs toward practical applications. Proposed scenarios, such as ultrascaled transistors, on-chip photonics, flexible optoelectronics, and efficient electrocatalysis, critically depend on the scalable production of large-area TMD films. Correspondingly, substantial efforts have been devoted to refining the synthesizing methodology of 2D TMDs, which brought the field to a stage that necessitates a comprehensive summary. In this Review, we give a systematic overview of the basic designs and significant advancements in large-area epitaxial growth of TMDs. We first sketch out their fundamental structures and diverse properties. Subsequent discussion encompasses the state-of-the-art wafer-scale production designs, single-crystal epitaxial strategies, and techniques for structure modification and postprocessing. Additionally, we highlight the future directions for application-driven material fabrication and persistent challenges, aiming to inspire ongoing exploration along a revolution in the modern semiconductor industry.

Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlOx/Al2O3 and a double-gate structure employing high-k dielectric HfO2. Due to the superior subthreshold characteristics, monolayer WS2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage (VDD) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm-1 at VDD = 1 V. In addition, the monolayer WS2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS2 for high-gain and low-power logic circuits and validate the practical application in large areas.

Mitigation of Device Heterogeneity in Graphene Hall Sensor Arrays Using Per-Element Backgate Tuning

Graphene Hall-effect magnetic field sensors (GHSs) exhibit high performance comparable to state-of-the-art commercial Hall sensors made from III-V semiconductors. Graphene is also amenable to CMOS-compatible fabrication processes, making GHSs attractive candidates for implementing magnetic sensor arrays for imaging fields in biosensing and scanning probe applications. However, their practical appeal is limited by response heterogeneity and drift, arising from the high sensitivity of two-dimensional (2D) materials to local device imperfections. To address this challenge, we designed a GHS array in which an individual backgate is added to each GHS, allowing the carrier density of each sensor to be electrostatically tuned independent of other sensors in the array. Compared to the constraints encountered when all devices are tuned with the same backgate, we expected that the flexibility afforded by individual tuning would allow for the array's sensitivity, uniformity, and reconfigurability to be enhanced. We fabricated an array of 16 GHSs, each with its own backgate terminal, and characterized the ability to modulate GHS carrier density and Hall sensitivity within CMOS-compatible voltage ranges. We then demonstrated that individual device tuning can be used to break the trade-off between device sensitivity and uniformity in the GHS array, allowing for enhancement of both objectives. Our results showed that GHS arrays exhibiting >30% variability under single-backgate operation could be compensated using individual tuning to achieve <2% variability with minimal impact on the array sensitivity.

LAB-to-FAB Transition of 2D FETs: Available Strategies and Future Trends

The last decade has seen dramatic progress in research on FETs with 2D channels. Starting from the single devices fabricated using exfoliated flakes in the early 2010s, by the early 2020s, 2D FETs being trialed for mass production and vertical stacking of 2D channels made by leading semiconductor companies. However, the industry is focused solely on transition metal dichalcogenide (TMD) channels coupled with conventional 3D oxide insulators such as Al2O3 and HfO2. This has resulted in numerous challenges, such as poor-quality interfaces and reliability limitations due to oxide traps. At the same time, the alternative routes for 2D FETs offered by laboratory (LAB) research have not been appreciated until now, even though the use of the native oxides of 2D channels has recently resulted in the first 2D FinFETs. Considering the research progress achieved in the last decade, from this perspective, we will discuss the main challenges for industry integration of 2D FETs and also suggest possible future steps which could propel these emerging technologies towards market applications.

Organic Electrochemical Transistors for Biomarker Detections

The improvement of living standards and the advancement of medical technology have led to an increased focus on health among individuals. Detections of biomarkers are feasible approaches to obtaining information about health status, disease progression, and response to treatment of an individual. In recent years, organic electrochemical transistors (OECTs) have demonstrated high electrical performances and effectiveness in detecting various types of biomarkers. This review provides an overview of the working principles of OECTs and their performance in detecting multiple types of biomarkers, with a focus on the recent advances and representative applications of OECTs in wearable and implantable biomarker detections, and provides a perspective for the future development of OECT-based biomarker sensors.

Biomimetic wafer-scale alignment of tellurium nanowires for high-mobility flexible and stretchable electronics

Flexible and stretchable thin-film transistors (TFTs) are crucial in skin-like electronics for wearable and implantable applications. Such electronics are usually constrained in performance owing to a lack of high-mobility and stretchable semiconducting channels. Tellurium, a rising semiconductor with superior charge carrier mobilities, has been limited by its intrinsic brittleness and anisotropy. Here, we achieve highly oriented arrays of tellurium nanowires (TeNWs) on various substrates with wafer-scale scalability by a facile lock-and-shear strategy. Such an assembly approach mimics the alignment process of the trailing tentacles of a swimming jellyfish. We further apply these TeNW arrays in high-mobility TFTs and logic gates with improved flexibility and stretchability. More specifically, mobilities over 100 square centimeters per volt per second and on/off ratios of ~104 are achieved in TeNW-TFTs. The TeNW-TFTs on polyethylene terephthalate can sustain an omnidirectional bending strain of 1.3% for more than 1000 cycles. Furthermore, TeNW-TFTs on an elastomeric substrate can withstand a unidirectional strain of 40% with no performance degradation.

Enhanced Photogating Gain in Scalable MoS2 Plasmonic Photodetectors via Resonant Plasmonic Metasurfaces

Absorption of photons in atomically thin materials has become a challenge in the realization of ultrathin, high-performance optoelectronics. While numerous schemes have been used to enhance absorption in 2D semiconductors, such enhanced device performance in scalable monolayer photodetectors remains unattained. Here, we demonstrate wafer-scale integration of monolayer single-crystal MoS2 photodetectors with a nitride-based resonant plasmonic metasurface to achieve a high detectivity of 2.58 × 1012 Jones with a record-low dark current of 8 pA and long-term stability over 40 days. Upon comparison with control devices, we observe an overall enhancement factor of >100; this can be attributed to the local strong EM field enhanced photogating effect by the resonant plasmonic metasurface. Considering the compatibility of 2D semiconductors and hafnium nitride with the Si CMOS process and their scalability across wafer sizes, our results facilitate the smooth incorporation of 2D semiconductor-based photodetectors into the fields of imaging, sensing, and optical communication applications.

Polarized Tunneling Transistor for Ultralow-Energy-Consumption Artificial Synapse toward Neuromorphic Computing

Neural networks based on low-power artificial synapses can significantly reduce energy consumption, which is of great importance in today's era of artificial intelligence. Two-dimensional (2D) material-based floating-gate transistors (FGTs) have emerged as compelling candidates for simulating artificial synapses owing to their multilevel and nonvolatile data storage capabilities. However, the low erasing/programming speed of FGTs renders them unsuitable for low-energy-consumption artificial synapses, thereby limiting their potential in high-energy-efficient neuromorphic computing. Here, we introduce a FGT-inspired MoS2/Trap/PZT heterostructure-based polarized tunneling transistor (PTT) with a simple fabrication process and significantly enhanced erasing/programming speed. Distinct from the FGT, the PTT lacks a tunnel layer, leading to a marked improvement in its erasing/programming speed. The PTT's highest erasing/programming (operation) speed can reach ∼20 ns, which outperforms the performance of most FGTs based on 2D heterostructures. Furthermore, the PTT has been utilized as an artificial synapse, and its weight-update energy consumption can be as low as 0.0002 femtojoule (fJ), which benefits from the PTT's ultrahigh operation speed. Additionally, PTT-based artificial synapses have been employed in constructing artificial neural network simulations, achieving facial-recognition accuracy (95%). This groundbreaking work makes it possible for fabricating future high-energy-efficient neuromorphic transistors utilizing 2D materials.

Tensile Strain-Dependent Ultrafast Electron Transfer and Relaxation Dynamics in Flexible WSe2/MoS2 Heterostructures

Understanding and controlling carrier dynamics in two-dimensional (2D) van der Waals heterostructures through strain are crucial for their flexible applications. Here, femtosecond transient absorption spectroscopy is employed to elucidate the interlayer electron transfer and relaxation dynamics under external tensile strains in a WSe2/MoS2 heterostructure. The results show that a modest ∼1% tensile strain can significantly alter the lifetimes of electron transfer and nonradiative electron-hole recombination by >30%. Ab initio non-adiabatic molecular dynamics simulations suggest that tensile strain weakens the electron-phonon coupling, thereby suppressing the transfer and recombination dynamics. Theoretical predictions indicate that strain-induced energy difference increases along the electron transfer path could contribute to the prolongation of the transfer lifetime. A subpicosecond decay process, related to hot-electron cooling, remains almost unaffected by strain. This study demonstrates the potential of tuning interlayer carrier dynamics through external strains, offering insights into flexible optoelectronic device design with 2D materials.

PZT-Enabled MoS2 Floating Gate Transistors: Overcoming Boltzmann Tyranny and Achieving Ultralow Energy Consumption for High-Accuracy Neuromorphic Computing

Low-power electronic devices play a pivotal role in the burgeoning artificial intelligence era. The study of such devices encompasses low-subthreshold swing (SS) transistors and neuromorphic devices. However, conventional field-effect transistors (FETs) face the inherent limitation of the "Boltzmann tyranny", which restricts SS to 60 mV decade-1 at room temperature. Additionally, FET-based neuromorphic devices lack sufficient conductance states for highly accurate neuromorphic computing due to a narrow memory window. In this study, we propose a pioneering PZT-enabled MoS2 floating gate transistor (PFGT) configuration, demonstrating a low SS of 46 mV decade-1 and a wide memory window of 7.2 V in the dual-sweeping gate voltage range from -7 to 7 V. The wide memory window provides 112 distinct conductance states for PFGT. Moreover, the PFGT-based artificial neural network achieves an outstanding facial-recognition accuracy of 97.3%. This study lays the groundwork for the development of low-SS transistors and highly energy efficient artificial synapses utilizing two-dimensional materials.

Large-scale and stacked transfer of bilayers MoS2devices on a flexible polyimide substrate

Two-dimensional transition metal dichalcogenides (TMDs), as flexible and stretchable materials, have attracted considerable attention in the field of novel flexible electronics due to their excellent mechanical, optical, and electronic properties. Among the various TMD materials, atomically thin MoS2has become the most widely used material due to its advantageous properties, such as its adjustable bandgap, excellent performance, and ease of preparation. In this work, we demonstrated the practicality of a stacked wafer-scale two-layer MoS2film obtained by transferring multiple single-layer films grown using chemical vapor deposition. The MoS2field-effect transistor cell had a top-gated device structure with a (PI) film as the substrate, which exhibited a high on/off ratio (108), large average mobility (∼8.56 cm2V-1s-1), and exceptional uniformity. Furthermore, a range of flexible integrated logic devices, including inverters, NOR gates, and NAND gates, were successfully implemented via traditional lithography. These results highlight the immense potential of TMD materials, particularly MoS2, in enabling advanced flexible electronic and optoelectronic devices, which pave the way for transformative applications in future-generation electronics.

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array.

TiO2-modified MoS2 monolayer films enable sensitive NH3 sensing at room temperature

The research and development of high-performance NH3 sensors are of great significance for environment monitoring and disease diagnosis applications. Two-dimensional (2D) MoS2 nanomaterials have exhibited great potential for building room-temperature (RT) NH3 sensors but still suffer from relatively low sensitivity. Herein, the TiO2-modified monolayer MoS2 films with controllable TiO2 loading contents are fabricated by a facile approach. A remarkable enhancement in the RT NH3 sensing performance is achieved after the n-n hetero-compositing of the TiO2/MoS2 system. The device with 95% surface coverage of TiO2 shows enhanced sensor response, low detection limit (0.5 ppm), wide detection range (0.5-1000 ppm), good repeatability, and superior selectivity against other gases. In situ Kelvin potential force microscopy results revealed that the TiO2 modification not only improved the surface reactivity of the sensing layers but also contributed to the NH3 sensing performance by serving as the "gas-gating" layers that modulated the electron depletion layer and the conductivity of the MoS2 films. Such an n-n hetero-compositing strategy can provide a simple and cost-effective approach for developing high-performance NH3 sensors based on 2D semiconductors.

Carbon Nanotube Field-Effect Transistor Biosensor with an Enlarged Gate Area for Ultra-Sensitive Detection of a Lung Cancer Biomarker

Carcinoembryonic antigen (CEA) is a recognized biomarker for lung cancer and can be used for early detection. However, the clinical value of CEA is not fully realized due to the rigorous requirement for high-sensitivity and wide-range detection methods. Field-effect transistor (FET) biosensors, as one of the potentially powerful platforms, may detect CEA with a significantly higher sensitivity than conventional clinical testing equipment, while their sensitivity and detection range for CEA are far below the requirement for early detection. Here, we construct a floating gate FET biosensor to detect CEA based on a semiconducting carbon nanotube (CNT) film combined with an undulating yttrium oxide (Y₂O₃) dielectric layer as the biosensing interface. Utilizing an undulating biosensing interface, the proposed device showed a wider detection range and optimized sensitivity and detection limit, which benefited from an increase of probe-binding sites on the sensing interface and an increase of electric double-layer capacitance, respectively. The outcomes of analytical studies confirm that the undulating Y₂O₃ provided the desired biosensing surface for probe immobilization and performance optimization of a CNT-FET biosensor toward CEA including a wide detection range from 1 fg/mL to 1 ng/mL, good linearity, and high sensitivity of 72 ag/mL. More crucially, the sensing platform can function normally in the complicated environment of fetal bovine serum, indicating its great promise for early lung cancer screening.

Enhancing optical characteristics of mediator-assisted wafer-scale MoS2and WS2on h-BN

Two-dimensional (2D) materials and their heterostructures exhibit intriguing optoelectronic properties; thus, they are good platforms for exploring fundamental research and further facilitating real device applications. The key is to preserve the high quality and intrinsic properties of 2D materials and their heterojunction interface even in production scale during the transfer and assembly process so as to apply in semiconductor manufacturing field. In this study, we successfully adopted a wet transfer existing method to separate mediator-assisted wafer-scale from SiO₂/Si growing wafer for the first time with intermediate annealing to fabricate wafer-scale MoS₂/h-BN and WS₂/h-BN heterostructures on a SiO₂/Si wafer. Interestingly, the high-quality wafer-scale 2D material heterostructure optical properties were enhanced and confirmed by Raman and photoluminescence spectroscopy. Our approach can be applied to other 2D materials and expedite mass production for industrial applications.

Emerging MoS2 Wafer-Scale Technique for Integrated Circuits

As an outstanding representative of layered materials, molybdenum disulfide (MoS2) has excellent physical properties, such as high carrier mobility, stability, and abundance on earth. Moreover, its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics, flexible electronics, and focal-plane photodetector. However, to realize the all-aspects application of MoS2, the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization. Although the MoS2 grain size has already improved from several micrometers to sub-millimeters, the high-quality growth of wafer-scale MoS2 is still of great challenge. Herein, this review mainly focuses on the evolution of MoS2 by including chemical vapor deposition, metal-organic chemical vapor deposition, physical vapor deposition, and thermal conversion technology methods. The state-of-the-art research on the growth and optimization mechanism, including nucleation, orientation, grain, and defect engineering, is systematically summarized. Then, this review summarizes the wafer-scale application of MoS2 in a transistor, inverter, electronics, and photodetectors. Finally, the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS2.

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time-zero and time-dependent variability in the performance of the transistors appear critical. While time-zero variability is primarily related to immature processing, time-dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time-dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor-related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors

2D semiconductors, such as molybdenum disulfide (MoS₂ ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS₂ film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS₂ field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS₂ logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

The Road for 2D Semiconductors in the Silicon Age

Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high-performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon-compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all-in-one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer-scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.

Large-Scale MoS2 Pixel Array for Imaging Sensor

Two-dimensional molybdenum disulfide (MoS₂) has been extensively investigated in the field of optoelectronic devices. However, most reported MoS₂ phototransistors are fabricated using the mechanical exfoliation method to obtain micro-scale MoS₂ flakes, which is laboratory- feasible but not practical for the future industrial fabrication of large-scale pixel arrays. Recently, wafer-scale MoS₂ growth has been rapidly developed, but few results of uniform large-scale photoelectric devices were reported. Here, we designed a 12 × 12 pixels pixel array image sensor fabricated on a 2 cm × 2 cm monolayer MoS₂ film grown by chemical vapor deposition (CVD). The photogating effect induced by the formation of trap states ensures a high photoresponsivity of 364 AW^-1, which is considerably superior to traditional CMOS sensors (≈0.1 AW^-1). Experimental results also show highly uniform photoelectric properties in this array. Finally, the concatenated image obtained by laser lighting stencil and photolithography mask demonstrates the promising potential of 2D MoS₂ for future optoelectrical applications.

The first progress of plasma-based transition metal dichalcogenide synthesis: a stable 1T phase and promising applications

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have attracted attention as polymorphs depending on their phases (1T and 2H) when applying typical synthesis methods. The 2H phase is generally synthesised through chemical vapour deposition (CVD) on a wafer-scale at high temperatures, and many synthesis methods have been reported owing to their thermodynamic stability and semiconductor properties. By contrast, although the 1T phase is meta-stable with an octahedral coordination, thereby limiting the use of synthesis methods, the recent structural advantage in terms of the hydrogen evolution reaction (HER) has been emphasised. Despite this demand, no large-area thin-film synthesis method for 1T-TMDs has been developed. Among several strategies of synthesizing metallic-phase (1T) TMDs, chemical exfoliation (alkali metal intercalation) is a major strategy and others have been used for electron-beam irradiation, laser irradiation, defects, plasma hot electron transfer, and mechanical strain. Therefore, we suggest an innovative synthesis method using plasma-enhanced CVD (PECVD) for both the 1T and 2H phases of TMDs (MoS2 and WS2). Because ions and radicals are accelerated to the substrate within the sheath region, a high-temperature source is not needed for vapour ionisation, and thus the process temperature can be significantly lowered (150 °C). Moreover, a 4-inch wafer-scale of a thin film is an advantage and can be synthesised on arbitrary substrates (SiO2/Si wafer, glassy carbon electrode, Teflon, and polyimide). Furthermore, the PECVD method was applied to TMD-graphene heterostructure films with a graphene-transferred substrate, and for the first time, sequential metal seed layer depositions of W (1 nm) and Mo (1 nm) were sulfurized to MoS2-WS2 vertical heterostructures with Ar + H2S plasma. We considered the prospects and challenges of the new PECVD method in the development of practical applications in next-generation integrated electronics, HER catalysts, and flexible biosensors.

Strategies for Controlled Growth of Transition Metal Dichalcogenides by Chemical Vapor Deposition for Integrated Electronics

In recent years, transition metal dichalcogenide (TMD)-based electronics have experienced a prosperous stage of development, and some considerable applications include field-effect transistors, photodetectors, and light-emitting diodes. Chemical vapor deposition (CVD), a typical bottom-up approach for preparing 2D materials, is widely used to synthesize large-area 2D TMD films and is a promising method for mass production to implement them for practical applications. In this review, we investigate recent progress in controlled CVD growth of 2D TMDs, aiming for controlled nucleation and orientation, using various CVD strategies such as choice of precursors or substrates, process optimization, and system engineering. We then survey different patterning methods, such as surface patterning, metal precursor patterning, and postgrowth sulfurization/selenization/tellurization, to mass produce heterostructures for device applications. With these strategies, various well-designed architectures, such as wafer-scale single crystals, vertical and lateral heterostructures, patterned structures, and arrays, are achieved. In addition, we further discuss various electronics made from CVD-grown TMDs to demonstrate the diverse application scenarios. Finally, perspectives regarding the current challenges of controlled CVD growth of 2D TMDs are also suggested.

Layer-by-layer epitaxy of multi-layer MoS2 wafers

The 2D semiconductor of MoS₂ has great potential for advanced electronics technologies beyond silicon. So far, high-quality monolayer MoS₂ wafers have been available and various demonstrations from individual transistors to integrated circuits have also been shown. In addition to the monolayer, multilayers have narrower band gaps but improved carrier mobilities and current capacities over the monolayer. However, achieving high-quality multi-layer MoS₂ wafers remains a challenge. Here we report the growth of high-quality multi-layer MoS₂ 4-inch wafers via the layer-by-layer epitaxy process. The epitaxy leads to well-defined stacking orders between adjacent epitaxial layers and offers a delicate control of layer numbers up to six. Systematic evaluations on the atomic structures and electronic properties were carried out for achieved wafers with different layer numbers. Significant improvements in device performances were found in thicker-layer field-effect transistors (FETs), as expected. For example, the average field-effect mobility (μ_FE) at room temperature (RT) can increase from ∼80 cm²·V^–1·s^–1 for monolayers to ∼110/145 cm²·V^–1·s^–1 for bilayer/trilayer devices. The highest RT μ_FE of 234.7 cm²·V^–1·s^–1 and record-high on-current densities of 1.70 mA·μm^–1 at V_ds = 2 V were also achieved in trilayer MoS₂ FETs with a high on/off ratio of >10⁷. Our work hence moves a step closer to practical applications of 2D MoS₂ in electronics.

Wafer-Scale Demonstration of MBC-FET and C-FET Arrays Based on Two-Dimensional Semiconductors

Two-dimentional semiconductors have shown potential applications in multi-bridge channel field-effect transistors (MBC-FETs) and complementary field-effect transistors (C-FETs) due to their atomic thickness, stackability, and excellent electrical properties. However, the exploration of MBC-FET and C-FET based on large-scale 2D semiconductors is still lacking. Here, based on a reliable vertical stacking of wafer-scale 2D semiconductors, large-scale MBC-FETs and C-FETs using n-type MoS₂ and p-type MoTe₂ are successfully fabricated. The drive current of an MBC-FET with two layers of MoS₂ channel (20 µm/10 µm) is up to 60 µA under 1 V bias. Compared with the single-gate MoS₂ FET, the carrier mobility of MBC-FET is 2.3 times higher and the sub-threshold swing is 70% smaller. Furthermore, NAND and NOR logic circuits are also constructed based on two vertically stacked MoS₂ channels. Then, C-FET arrays are fabricated by 3D integrating n-type MoS₂ FET and p-type MoTe₂ FET, which exhibit a voltage gain of 7 V/V when V_DD  = 4 V. In addition, this C-FET device can directly convert light signals to an electrical digital signal within a single device. The demonstration of MBC-FET and C-FET based on large-scale 2D semiconductors will promote the application of 2D semiconductors in next-generation circuits.

Engineering Top Gate Stack for Wafer-Scale Integrated Circuit Fabrication Based on Two-Dimensional Semiconductors

In recent years, two-dimensional (2D) semiconductors have attracted considerable attention from both academic and industrial communities. Recent research has begun transforming from constructing basic field-effect transistors (FETs) into designing functional circuits. However, device processing remains a bottleneck in circuit-level integration. In this work, a non-destructive doping strategy is proposed to modulate precisely the threshold voltage (V_TH) of MoS₂-FETs in a wafer scale. By inserting an Al interlayer with a varied thickness between the high-k dielectric and the Au top gate (TG), the doping could be controlled. The full oxidation of the Al interlayer generates a surplus of oxygen vacancy (Vo) in the high-k dielectric layer, which further leads to stable electron doping. The proposed strategy is then used to optimize an inverter circuit by matching the electrical properties of the load and driver transistors. Furthermore, the doping strategy is used to fabricate digital logic blocks with desired logic functions, which indicates its potential to fabricate fully integrated multistage logic circuits based on wafer-scale 2D semiconductors.

Analysis of Schottky barrier heights and reduced Fermi-level pinning in monolayer CVD-grown MoS2field-effect-transistors

Chemical vapor deposition (CVD)-grown monolayer (ML) molybdenum disulfide (MoS₂) is a promising material for next-generation integrated electronic systems due to its capability of high-throughput synthesis and compatibility with wafer-scale fabrication. Several studies have described the importance of Schottky barriers in analyzing the transport properties and electrical characteristics of MoS₂field-effect-transistors (FETs) with metal contacts. However, the analysis is typically limited to single devices constructed from exfoliated flakes and should be verified for large-area fabrication methods. In this paper, CVD-grown ML MoS₂was utilized to fabricate large-area (1 cm × 1 cm) FET arrays. Two different types of metal contacts (i.e. Cr/Au and Ti/Au) were used to analyze the temperature-dependent electrical characteristics of ML MoS₂FETs and their corresponding Schottky barrier characteristics. Statistical analysis provides new insight about the properties of metal contacts on CVD-grown MoS₂compared to exfoliated samples. Reduced Schottky barrier heights (SBH) are obtained compared to exfoliated flakes, attributed to a defect-induced enhancement in metallization of CVD-grown samples. Moreover, the dependence of SBH on metal work function indicates a reduction in Fermi level pinning compared to exfoliated flakes, moving towards the Schottky-Mott limit. Optical characterization reveals higher defect concentrations in CVD-grown samples supporting a defect-induced metallization enhancement effect consistent with the electrical SBH experiments.

An artificial neural network chip based on two-dimensional semiconductor

Recently, research on two-dimensional (2D) semiconductors has begun to translate from the fundamental investigation into rudimentary functional circuits. In this work, we unveil the first functional MoS₂ artificial neural network (ANN) chip, including multiply-and-accumulate (MAC), memory and activation function circuits. Such MoS₂ ANN chip is realized through fabricating 818 field-effect transistors (FETs) on a wafer-scale and high-homogeneity MoS₂ film, with a gate-last process to realize top gate structured FETs. A 62-level simulation program with integrated circuit emphasis (SPICE) model is utilized to design and optimize our analog ANN circuits. To demonstrate a practical application, a tactile digit sensing recognition was demonstrated based on our ANN circuits. After training, the digit recognition rate exceeds 97%. Our work not only demonstrates the protentional of 2D semiconductors in wafer-scale integrated circuits, but also paves the way for its future application in AI computation.

Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS₂ top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS₂ FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials.

Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.

Centimeter-Scale Few-Layer PdS2: Fabrication and Physical Properties

To develop next-generation electronic devices, novel semiconductive materials are urgently required. The transition metal dichalcogenides (TMDs) hold the promise of next generation of semiconductor materials for emerging electronic applications. As a member of the group-10 TMDs, PdS₂ has a notable layer-number-dependent band structure and tremendously high carrier mobility at room temperature. Here, we demonstrate the experimental realization of centimeter-scale synthesis of the few-layer PdS₂ by the combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods. For the first time, the optical anisotropic properties of the few-layer PdS₂ were investigated through angle-resolved polarized Raman spectroscopy. Also, the evolution of Raman spectra was studied depending on the temperature in the range of 12-300 K. To further understand the electronic properties of the few-layer PdS₂, the field-effect transistor (FET) devices were fabricated and investigated. The electronic measurements of such FET devices reveal that the PdS₂ materials exhibit a tunable ambipolar transport mechanism with field-effect mobility of up to ∼388 cm² V^-1 s^-1 and the on/off ratio of ∼800, which were not reported before in the literature. To well understand the experimental results, the electronic structure of PdS₂ was determined using density functional theory (DFT) calculations. These excellent physical properties are very helpful in developing high-performance opto-electronic applications.

Recent developments in 2D transition metal dichalcogenides: phase transition and applications of the (quasi-)metallic phases

The advent of two-dimensional transition metal dichalcogenides (2D-TMDs) has led to an extensive amount of interest amongst scientists and engineers alike and an intensive amount of research has brought about major breakthroughs in the electronic and optical properties of 2D materials. This in turn has generated considerable interest in novel device applications. With the polymorphic structural features of 2D-TMDs, this class of materials can exhibit both semiconducting and metallic (quasi-metallic) properties in their respective phases. This polymorphic property further increases the interest in 2D-TMDs both in fundamental research and for their potential utilization in novel high-performance device applications. In this review, we highlight the unique structural properties of few-layer and monolayer TMDs in the metallic 1T- and quasi-metallic 1T'-phases, and how these phases dictate their electronic and optical properties. An overview of the semiconducting-to-(quasi)-metallic phase transition of 2D-TMD systems will be covered along with a discussion on the phase transition mechanisms. The current development in the applications of (quasi)-metallic 2D-TMDs will be presented ranging from high-performance electronic and optoelectronic devices to energy storage, catalysis, piezoelectric and thermoelectric devices, and topological insulator and neuromorphic computing applications. We conclude our review by highlighting the challenges confronting the utilization of TMD-based systems and projecting the future developmental trends with an outlook of the progress needed to propel this exciting field forward.

Enhancing and quantifying spatial homogeneity in monolayer WS2

Controlling the radiative properties of monolayer transition metal dichalcogenides is key to the development of atomically thin optoelectronic devices applicable to a wide range of industries. A common problem for exfoliated materials is the inherent disorder causing spatially varying nonradiative losses and therefore inhomogeneity. Here we demonstrate a five-fold reduction in the spatial inhomogeneity in monolayer WS2, resulting in enhanced overall photoluminescence emission and quality of WS2 flakes, by using an ambient-compatible laser illumination process. We propose a method to quantify spatial uniformity using statistics of spectral photoluminescence mapping. Analysis of the dynamic spectral changes shows that the enhancement is due to a spatially sensitive reduction of the charged exciton spectral weighting. The methods presented here are based on widely adopted instrumentation. They can be easily automated, making them ideal candidates for quality assessment of transition metal dichalcogenide materials, both in the laboratory and industrial environments.

An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations

In-memory computing may enable multiply-accumulate (MAC) operations, which are the primary calculations used in artificial intelligence (AI). Performing MAC operations with high capacity in a small area with high energy efficiency remains a challenge. In this work, we propose a circuit architecture that integrates monolayer MoS₂ transistors in a two-transistor–one-capacitor (2T-1C) configuration. In this structure, the memory portion is similar to a 1T-1C Dynamic Random Access Memory (DRAM) so that theoretically the cycling endurance and erase/write speed inherit the merits of DRAM. Besides, the ultralow leakage current of the MoS₂ transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The electrical characteristics of a single MoS₂ transistor also allow analog computation by multiplying the drain voltage by the stored voltage on the capacitor. The sum-of-product is then obtained by converging the currents from multiple 2T-1C units. Based on our experiment results, a neural network is ex-situ trained for image recognition with 90.3% accuracy. In the future, such 2T-1C units can potentially be integrated into three-dimensional (3D) circuits with dense logic and memory layers for low power in-situ training of neural networks in hardware.

In standard computing architectures, memory and logic circuits are separated, a feature that slows matrix operations vital to deep learning algorithms. Here, the authors present an alternate in-memory architecture and demonstrate a feasible approach for analog matrix multiplication.

Dramatic Reduction of Contact Resistance via Ultrathin LiF in Two-Dimensional MoS2 Field Effect Transistors

Molybdenum disulfide (MoS₂) has been regarded as one of the most important n-type two-dimensional (2D) transition metal dichalcogenide semiconductors for nanoscale electron devices. Relatively high contact resistance (R_C) remains as an issue in the 2D-devices yet to be resolved. Reliable technique is very compelling to practically produce low R_C values in device electronics, although scientific approaches have been made to obtain a record-low R_C. To resolve this practical issue, we here use thermal-evaporated ultrathin LiF between channel and source/drain metal to fabricate 2D-like MoS₂ field effect transistors (FETs) with minimum R_C. Under 4-bar FET method, R_C less than ∼600 Ω·μm is achieved from the LiF/Au contact MoS₂ FET. Our normal 2-bar FET with LiF thus shows the same mobility as that of 4-bar FET that should have no R_C in principle. On the basis of these results, ultrathin LiF is also applied for transparent conducting oxide contact, successfully enabling transparent MoS₂ FETs.

A wafer-scale synthesis of monolayer MoS2 and their field-effect transistors toward practical applications

Molybdenum disulfide (MoS2) has attracted considerable research interest as a promising candidate for downscaling integrated electronics due to the special two-dimensional structure and unique physicochemical properties. However, it is still challenging to achieve large-area MoS2 monolayers with desired material quality and electrical properties to fulfill the requirement for practical applications. Recently, a variety of investigations have focused on wafer-scale monolayer MoS2 synthesis with high-quality. The 2D MoS2 field-effect transistor (MoS2-FET) array with different configurations utilizes the high-quality MoS2 film as channels and exhibits favorable performance. In this review, we illustrated the latest research advances in wafer-scale monolayer MoS2 synthesis by different methods, including Au-assisted exfoliation, CVD, thin film sulfurization, MOCVD, ALD, VLS method, and the thermolysis of thiosalts. Then, an overview of MoS2-FET developments was provided based on large-area MoS2 film with different device configurations and performances. The different applications of MoS2-FET in logic circuits, basic memory devices, and integrated photodetectors were also summarized. Lastly, we considered the perspective and challenges based on wafer-scale monolayer MoS2 synthesis and MoS2-FET for developing practical applications in next-generation integrated electronics and flexible optoelectronics.

Hidden Vacancy Benefit in Monolayer 2D Semiconductors

Monolayer 2D semiconductors (e.g., MoS₂ ) are of considerable interest for atomically thin transistors but generally limited by insufficient carrier mobility or driving current. Minimizing the lattice defects in 2D semiconductors represents a common strategy to improve their electronic properties, but has met with limited success to date. Herein, a hidden benefit of the atomic vacancies in monolayer 2D semiconductors to push their performance limit is reported. By purposely tailoring the sulfur vacancies (SVs) to an optimum density of 4.7% in monolayer MoS₂ , an unusual mobility enhancement is obtained and a record-high carrier mobility (>115 cm² V^-1 s^-1 ) is achieved, realizing monolayer MoS₂ transistors with an exceptional current density (>0.60 mA µm^-1 ) and a record-high on/off ratio >10¹⁰ , and enabling a logic inverter with an ultrahigh voltage gain >100. The systematic transport studies reveal that the counterintuitive vacancy-enhanced transport originates from a nearest-neighbor hopping conduction model, in which an optimum SV density is essential for maximizing the charge hopping probability. Lastly, the vacancy benefit into other monolayer 2D semiconductors is further generalized; thus, a general strategy for tailoring the charge transport properties of monolayer materials is defined.

Benchmarking monolayer MoS2 and WS2 field-effect transistors

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS₂ and WS₂ films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS₂ FETs and 160 WS₂ FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm² chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm² V^-1 s^-1 in WS₂ FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits.

Large-area synthesis of transition metal dichalcogenides via CVD and solution-based approaches and their device applications

For the last decade, two-dimensional transition metal dichalcogenides (TMDCs) have attracted considerable attention due to their unique physical and chemical properties. Novel devices based on these materials are commonly fabricated using the exfoliated samples, which lacks control of the thickness and cannot be scaled. Therefore, the synthesis of large-area TMDC thin films with a high uniformity to advance the field is required. This article reviews the latest advances in the synthesis of wafer-scale thin films using chemical vapor deposition methods. The key factors that determine the electrical performance of TMDCs are introduced, including the interfacial properties and defects. The latest solution-based techniques which suggest the opportunity to obtain large-area TMDC thin films with a low-cost process and the potential applications in electronics and optoelectronics are also discussed. The outlook for future research directions, challenges, and possible development of 2D materials are further discussed.

Wafer-Scale Highly Oriented Monolayer MoS2 with Large Domain Sizes

Two-dimensional molybdenum disulfide (MoS₂) is an emergent semiconductor with great potential in next-generation scaled-up electronics, but the production of high-quality monolayer MoS₂ wafers still remains a challenge. Here, we report an epitaxy route toward 4 in. monolayer MoS₂ wafers with highly oriented and large domains on sapphire. Benefiting from a multisource design for our chemical vapor deposition setup and the optimization of the growth process, we successfully realized material uniformity across the entire 4 in. wafer and greater than 100 μm domain size on average. These monolayers exhibit the best electronic quality ever reported, as evidenced from our spectroscopic and transport characterizations. Our work moves a step closer to practical applications of monolayer MoS₂.

High-Throughput Growth of Wafer-Scale Monolayer Transition Metal Dichalcogenide via Vertical Ostwald Ripening

For practical device applications, monolayer transition metal dichalcogenide (TMD) films must meet key industry needs for batch processing, including the high-throughput, large-scale production of high-quality, spatially uniform materials, and reliable integration into devices. Here, high-throughput growth, completed in 12 min, of 6-inch wafer-scale monolayer MoS₂ and WS₂ is reported, which is directly compatible with scalable batch processing and device integration. Specifically, a pulsed metal-organic chemical vapor deposition process is developed, where periodic interruption of the precursor supply drives vertical Ostwald ripening, which prevents secondary nucleation despite high precursor concentrations. The as-grown TMD films show excellent spatial homogeneity and well-stitched grain boundaries, enabling facile transfer to various target substrates without degradation. Using these films, batch fabrication of high-performance field-effect transistor (FET) arrays in wafer-scale is demonstrated, and the FETs show remarkable uniformity. The high-throughput production and wafer-scale automatable transfer will facilitate the integration of TMDs into Si-complementary metal-oxide-semiconductor platforms.

Low consumption two-terminal artificial synapse based on transfer-free single-crystal MoS2 memristor

Both synaptic emulators and brain-like calculation demand an energy-efficient and bio-realistic device where two-dimensional materials have been proven as a promising competitor. Lateral memristors based on transfer-free single-crystal MoS₂ with single layer grown by chemical vapor deposition (CVD) were fabricated. Here the MoS₂ memristor successfully emulates typical biological synaptic behaviors including excitatory/inhibitory post-synaptic current (EPSC/IPSC), spike timing-dependent plasticity (STDP), spike rate-dependent plasticity (SRDP) and long-term plasticity (LTP). Moreover, an interesting multi-state LTP and a low consumption of 1.8 pJ after LTP process are achieved which is attributed to the high resistance of transfer-free single-crystal monolayer MoS₂, representing a low value among previous MoS₂ devices. The migration of Sulfur vacancies lead the conductance modulation by changing the Schottky barrier instead of forming a filament. Our work demonstrates that MoS₂ memristors can more flexibly satisfy the demands of complex artificial synaptic/neuron applications.

Photodetector based on heterostructure of two-dimensional WSe2/In2Se3

Heterojunctions formed by two-dimensional (2D) layered semiconducting materials have been studied extensively in the past few years. These van der Waals (vdW) structures have shown great potential for future electronic and optoelectronic devices. However, the optoelectronic performance of these devices is limited by the indirect band gap of multilayer materials and low light absorption of single layer materials. Here, we fabricate photodetectors based on heterojunctions composed of n-type multilayer α-indium selenide (In₂Se₃) and p-type tungsten diselenide (WSe₂) for the first time. The direct band gap of multilayer α-In₂Se₃ and type-II band alignment of the WSe₂/In₂Se₃ heterojunction enable high optoelectronic performance of the devices at room temperature in the air. Without light illumination, the dark current is effectively suppressed to 10^-13 A under -1 V bias and a high rectification ratio of 7.37 × 10³ is observed. Upon laser illumination with a wavelength of 650 nm, the typical heterojunction device exhibits a photocurrent on/off ratio exceeding 1.24 × 10⁵, a maximum photo responsivity of 26 mA W^-1 and a short photoresponse time of 2.22 ms. Moreover, the heterojunction photodetectors show obvious light response in the wavelength range from 650 nm to 900 nm. The present 2D vdW heterojunctions composed of direct band gap multilayer materials show great potential for future optoelectronic devices.

Low-damaged p-type doping of MoS2 using direct nitrogen plasma modulated by toroidal-magnetic-field

Low damaged doping of two-dimensional (2D) materials proves to be a significant obstacle in realizing fundamental devices such as p-n junction diodes and transistors due to its atom layer thickness. In this work, the defect formation energy and p-type conduction behavior of nitrogen plasma doping are investigated by first principle calculation. Low damaged substitutional p-type doping in MoS₂ using low energy nitrogen plasma composed of N⁺ and N₂ ⁺ is achieved by a novel toroidal magnetic field (TMF). The TMF helps to raise the concentration of N₂ ⁺ ions at low RF power condition. The electrical characteristics of double-layer MoS₂ field-effect transistors (FETs) clearly show an efficient p-type doping behavior. Atomic force microscope is applied to verify the slight damage in MoS₂. X-ray photoelectron spectroscopy, photoluminescence and Raman spectroscopy confirm the effective p-type doping characteristic with weak damage. These findings provide a low damage technology for efficient carrier modulation of MoS₂ and other homogeneous TMDC materials, which overcomes barriers in developing 2D electronic and optoelectronic devices.

Probing Effective Out-of-Plane Piezoelectricity in van der Waals Layered Materials Induced by Flexoelectricity

Many van der Waals layered 2D materials, such as h-BN, transition metal dichalcogenides (TMDs), and group-III monochalcogenides, have been predicted to possess piezoelectric and mechanically flexible natures, which greatly motivates potential applications in piezotronic devices and nanogenerators. However, only intrinsic in-plane piezoelectricity exists in these 2D materials and the piezoelectric effect is confined in odd-layers of TMDs. The present work is intent on combining the free-standing design and piezoresponse force microscopy techniques to obtain and directly quantify the effective out-of-plane electromechanical coupling induced by strain gradient on atomically thin MoS₂ and InSe flakes. Conspicuous piezoresponse and the measured piezoelectric coefficient with respect to the number of layers or thickness are systematically illustrated for both MoS₂ and InSe flakes. Note that the promising effective piezoelectric coefficient (d^eff ₃₃ ) of about 21.9 pm V^-1 is observed on few-layered InSe. The out-of-plane piezoresponse arises from the net dipole moment along the normal direction of the curvature membrane induced by strain gradient. This work not only provides a feasible and flexible method to acquire and quantify the out-of-plane electromechanical coupling on van der Waals layered materials, but also paves the way to understand and tune the flexoelectric effect of 2D systems.

Negative Transconductance Heterojunction Organic Transistors and their Application to Full-Swing Ternary Circuits

Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H-TRs) exhibit negative transconductance (NTC) regions. Using the NTC characteristics of H-TRs, ternary inverters have recently been demonstrated. However, they have shown incomplete inverter characteristics; the output voltage (V_OUT ) does not fully swing from V_DD to G_ND . A new H-TR device structure that consists of a dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) layer stacked on a PTCDI-C13 layer is presented. Due to the continuous DNTT layer from source to drain, the proposed device exhibits novel switching behavior: p-type off/p-type subthreshold region /NTC/ p-type on. As a result, it has a very high on/off current ratio (≈10⁵ ) and exhibits NTC behavior. It is also demonstrated that an array of 36 of these H-TRs have 100% yield, a uniform on/off current ratio, and uniform NTC characteristics. Furthermore, the proposed ternary inverter exhibits full V_DD -to-G_ND swing of V_OUT with three distinct logic states. The proposed transistors and inverters exhibit hysteresis-free operation due to the use of a hydrophobic gate dielectric and encapsulating layers. Based on this, the transient operation of a ternary inverter circuit is demonstrated for the first time.

Wafer-scale transferred multilayer MoS2 for high performance field effect transistors

Chemical vapor deposition synthesis of semiconducting transition metal dichalcogenides (TMDs) offers a new route to build next-generation semiconductor devices. But realization of continuous and uniform multilayer (ML) TMD films is still limited by their specific growth kinetics, such as the competition between surface and interfacial energy. In this work, a layer-by-layer vacuum stacking transfer method is applied to obtain uniform and non-destructive ML-MoS₂ films. Back-gated field effect transistor (FET) arrays of 1L- and 2L-MoS₂ are fabricated on the same wafer, and their electrical performances are compared. We observe a significant increase of field-effect mobility for 2L-MoS₂ FETs, up to 32.5 cm² V^-1 s^-1, which is seven times higher than that of 1L-MoS₂ (4.5 cm² V^-1 s^-1). Then we also fabricated 1L-, 2L-, 3L-, and 4L-MoS₂ FETs to further investigate the thickness-dependent characteristics of transferred ML-MoS₂. Measurement results show a higher mobility but a smaller current on/off ratio as the layer number increases, suggesting that a balance between mobility and current on/off ratio can be achieved in 2L- and 3L-MoS₂ FETs. Dual-gated structure is also investigated to demonstrate an improved electrostatic control of the ML-MoS₂ channel.