Controllable P- and N-Type Conversion of MoTe2 via Oxide Interfacial Layer for Logic Circuits

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Defect Engineering of MoTe2 via Thiol Treatment for Type III van der Waals Heterojunction Phototransistor

Molybdenum ditelluride (MoTe2) nanosheets have displayed intriguing physicochemical properties and opto-electric characteristics as a result of their tunable and small band gap (Eg ∼ 1 eV), facilitating concurrent electron and hole transport. Despite the numerous efforts devoted to the development of p-type MoTe2 field-effect transistors (FETs), the presence of tellurium (Te) point vacancies has caused serious reliability issues. Here, we overcome this major limitation by treating the MoTe2 surface with thiolated molecules to heal Te vacancies. Comprehensive materials and electrical characterizations provided unambiguous evidence for the efficient chemisorption of butanethiol. Our thiol-treated MoTe2 FET exhibited a 10-fold increase in hole current and a positive threshold voltage shift of 25 V, indicative of efficient hole carrier doping. We demonstrated that our powerful molecular engineering strategy can be extended to the controlled formation of van der Waals heterostructures by developing an n-SnS2/thiol-MoTe2 junction FET (thiol-JFET). Notably, the thiol-JFET exhibited a significant negative photoresponse with a responsivity of 50 A W-1 and a fast response time of 80 ms based on band-to-band tunneling. More interestingly, the thiol-JFET displayed a gate tunable trimodal photodetection comprising two photoactive modes (positive and negative photoresponse) and one photoinactive mode. These findings underscore the potential of molecular engineering approaches in enhancing the performance and functionality of MoTe2-based nanodevices as key components in advanced 2D-based optoelectronics.

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

Nanoscale Channel Length MoS2 Vertical Field-Effect Transistor Arrays with Side-Wall Source/Drain Electrodes

Two-dimensional transition metal dichalcogenides (TMDCs) have natural advantages in overcoming the short-channel effect in field-effect transistors (FETs) and in fabricating three-dimensional FETs, which benefit in increasing device density. However, so far, most reported works related to MoS2 FETs with a sub-100 nm channel employ mechanically exfoliated materials and all of the works involve electron beam lithography (EBL), which may limit their application in fabricating wafer-scale device arrays as demanded in integrated circuits (ICs). In this work, MoS2 FET arrays with a side-wall source and drain electrodes vertically distributed are designed and fabricated. The channel length of the as-fabricated FET is basically determined by the thickness of an insulating layer between the source and drain electrodes. The vertically distributed source and drain electrodes enable to reduce the electrode-occupied area and increase in the device density. The as-fabricated vertical FETs exhibit on/off ratios comparable to those of mechanically exfoliated MoS2 FETs with a nanoscale channel length under identical VDS. In addition, the as-fabricated FETs can work at a VDS as low as 10 mV with a desirable on/off ratio (1.9 × 107), which benefits in developing low-power devices. Moreover, the fabrication process is free from EBL and can be applied to wafer-scale device arrays. The statistical results show that the fabricated FET arrays have a device yield of 87.5% and an average on/off ratio of about 1.7 × 106 at a VDS of 10 mV, with the lowest and highest ones to be about 1.3 × 104 and 1.9 × 107, respectively, demonstrating the good reliability of our fabrication process. Our work promises a bright future for TMDCs in realizing high-density and low-power nanoelectronic devices in ICs.

Nonconventional Strain Engineering for Uniform Biaxial Tensile Strain in MoS2 Thin Film Transistors

Strain engineering has been employed as a crucial technique to enhance the electrical properties of semiconductors, especially in Si transistor technologies. Recent theoretical investigations have suggested that strain engineering can also markedly enhance the carrier mobility of two-dimensional (2D) transition-metal dichalcogenides (TMDs). The conventional methods used in strain engineering for Si and other bulk semiconductors are difficult to adapt to ultrathin 2D TMDs. Here, we report a strain engineering approach to apply the biaxial tensile strain to MoS2. Metal-organic chemical vapour deposition (MOCVD)-grown large-area MoS2 films were transferred onto SiO2/Si substrate, followed by the selective removal of the underneath Si. The release of compressive residual stress in the oxide layer induces strain in MoS2 on top of the SiO2 layer. The amount of strain can be precisely controlled by the thickness of oxide stressors. After the transistors were fabricated with strained MoS2 films, the array of strained transistors was transferred onto plastic substrates. This process ensured that the MoS2 channels maintained a consistent tensile strain value across a large area.

Content-Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing

As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.

2D Materials in Flexible Electronics: Recent Advances and Future Prospectives

Flexible electronics have recently gained considerable attention due to their potential to provide new and innovative solutions to a wide range of challenges in various electronic fields. These electronics require specific material properties and performance because they need to be integrated into a variety of surfaces or folded and rolled for newly formatted electronics. Two-dimensional (2D) materials have emerged as promising candidates for flexible electronics due to their unique mechanical, electrical, and optical properties, as well as their compatibility with other materials, enabling the creation of various flexible electronic devices. This article provides a comprehensive review of the progress made in developing flexible electronic devices using 2D materials. In addition, it highlights the key aspects of materials, scalable material production, and device fabrication processes for flexible applications, along with important examples of demonstrations that achieved breakthroughs in various flexible and wearable electronic applications. Finally, we discuss the opportunities, current challenges, potential solutions, and future investigative directions about this field.

Large-Scale Complementary Logic Circuit Enabled by Al2O3 Passivation-Induced Carrier Polarity Modulation in Tungsten Diselenide

Achieving effective polarity control of n- and p-type transistors based on two-dimensional (2D) materials is a critical challenge in the process of integrating transition metal dichalcogenides (TMDC) into complementary metal-oxide semiconductor (CMOS) logic circuits. Herein, we utilized a proficient and nondestructive method of electron-charge transfer to achieve a complete carrier polarity conversion from p-to n-type by depositing a thin layer of aluminum oxide (Al2O3) onto tungsten diselenide (WSe2). By utilizing the Al2O3 passivation layer, we observed precisely tuned n-type behavior in contrast to transistors fabricated on the as-grown WSe2 film without any passivation layer, which display prominent p-type behavior. The polarity-transformed n-type WSe2 transistor from the pristine p-type shows the maximum ON current of ∼0.1 μA accompanied by a high electron mobility of 7 cm2 V-1 s-1 at a drain voltage (VDS) of 1 V. We successfully showcased a homogeneous CMOS inverter utilizing 2D-TMDC which exhibits an impressive voltage gain of 7 at VDD = 5 V. Moreover, this effective polarity control approach was further expanded upon to successfully demonstrate a range of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. The proposed methodology possesses significant promise for facilitating the advancement of high-density circuitry components utilizing 2D-TMDC.

Fabrication of p-type 2D single-crystalline transistor arrays with Fermi-level-tuned van der Waals semimetal electrodes

High-performance p-type two-dimensional (2D) transistors are fundamental for 2D nanoelectronics. However, the lack of a reliable method for creating high-quality, large-scale p-type 2D semiconductors and a suitable metallization process represents important challenges that need to be addressed for future developments of the field. Here, we report the fabrication of scalable p-type 2D single-crystalline 2H-MoTe2 transistor arrays with Fermi-level-tuned 1T'-phase semimetal contact electrodes. By transforming polycrystalline 1T'-MoTe2 to 2H polymorph via abnormal grain growth, we fabricated 4-inch 2H-MoTe2 wafers with ultra-large single-crystalline domains and spatially-controlled single-crystalline arrays at a low temperature (~500 °C). Furthermore, we demonstrate on-chip transistors by lithographic patterning and layer-by-layer integration of 1T' semimetals and 2H semiconductors. Work function modulation of 1T'-MoTe2 electrodes was achieved by depositing 3D metal (Au) pads, resulting in minimal contact resistance (~0.7 kΩ·μm) and near-zero Schottky barrier height (~14 meV) of the junction interface, and leading to high on-state current (~7.8 μA/μm) and on/off current ratio (~105) in the 2H-MoTe2 transistors.

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2

In this work, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS₂ and p-MoTe₂ grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO₂ is used as the gate dielectric. An Al₂ O₃ seed layer is used to protect the MoS₂ from heavily n-doping in the later-on atomic layer deposition process. P-MoTe₂ FET is intentionally designed as the upper layer. Because p-doping of MoTe₂ results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe₂ . An HfO₂ capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at V_DD of 1 V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at V_DD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.

Emerging 2D Metal Oxides: From Synthesis to Device Integration

2D metal oxides have aroused increasing attention in the field of electronics and optoelectronics due to their intriguing physical properties. In this review, an overview of recent advances on synthesis of 2D metal oxides and their electronic applications is presented. First, the tunable physical properties of 2D metal oxides that relate to the structure (various oxidation-state forms, polymorphism, etc.), crystallinity and defects (anisotropy, point defects, and grain boundary), and thickness (quantum confinement effect, interfacial effect, etc.) are discussed. Then, advanced synthesis methods for 2D metal oxides besides mechanical exfoliation are introduced and classified into solution process, vapor-phase deposition, and native oxidation on a metal source. Later, the various roles of 2D metal oxides in widespread applications, i.e., transistors, inverters, photodetectors, piezotronics, memristors, and potential applications (solar cell, spintronics, and superconducting devices) are discussed. Finally, an outlook of existing challenges and future opportunities in 2D metal oxides is proposed.

Digital Keying Enabled by Reconfigurable 2D Modulators

Energy, area, and bandwidth efficient communication primitives are essential to sustain the rapid increase in connectivity among internet-of-things (IoT) edge devices. While IoT edge-sensing, edge-computing, and edge-storage have witnessed innovation in materials and devices, IoT edge communication is yet to experience such transformation. The aging silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology continues to remain the mainstay of communication devices where they are used to implement amplitude, frequency, and phase shift keying (amplitude-shift keying [ASK]/frequency-shift keying [FSK]/phase-shift keying [PSK]). Keying allows digital information to be communicated over a radio channel. While CMOS-based keying devices have evolved over the years, their hardware footprint and energy consumption are major concerns for resource constrained IoT communication. Furthermore, separate circuit designs and hardware elements are needed for each keying scheme and achieving multibit modulation to improve bandwidth efficiency remains a challenge. Here, a reconfigurable modulator is introduced that exploits unique ambipolar transport and programmable Dirac voltage in ultrathin MoTe₂ field-effect transistors to achieve ASK, FSK, and PSK modulation. Furthermore, by integrating two programmed MoTe₂ field-effect transistors, multibit data modulation is demonstrated, which improves the bandwidth efficiency by 200%. Finally, a frequency quadrupler is also realized exploiting the unique "double-well" transfer characteristic.

Diffused Beam Energy to Dope van der Waals Electronics and Boost Their Contact Barrier Lowering

Contact engineering of two-dimensional semiconductors is a central issue for performance improvement of micro-/nanodevices based on these materials. Unfortunately, the various methods proposed to improve the Schottky barrier height normally require the use of high temperatures, chemical dopants, or complex processes. This work demonstrates that diffused electron beam energy (DEBE) treatment can simultaneously reduce the Schottky barrier height and enable the direct writing of electrical circuitry on van der Waals semiconductors. The electron beam energy projected into the region outside the electrode diffuses into the main channel, producing selective-area n-type doping in a layered MoTe₂ (or MoS₂) field-effect transistor. As a result, the Schottky barrier height at the interface between the electrode and the DEBE-treated MoTe₂ channel is as low as 12 meV. Additionally, because selective-area doping is possible, DEBE can allow the formation of both n- and p-type doped channels within the same atomic plane, which enables the creation of a nonvolatile and homogeneous MoTe₂ p-n rectifier with an ideality factor of 1.1 and a rectification ratio of 1.3 × 10³. These results indicate that the DEBE method is a simple, efficient, mask-free, and chemical dopant-free approach to selective-area doping for the development of van der Waals electronics with excellent device performances.

Atomistic Observation of the Local Phase Transition in MoTe2 for Application in Homojunction Photodetectors

Direct atomic-scale observation of the local phase transition in transition metal dichalcogenides (TMDCs) is critically required to carry out in-depth studies of their atomic structures and electronic features. However, the structural aspects including crystal symmetries tend to be unclear and unintuitive in real-time monitoring of the phase transition process. Herein, by using in situ transmission electron microscopy, information about the phase transition mechanism of MoTe₂ from hexagonal structure (2H phase) to monoclinic structure (1T' phase) driven by sublimation of Te atoms after a spike annealing is obtained directly. Furthermore, with the control of Te atom sublimation by modulating the hexagonal boron nitride (h-BN) coverage in the desired area, the lateral 1T'-enriched MoTe₂ /2H MoTe₂ homojunction can be one-step constructed via an annealing treatment. Owing to the gradient bandgap provided by 1T'-enriched MoTe₂ and 2H MoTe₂ , the photodetector composed of the 1T'-enriched MoTe₂ /2H MoTe₂ homojunction shows fast photoresponse and ten times larger photocurrents than that consisting of a pure 2H MoTe₂ channel. The study reveals a route to improve the performance of optoelectronic and electronic devices based on TMDCs with both semiconducting and semimetallic phases.

Low-power-consumption CMOS inverter array based on CVD-grown p-MoTe2 and n-MoS2

Two-dimensional (2D) semi-conductive transition metal dichalcogenides (TMDCs) have shown advantages for logic application. Complementary metal-oxide-semiconductor (CMOS) inverter is an important component in integrated circuits in view of low power consumption. So far, the performance of the reported TMDCs-based CMOS inverters is not satisfactory. Besides, most of the inverters were made of mechanically exfoliated materials, which hinders their reproducible production and large-scale integration in practical application. In this study, we demonstrate a practical approach to fabricate CMOS inverter arrays using large-area p-MoTe₂ and n-MoS₂, which are grown via chemical vapor deposition method. The current characteristics of the channel materials are balanced by atomic layer depositing Al₂O₃. Complete logic swing and clear dynamic switching behavior are observed in the inverters. Especially, ultra-low power consumption of ∼0.37 nW is achieved. Our work paves the way for the application of 2D TMDCs materials in large-scale low-power-consumption logic circuits.

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A practical approach to fabricate large-scale CMOS inverter arrays is demonstrated

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A method to balance the current characteristics of the channel materials is developed

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Complete logic swing and clear dynamic switching behavior are observed

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Ultra-low power consumption of ∼0.37 nW is achieved

Substitutionally Doped MoSe2 for High-Performance Electronics and Optoelectronics

2D materials, of which the carrier type and concentration are easily tuned, show tremendous superiority in electronic and optoelectronic applications. However, the achievements are still quite far away from practical applications. Much more effort should be made to further improve their performance. Here, p-type MoSe₂ is successfully achieved via substitutional doping of Ta atoms, which is confirmed experimentally and theoretically, and outstanding homojunction photodetectors and inverters are fabricated. MoSe₂ p-n homojunction device with a low reverse current (300 pA) exhibits a high rectification ratio (10⁴ ). The analysis of dark current reveals the domination of the Shockley-Read-Hall (SRH) and band-to-band tunneling (BTB) current. The homojunction photodetector exhibits a large open-circuit voltage (0.68 V) and short-circuit currents (1 µA), which is suitable for micro-solar cells. Furthermore, it possesses outstanding responsivity (0.28 A W^-1 ), large external quantum efficiency (42%), and a high signal-to-noise ratio (≈10⁷ ). Benefiting from the continuous energy band of homojunction, the response speed reaches up to 20 µs. Besides, the Ta-doped MoSe₂ inverter exhibits a high voltage gain (34) and low power consumption (127 nW). This work lays a foundation for the practical application of 2D material devices.

Atomic-Layer-Deposition-Based 2D Transition Metal Chalcogenides: Synthesis, Modulation, and Applications

Transition metal chalcogenides (TMCs) are a large family of 2D materials with different properties, and are promising candidates for a wide range of applications such as nanoelectronics, sensors, energy conversion, and energy storage. In the research of new materials, the development and investigation of industry-compatible synthesis techniques is of key importance. In this respect, it is important to study 2D TMC materials synthesized by the atomic layer deposition (ALD) technique, which is widely applied in industries. In addition to the synthesis of 2D TMCs, ALD is used to modulate the characteristic of 2D TMCs such as their carrier density and morphology. So far, the improvement of thin film uniformity without oxidation and the synthesis of low-dimensional nanomaterials on 2D TMCs have been the research focus. Herein, the synthesis and modulation of 2D TMCs by ALD is described, and the characteristics of ALD-based TMCs used in nanoelectronics, sensors, and energy applications are discussed.

Ambipolar 2D Semiconductors and Emerging Device Applications

With the rise of 2D materials, new physics and new processing techniques have emerged, triggering possibilities for the innovation of electronic and optoelectronic devices. Among them, ambipolar 2D semiconductors are of excellent gate-controlled capability and distinctive physical characteristic that the major charge carriers can be dynamically, reversibly and rapidly tuned between holes and electrons by electrostatic field. Based on such properties, novel devices, like ambipolar field-effect transistors, light-emitting transistors, electrostatic-field-charging PN diodes, are developed and show great advantages in logic and reconfigurable circuits, integrated optoelectronic circuits, and artificial neural network image sensors, enriching the functions of conventional devices and bringing breakthroughs to build new architectures. This review first focuses on the basic knowledge including fundamental principle of ambipolar semiconductors, basic material preparation techniques, and how to obtain the ambipolar behavior through electrical contact engineering. Then, the current ambipolar 2D semiconductors and their preparation approaches and main properties are summarized. Finally, the emerging new device structures are overviewed in detail, along with their novel electronic and optoelectronic applications. It is expected to shed light on the future development of ambipolar 2D semiconductors, exploring more new devices with novel functions and promoting the applications of 2D materials.

Emerging Opportunities for Electrostatic Control in Atomically Thin Devices

Electrostatic control of charge carrier concentration underlies the field-effect transistor (FET), which is among the most ubiquitous devices in the modern world. As transistors and related electronic devices have been miniaturized to the nanometer scale, electrostatics have become increasingly important, leading to progressively sophisticated device geometries such as the finFET. With the advent of atomically thin materials in which dielectric screening lengths are greater than device physical dimensions, qualitatively different opportunities emerge for electrostatic control. In this Review, recent demonstrations of unconventional electrostatic modulation in atomically thin materials and devices are discussed. By combining low dielectric screening with the other characteristics of atomically thin materials such as relaxed requirements for lattice matching, quantum confinement of charge carriers, and mechanical flexibility, high degrees of electrostatic spatial inhomogeneity can be achieved, which enables a diverse range of gate-tunable properties that are useful in logic, memory, neuromorphic, and optoelectronic technologies.