Amorphous IGZO TFT with High Mobility of ∼70 cm2/(V s) via Vertical Dimension Control Using PEALD

Ultrathin α-Bi2O3 Thin-Film Transistor for Cost-Effective Oxide-TFT Inverters

Electronics is advancing toward greater diversity and sustainability by prioritizing energy efficiency and cost-effectiveness. Metal oxide thin-film transistor (TFT) represents a technology at the forefront of advancing next-generation sustainable electronics, and exploring oxide channel compositions is a crucial step in opening opportunities for developing next-generation device applications. This study presents the first development of n-channel α-Bi2O3-TFTs using a 4 nm ultrathin channel prepared by a cost-effective vacuum-free and solvent-free liquid metal printing method in ambient air. Even the pristine device exhibited a clear TFT action but required a large negative gate bias to turn off due mainly to excess carriers from oxygen vacancy in the α-Bi2O3 channel. Oxygen-containing post-annealing reduced both channel carrier and subgap defect densities, enabling the development of depletion and enhancement-type α-Bi2O3-TFTs with the saturation mobility of 2-4 cm2 V-1 s-1. Two types of oxide-TFT-based inverter circuits, zero-VGS-NMOS and CMOS inverters, were fabricated by using α-Bi2O3-TFTs, operating in a high voltage gain of over 130. This work demonstrates the potential of oxide semiconductor materials toward the development of next-generation sustainable electronics.

Ultralow-Power Circuit and Sensing Applications Based on Subthermionic Threshold Switching Transistors

The most recent breakthrough in state-of-the-art electronics and optoelectronics involves the adoption of steep-slope field-effect transistors (FETs), promoting sub-60 mV/dec subthreshold swing (SS) at ambient temperature, effectively overcoming "Boltzmann limit" to minimize power consumption. Here, a series integration of nanoscale copper-based resistive-filamentary threshold switch (TS) with the IGZO channel-based FET is used to develop a TS-FET, in which the turn-on characteristics exhibit an abrupt transition over five decades, with an extremely low SS of 7 mV/dec, a high on/off ratio (>109), and ultralow leakage current (40-fold decrease), ensuring excellent repeatability and device yield. Unlike previous device-centric studies, this work highlights potential circuit applications (logic-inverter, pulse-sensor amplification, and photodetector) based on TS-FET. The sharp transition behavior of TS-FET enables the establishment of logic inverters with a high voltage gain of ≈800, with a circuit-level demonstration achieving a bias-independent record-high intrinsic gain (>1000). A wearable pulse sensor integrated with an amplifier circuit ensured the precise amplification of electrophysical signals by 450 times. In addition, the application of a TS-FET-based photodetector features high responsivity (1.08 × 104 mA/W) and detectivity (1.03 × 1020 Jones). The low-power strategy of TS-FETs is promising for the development of energy-efficient integrated circuits alongside sensor-interconnected biomedical applications in wearable technology.

A Review of Wide Bandgap Semiconductors: Insights into SiC, IGZO, and Their Defect Characteristics

Although the irreplaceable position of silicon (Si) semiconductor materials in the field of information has become a consensus, new materials continue to be sought to expand the application range of semiconductor devices. Among them, research on wide bandgap semiconductors has already achieved preliminary success, and the relevant achievements have been applied in the fields of energy conversion, display, and storage. However, similar to the history of Si, the immature material grown and device manufacturing processes at the current stage seriously hinder the popularization of wide bandgap semiconductor-based applications, and one of the crucial issues behind this is the defect problem. Here, we take amorphous indium gallium zinc oxide (a-IGZO) and 4H silicon carbide (4H-SiC) as two representatives to discuss physical/mechanical properties, electrical performance, and stability from the perspective of defects. Relevant experimental and theoretical works on defect formation, evolution, and annihilation are summarized, and the impacts on carrier transport behaviors are highlighted. State-of-the-art applications using the two materials are also briefly reviewed. This review aims to assist researchers in elucidating the complex impacts of defects on electrical behaviors of wide bandgap semiconductors, enabling them to make judgments on potential defect issues that may arise in their own processes. It aims to contribute to the effort of using various post-treatment methods to control defect behaviors and achieve the desired material and device performance.

Reliable Operation in High-Mobility Indium Oxide Thin Film Transistors

Transparent oxide semiconductors (TOSs) based thin-film transistors (TFTs) that exhibit higher field effect mobility (µFE) are highly required toward the realization of next-generation displays. Among numerous types of TOS-TFTs, In2O3-based TFTs are the front-running candidate because they exhibit the highest µFE ≈100 cm2 V-1 s-1. However, the device operation of In2O3 TFTs is unreliable; a large voltage shift occurs especially when negative gate bias is applied due to adsorption/desorption of gas molecules. Although passivation of the TFTs is used to overcome such instability, previously proposed passivation materials do not improve the reliability. Here, it is shown that the In2O3 TFTs passivated with Y2O3 and Er2O3 films are highly reliable and do not show threshold voltage shifts when applying gate bias. Positive and negative gate bias is applied to the In2O3 TFTs passivated with various insulating oxides and found that only the In2O3 TFTs passivated with Y2O3 and Er2O3 films do not exhibit threshold voltage shifts. It is observed that only the Y2O3 grew heteroepitaxially on the In2O3 crystal. This is the origin of the high reliability of the In2O3 TFTs passivated with Y2O3 and Er2O3 films. This finding accelerates the development of next-generation displays using high-mobility In2O3 TFTs.

Effect of interface defects on electrical characteristics of a-ITGZO TFTs under bottom, top, and dual gatings

Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm2/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.6 cm2/V∙s, 301 mV/decade) and bottom (11.1 cm2/V∙s, 487 mV/decade) gatings. For an a-ITGZO TFT, oxygen deficiencies are more prevalent in the bottom-gate dielectric interface than in the top-gate dielectric interface, and they are less prevalent inside the channel layer than at the interfaces, indicating that the presence of oxygen deficiencies significantly affects the field-effect mobility and subthreshold swing. Moreover, the variation in the electrical characteristics due to the positive bias stress is discussed here.

Inkjet printed IGZO memristors with volatile and non-volatile switching

Solution-based memristors deposited by inkjet printing technique have a strong technological potential based on their scalability, low cost, environmentally friendlier processing by being an efficient technique with minimal material waste. Indium-gallium-zinc oxide (IGZO), an oxide semiconductor material, shows promising resistive switching properties. In this work, a printed Ag/IGZO/ITO memristor has been fabricated. The IGZO thickness influences both memory window and switching voltage of the devices. The devices show both volatile counter8wise (c8w) and non-volatile 8wise (8w) switching at low operating voltage. The 8w switching has a SET and RESET voltage lower than 2 V and - 5 V, respectively, a retention up to 105 s and a memory window up to 100, whereas the c8w switching shows volatile characteristics with a low threshold voltage (Vth < - 0.65 V) and a characteristic time (τ) of 0.75 ± 0.12 ms when a single pulse of - 0.65 V with width of 0.1 ms is applied. The characteristic time alters depending on the number of pulses. These volatile characteristics allowed them to be tested on different 4-bit pulse sequences, as an initial proof of concept for temporal signal processing applications.

Graded-Band-Gap Zinc-Tin Oxide Thin-Film Transistors with a Vertically Stacked Structure for Wavelength-Selective Photodetection

Filter-free wavelength-selective photodetectors have garnered significant attention due to the growing demand for smart sensors, artificial intelligence, the Internet of Everything, and so forth. However, the challenges associated with large-scale preparation and compatibility with complementary metal-oxide-semiconductor (CMOS) technology limit their wide-ranging applications. In this work, we address the challenges by constructing vertically stacked graded-band-gap zinc-tin oxide (ZTO) thin-film transistors (TFTs) specifically designed for wavelength-selective photodetection. The ZTO thin films with various band gaps are fabricated via atomic layer deposition (ALD) by varying the ALD cycle ratios of zinc oxide (ZnO) and SnO2. The ZTO film with a small Sn ratio exhibits a decreased band gap, and the resultant TFT shows a degraded performance, which can be attributed to the Sn4+ dopant introducing a series of deep-state energy levels in the ZnO band gap. As the ratio of Sn increases further, the band gap of the ZTO also increases, and the mobility of the ZTO TFT increases up to 30 cm2/V s, with a positive shift of the threshold voltage. The photodetectors employing ZTO thin films with distinct band gaps show different spectral responsivities. Then, vertically stacked ZTO (S-ZTO) thin films, with gradient band gaps increasing from the bottom to the top, have been successfully deposited using consecutive ALD technology. The S-ZTO TFT shows decent performance with a mobility of 18.4 cm2/V s, a threshold voltage of 0.5 V, an on-off current ratio higher than 107, and excellent stability under ambient conditions. The resultant S-ZTO TFT also exhibits obviously distinct photoresponses to light at different wavelength ranges. Furthermore, a device array of S-ZTO TFTs demonstrates color imaging by precisely reconstructing patterned illuminations with different wavelengths. Therefore, this work provides CMOS-compatible and structure-compact wavelength-selective photodetectors for advanced and integrable optoelectronic applications.

c-Axis Aligned 3 nm Thick In2O3 Crystal Using New Liquid DBADMIn Precursor for Highly Scaled FET Beyond the Mobility-Stability Trade-off

Oxide semiconductors (OS) are attractive materials for memory and logic device applications owing to their low off-current, high field effect mobility, and superior large-area uniformity. Recently, successful research has reported the high field-effect mobility (μFE) of crystalline OS channel transistors (above 50 cm2 V-1 s-1). However, the memory and logic device application presents challenges in mobility and stability trade-offs. Here, we propose a method for achieving high-mobility and high-stability by lowering the grain boundary effect. A DBADMIn precursor was synthesized to deposit highly c-axis-aligned C(222) crystalline 3 nm thick In2O3 films. In this study, the 250 °C deposited 3 nm thick In2O3 channel transistor exhibited high μFE of 41.12 cm2 V-1 s-1, Vth of -0.50 V, and SS of 150 mV decade-1 with superior stability of 0.16 V positive shift during PBTS at 100 °C, 3 MV cm-1 stress conditions for 3 h.

Implementation of Artificial Synapse Using IGZO-Based Resistive Switching Device

In this study, we present the resistive switching characteristics and the emulation of a biological synapse using the ITO/IGZO/TaN device. The device demonstrates efficient energy consumption, featuring low current resistive switching with minimal set and reset voltages. Furthermore, we establish that the device exhibits typical bipolar resistive switching with the coexistence of non-volatile and volatile memory properties by controlling the compliance during resistive switching phenomena. Utilizing the IGZO-based RRAM device with an appropriate pulse scheme, we emulate a biological synapse based on its electrical properties. Our assessments include potentiation and depression, a pattern recognition system based on neural networks, paired-pulse facilitation, excitatory post-synaptic current, and spike-amplitude dependent plasticity. These assessments confirm the device's effective emulation of a biological synapse, incorporating both volatile and non-volatile functions. Furthermore, through spike-rate dependent plasticity and spike-timing dependent plasticity of the Hebbian learning rules, high-order synapse imitation was done.

Machine Learning Driven Channel Thickness Optimization in Dual-Layer Oxide Thin-Film Transistors for Advanced Electrical Performance

Machine learning (ML) provides temporal advantage and performance improvement in practical electronic device design by adaptive learning. Herein, Bayesian optimization (BO) is successfully applied to the design of optimal dual-layer oxide semiconductor thin film transistors (OS TFTs). This approach effectively manages the complex correlation and interdependency between two oxide semiconductor layers, resulting in the efficient design of experiment (DoE) and reducing the trial-and-error. Considering field effect mobility (𝜇) and threshold voltage (Vth ) simultaneously, the dual-layer structure designed by the BO model allows to produce OS TFTs with remarkable electrical performance while significantly saving an amount of experimental trial (only 15 data sets are required). The optimized dual-layer OS TFTs achieve the enhanced field effect mobility of 36.1 cm2  V-1  s-1 and show good stability under bias stress with negligible difference in its threshold voltage compared to conventional IGZO TFTs. Moreover, the BO algorithm is successfully customized to the individual preferences by applying the weight factors assigned to both field effect mobility (𝜇) and threshold voltage (Vth ).

Uniform multilevel switching and synaptic properties in RF-sputtered InGaZnO-based memristor treated with oxygen plasma

Bipolar gradual resistive switching was investigated in ITO/InGaZnO/ITO resistive switching devices. Controlled intrinsic oxygen vacancy formation inside the switching layer enabled the establishment of a stable multilevel memory state, allowing for RESET voltage control and non-degradable data endurance. The ITO/InGaZnO interface governs the migration of oxygen ions and redox reactions within the switching layer. Voltage-stress-induced electron trapping and oxygen vacancy formation were observed before conductive filament electroforming. This device mimicked biological synapses, demonstrating short- and long-term potentiation and depression through electrical pulse sequences. Modulation of post-synaptic currents and pulse frequency-dependent short-term potentiation were successfully emulated in the InGaZnO-based artificial synapse. The ITO/InGaZnO/ITO memristor exhibited spike-amplitude-dependent plasticity, spike-rate-dependent plasticity, and potentiation-depression synaptic learning with low energy consumption, making it a promising candidate for large-scale integration.

Tunable-performance all-oxide structure field-effect transistor based atomic layer deposited Hf-doped In2O3 thin films

The relocation of peripheral transistors from the front-end-of-line (FEOL) to the back-end-of-line (BEOL) in fabrication processes is of significant interest, as it allows for the introduction of novel functionality in the BEOL while providing additional die area in the FEOL. Oxide semiconductor-based transistors serve as attractive candidates for BEOL. Within these categories, In2O3 material is particularly notable; nonetheless, the excessive intrinsic carrier concentration poses a limitation on its broader applicability. Herein, the deposition of Hf-doped In2O3 (IHO) films via atomic layer deposition for the first time demonstrates an effective method for tuning the intrinsic carrier concentration, where the doping concentration plays a critical role in determine the properties of IHO films and all-oxide structure transistors with Au-free process. The all-oxide transistors with In2O3: HfO2 ratio of 10:1 exhibited optimal electrical properties, including high on-current with 249 µA, field-effect mobility of 13.4 cm2 V-1 s-1, and on/off ratio exceeding 106, and also achieved excellent stability under long time positive bias stress and negative bias stress. These findings suggest that this study not only introduces a straightforward and efficient approach to improve the properties of In2O3 material and transistors, but as well paves the way for development of all-oxide transistors and their integration into BEOL technology.

Monolithic Integration of Semi-Transparent and Flexible Integrated Image Sensor Array with a-IGZO Thin-Film Transistors (TFTs) and p-i-n Hydrogenated Amorphous Silicon Photodiodes

A novel approach to fabricating a transparent and flexible one-transistor-one-diode (1T-1D) image sensor array on a flexible colorless polyimide (CPI) film substrate is successfully demonstrated with laser lift-off (LLO) techniques. Leveraging transparent indium tin oxide (ITO) electrodes and amorphous indium gallium zinc oxide (a-IGZO) channel-based thin-film transistor (TFT) backplanes, vertically stacked p-i-n hydrogenated amorphous silicon (a-Si:H) photodiodes (PDs) utilizing a low-temperature (<90 °C) deposition process are integrated with a densely packed 14 × 14 pixel array. The low-temperature-processed a-Si:H photodiodes show reasonable performance with responsivity and detectivity for 31.43 mA/W and 3.0 × 1010 Jones (biased at -1 V) at a wavelength of 470 nm, respectively. The good mechanical durability and robustness of the flexible image sensor arrays enable them to be attached to a curved surface with bending radii of 20, 15, 10, and 5 mm and 1000 bending cycles, respectively. These studies show the significant promise of utilizing highly flexible and rollable active-matrix technology for the purpose of dynamically sensing optical signals in spatial applications.

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors

Top-gate self-aligned structured oxide thin-film transistors (TFTs) are suitable for the backplanes of high-end displays because of their low parasitic capacitances. The gate insulator (GI) deposition process should be carefully designed to manufacture a highly stable, high-mobility oxide TFT, particularly for a top-gate structure. In this study, a nanometer-thick Al2O3 layer via plasma-enhanced atomic layer deposition (PE-ALD) is deposited on the top-gate bottom-contact structured oxide TFT as the interface tailoring layer, which can also act as the hydrogen barrier to modulate carrier generation from hydrogen incorporation into the active layer of the TFT during the following process such as postannealing. Al-doped InSnZnO (Al/ITZO) with an Al/In/Sn/Zn atomic ratio composition of 1.7:24.3:40:34 was used for high mobility oxide semiconductors, and an Al2O3/Si3N4 bilayer was used for the GI. The degradation issue due to the excellent barrier characteristics of Al2O3 and Si3N4 can be minimized. An oxide TFT fabricated without the interface tailoring layer exhibits conductor-like characteristics owing to the excessive carrier generation by hydrogen incorporation. However, TFTs with additional interface layers exhibit reasonable characteristics and distinct trends in electrical characteristics depending on the thicknesses of the interface layers. The optimized devices exhibit an average turn-on voltage (Von) of -0.31 V with 33.63 cm2/(V s) of high mobility and 0.09 V/dec of subthreshold swing value. The interfaces between the active layer and hydrogen barriers were investigated using a high-resolution transmission electron microscope, contact angle measurement, and secondary ion mass spectroscopy to reveal the origin of the trends in properties between the devices. The top-gate device with a hydrogen barrier using the four-cycle deposition exhibits optimum electrical characteristics of both high mobility and good stability with only a 0.04 V shift of Von under positive-bias temperature stress (PBTS). We realize a high-end, self-aligned TFT with high mobility [34.7 cm2/(V s)] and negligible Von shift of -0.06 V under PBTS by applying a subnanometer hydrogen barrier.

Progress, Challenges, and Opportunities in Oxide Semiconductor Devices: A Key Building Block for Applications Ranging from Display Backplanes to 3D Integrated Semiconductor Chips

As Si has faced physical limits on further scaling down, novel semiconducting materials such as 2D transition metal dichalcogenides and oxide semiconductors (OSs) have gained tremendous attention to continue the ever-demanding downscaling represented by Moore's law. Among them, OS is considered to be the most promising alternative material because it has intriguing features such as modest mobility, extremely low off-current, great uniformity, and low-temperature processibility with conventional complementary-metal-oxide-semiconductor-compatible methods. In practice, OS has successfully replaced hydrogenated amorphous Si in high-end liquid crystal display devices and has now become a standard backplane electronic for organic light-emitting diode displays despite the short time since their invention in 2004. For OS to be implemented in next-generation electronics such as back-end-of-line transistor applications in monolithic 3D integration beyond the display applications, however, there is still much room for further study, such as high mobility, immune short-channel effects, low electrical contact properties, etc. This study reviews the brief history of OS and recent progress in device applications from a material science and device physics point of view. Simultaneously, remaining challenges and opportunities in OS for use in next-generation electronics are discussed.

Approaches for 3D Integration Using Plasma-Enhanced Atomic-Layer-Deposited Atomically-Ordered InGaZnO Transistors with Ultra-High Mobility

As the scale-down and power-saving of silicon-based channel materials approach the limit, oxide semiconductors are being actively researched for applications in 3D back-end-of-line integration. For these applications, it is necessary to develop stable oxide semiconductors with electrical properties similar to those of Si. Herein, a single-crystal-like indium-gallium-zinc-oxide (IGZO) layer (referred to as a pseudo-single-crystal) is synthesized using plasma-enhanced atomic layer deposition and fabricated stable IGZO transistors with an ultra-high mobility of over 100 cm2  Vs-1 . To acquire high-quality atomic layer deposition-processed IGZO layers, the plasma power of the reactant is controlled as an effective processing parameter by evaluating and understanding the effect of the chemical reaction of the precursors on the behavior of the residual hydrogen, carbon, and oxygen in the as-deposited films. Based on these insights, this study found that there is a critical relationship between the optimal plasma reaction energy, superior electrical performance, and device stability.

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10's of MHz.

Intensive harmonized synapses with amorphous Cu2O-based memristors using ultrafine Cu nanoparticle sublayers formed via atomically controlled electrochemical pulse deposition

Resistive random-access memory (RRAM) devices have significant advantages for neuromorphic computing but have fatal problems of uncontrollability and abrupt resistive switching behaviors degrading their synaptic performance. In this paper, we propose the electrochemical design of an active Cu2O layer containing a strategic sublayer of ultrafine Cu nanoparticles (U-Cu NPs) to form uniformly dispersed conducting filaments, which can effectively improve the reliability for analog switching of RRAM-based neuromorphic computing. The electrochemical pulse deposited (EPD) U-Cu NPs are linked to the bottom electrode through a semi-conductive path within the bottom Cu2O layer, since the EPD is preferentially carried out on the conductive sites. All Cu2O films with U-Cu NPs are developed in situ in the single electrolyte bath without any pause. The proposed U-Cu NPs can concentrate the external electric field and can generate conductive filament paths for analog resistive switching. The applied electric field was uniformly spread to U-Cu NPs at the center of the active layer and displays resistive switching behavior via multiple conductive filaments. This shows a strong harmony between the resistance-switching characteristics and the analog operation of the active layer. This RRAM device shows outstanding gradual analog switching, great linearity, dynamic range, endurance, precision, speed, and retention characteristics simultaneously and adequately for neuromorphic computing by realizing multiple weak filament-type operation.

High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In_0.84Ga_0.16O or In_0.75Zn_0.25O), and a barrier layer (BL) (Ga₂O₃) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μ_FE) with band-like transport, steep gate swing (SS), and positive threshold voltage (V_TH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In_0.75Zn_0.25O/Ga₂O₃ NL TFT showed remarkable electrical performance: μ_FE of 77.1 ± 0.67 cm²/(V s), V_TH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and I_ON/OFF of 8.9 × 10⁹ with a low operation voltage range of ≤2 V and excellent stabilities (ΔV_TH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Heterojunction Transistors Printed via Instantaneous Oxidation of Liquid Metals

Semiconducting transparent metal oxides are critical high mobility materials for flexible optoelectronic devices such as displays. We introduce the continuous liquid metal printing (CLMP) technique to enable rapid roll-to-roll compatible deposition of semiconducting two-dimensional (2D) metal oxide heterostructures. We leverage CLMP to deposit 10 cm²-scale nanosheets of InO_x and GaO_x in seconds at a low process temperature (T < 200 °C) in air, fabricating heterojunction thin film transistors with 100× greater I_on/I_off, 4× steeper subthreshold slope, and a 50% increase in mobility over pure InO_x channels. Detailed nanoscale characterization of the heterointerface by X-ray photoelectron spectroscopy, UV-vis, and Kelvin probe elucidates the origins of enhanced electronic transport in these 2D heterojunctions. This combination of CLMP with the electrostatic control induced by the heterostructure architecture leads to high performance (μ_lin up to 22.6 cm²/(V s)) while reducing the process time for metal oxide transistors by greater than 100× compared with sol-gels and vacuum deposition methods.

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations

The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (~10^-22 A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it's essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in Al₂O₃ gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/-1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in Al₂O₃ gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at -0.73~-0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in Al₂O₃ dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process.

High-mobility and low subthreshold swing amorphous InGaZnO thin-film transistors byin situH2plasma and neutral oxygen beam irradiation treatment

In this work, staggered bottom-gate structure amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) with high-k ZrO₂gate dielectric were fabricated using low-cost atmospheric pressure-plasma enhanced chemical vapor deposition (AP-PECVD) within situhydrogenation to modulate the carrier concentration and improve interface quality. Subsequently, a neutral oxygen beam irradiation (NOBI) technique is applied, demonstrating that a suitable NOBI treatment could successfully enhance electrical characteristics by reducing native defect states and minimize the trap density in the back channel. A reverse retrograde channel (RRGC) with ultra-high/low carrier concentration is also formed to prevent undesired off-state leakage current and achieve a very low subthreshold swing. The resulting a-IGZO TFTs exhibit excellent electrical characteristics, including a low subthreshold swing of 72 mV dec^-1and high field-effect mobility of 35 cm²V^-1s^-1, due to conduction path passivation and stronger carrier confinement in the RRGC. The UV-vis spectroscopy shows optical transmittance above 90% in the visible range of the electromagnetic spectrum. The study confirms the H₂plasma with NOBI-treated a-IGZO/ZrO₂TFT is a promising candidate for transparent electronic device applications.

Organic/Inorganic Hybrid Top-Gate Transistors with Ultrahigh Electron Mobility via Enhanced Electron Pathways

The top-gate structure is currently adopted in various flat-panel displays because of its diverse advantages such as passivation from the external environment and process compatibility with industries. However, the mobility of the currently commercialized top-gate oxide thin-film transistors (TFTs) is insufficient to drive ultrahigh-resolution displays. Accordingly, this work suggests metal-capped Zn-Ba-Sn-O transistors with top-gate structures for inducing mobility-enhancing effects. The fabricated top-gate device contains para-xylylene (PPx), which is deposited by a low-temperature chemical vapor deposition (CVD) process, as a dielectric layer and exhibits excellent interfacial and dielectric properties. A technology computer-aided design (TCAD) device simulation reveals that the mobility enhancement in the Al-capped (Zn,Ba)SnO₃ (ZBTO) TFT is attributed not only to the increase in the electron concentration, which is induced by band engineering due to the Al work function but also to the increased electron velocity due to the redistribution of the lateral electric field. As a result, the mobility of the Al-capped top-gate ZBTO device is 5 times higher (∼110 cm²/Vs) than that of the reference device. These results demonstrate the applicability of top-gate oxide TFTs with ultrahigh mobility in a wide range of applications, such as for high-resolution, large-area, and flexible displays.

Physical Insights into Vacancy-Based Memtransistors: Toward Power Efficiency, Reliable Operation, and Scalability

Memtransistors that combine the properties of transistor and memristor hold significant promise for in-memory computing. While superior data storage capability is achieved in memtransistors through gate voltage-induced conductance modulation, the lateral device configuration would not only result in high write bias, which compromises the power efficiency, but also suffers from unsuccessful memory reset that leads to reliability concerns. To circumvent such performance limitations, an advanced physics-based model is required to uncover the dynamic resistive switching behavior and deduce the key driving parameters for the switching process. This work demonstrates a self-consistent physics-based model which incorporates the often-overlooked effects of lattice temperature, vacancy dynamics, and channel electrostatics to accurately solve the interaction between gate potential, ions, and carriers on the memristive switching mechanism. The completed model is carefully calibrated with an ambipolar WSe2 memtransistor and hence enables the investigation of the carrier polarity effect (electrons vs holes) on vacancy transport. Nevertheless, the validity of the model can be extended to different materials by a simple material-dependent parameter modification. Building upon the existing understanding of Schottky barrier height modulation, our study reveals three key insights─leveraging threshold voltage shifts to lower write bias; optimizing lattice temperature distribution and read bias polarity to achieve successful memory state recovery; engineering contact work function to overcome the detrimental parasitic current flow in short channel ambipolar memtransistors. Therefore, understanding the significant correlation between the switching mechanisms, different material systems, and device structures allows performance optimization of operating modes and device designs for future memtransistors-based computing systems.

Atomic Layer Deposition of Metal Oxides and Chalcogenides for High Performance Transistors

Atomic layer deposition (ALD) is a deposition technique well-suited to produce high-quality thin film materials at the nanoscale for applications in transistors. This review comprehensively describes the latest developments in ALD of metal oxides (MOs) and chalcogenides with tunable bandgaps, compositions, and nanostructures for the fabrication of high-performance field-effect transistors. By ALD various n-type and p-type MOs, including binary and multinary semiconductors, can be deposited and applied as channel materials, transparent electrodes, or electrode interlayers for improving charge-transport and switching properties of transistors. On the other hand, MO insulators by ALD are applied as dielectrics or protecting/encapsulating layers for enhancing device performance and stability. Metal chalcogenide semiconductors and their heterostructures made by ALD have shown great promise as novel building blocks to fabricate single channel or heterojunction materials in transistors. By correlating the device performance to the structural and chemical properties of the ALD materials, clear structure-property relations can be proposed, which can help to design better-performing transistors. Finally, a brief concluding remark on these ALD materials and devices is presented, with insights into upcoming opportunities and challenges for future electronics and integrated applications.

High-Density Patterning of InGaZnO by CH4: a Comparative Study of RIE and Pulsed Plasma ALE

InGaZnO (IGZO)-based thin-film transistors and selector diodes are increasingly investigated for a broad range of applications such as high-resolution displays, high-density memories, and high-speed computing. However, its potential to be a key material for next-generation devices is strongly contingent on developing patterning processes with minimal damage at nanoscale dimensions. IGZO can be etched using CH4-based plasma. Although the etched by-products are volatile, there remains a concern that passivation─an associated effect arising from the use of a hydrocarbon etchant─may inhibit the patterning process. However, there has been limited discussion on the CH4-based etching of IGZO and the subsequent patterning challenges arising with pitch scaling (<200 nm). In this work, we systematically investigate dry chemical etching schemes to pattern an IGZO film into densely packed nanostructures using CH4. Straight IGZO lines, ∼45 nm in width at a pitch of ∼135 nm, are produced by employing the traditional reactive ion etching method. While the passivating effect of CH4 does not impede the etching process, any further shrinkage of feature and pitch dimensions amplifies reactive ion etching-induced damage in the form of profile distortion and residue redeposition. We show that this is efficiently addressed via atomic layer etching (ALE) of IGZO with CH4 using a pulsed plasma. The unique combination of ALE and plasma pulsing enables controlled reduction of ion-assisted sputtering and redeposition of residues on the patterned IGZO features. This approach is highly scalable and is successfully applied here to achieve well-separated IGZO lines, with critical dimensions down to ∼20 nm at a dense pitch of ∼36 nm. These lines exhibit steep profiles (∼80°) and no undesirable change in IGZO composition post-patterning. Finally, ALE of IGZO under pulsed plasma, reproduced on 300 mm wafers, highlights its suitability in large-scale manufacturing for the intended applications.

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths

Roles of oxygen interstitial defects located in the In-Ga-Zn-O (IGZO) thin films prepared by atomic layer deposition were investigated with controlling the cationic compositions and gate-stack process conditions. It was found from the spectroscopic ellipsometry analysis that the excess oxygens increased with increasing the In contents within the IGZO channels. While the device using the IGZO channel with an In/Ga ratio of 0.2 did not show marked differences with the variations in the oxidant types during the gate-stack formation, the device characteristics were severely deteriorated with increasing the In/Ga ratio to 1.4, when the Al₂O₃ gate insulator (GI) was prepared with the H₂O oxidants (H₂O-Al₂O₃) due to a higher amount of excess oxygen in the channel. Additionally, during the deposition process of the Al-doped ZnO (AZO) gate electrode (GE) replacing from the indium-tin oxide (ITO) GE, the thermal annealing effect at 180 °C facilitated the passivation of oxygen vacancy and the strengthening of metal-oxygen bonding, which could stabilize the TFT operations. From these results, the gate-stack structure employing O₃-processed Al₂O₃ GI (O_3-Al₂O₃) and AZO GE (OA) was suggested to be most suitable for the device using IGZO channel with a higher In content. On the other hand, the device employing H₂O-Al₂O₃ GI and AZO GE exhibited larger negative shifts of threshold voltage (V_TH) under positive-bias-temperature stress (PBTS) condition than the device employing O_3- Al₂O₃ GI and ITO GE due to larger hydrogen contents within the gate stacks. Anomalous negative shifts of V_TH were accelerated with increasing the In contents of the IGZO channel. When the channel length of the fabricated device were scaled down to submicrometer regime, the OA gate stacks successfully alleviated the short-channel effects.

Comparative Study of Atomic Layer Deposited Indium-Based Oxide Transistors with a Fermi Energy Level-Engineered Heterojunction Structure Channel through a Cation Combinatorial Approach

Amorphous indium-gallium-zinc oxide (a-IGZO) has become a standard channel ingredient of switching/driving transistors in active-matrix organic light-emitting diode (AMOLED) televisions. However, mobile AMOLED displays with a high pixel density (≥500 pixels per inch) and good form factor do not often employ a-IGZO transistors due to their modest mobility (10-20 cm²/(V s)). Hybrid low-temperature polycrystalline silicon and oxide transistor (LTPO) technology is being adapted in high-end mobile AMOLED devices due to its ultralow power consumption and excellent current drivability. The critical issues of LTPO (including a complicated structure and high fabrication costs) require a search for alternative all-oxide thin-film transistors (TFTs) with low-cost processability and simple device architecture. The atomic layer deposition (ALD) method is a promising route for high-performance all-oxide TFTs due to its unique features, such as in situ cation composition tailoring ability, precise nanoscale thickness controllability, and excellent step coverage. Here, we report an in-depth comparative investigation of TFTs with indium-gallium oxide (IGO)/gallium-zinc oxide (GZO) and indium-zinc oxide (IZO)/GZO heterojunction stacks using an ALD method. IGO and IZO layers with different compositions were tested as a confinement layer (CL), whereas the GZO layer was used as a barrier layer (BL). Optimal IGO/GZO and IZO/GZO channels were carefully designed on the basis of their energy band properties, where the formation of a quasi-two-dimensional electron gas (q2DEG) near the CL/BL interface is realized by rational design of the band gaps and work-functions of the IGO, IZO, and GZO thin films. To verify the effect of q2DEG formation, the device performances and stabilities of TFTs with CL/BL oxide heterojunction stacks were examined and compared to those of TFTs with a single CL layer. The optimized device with the In_0.75Zn_0.25O/Ga_0.80Zn_0.20O stack showed remarkable electrical performance: μ_FE of 76.7 ± 0.51 cm²/(V s), V_TH of -0.37 ± 0.19 V, SS of 0.13 ± 0.01 V/dec, and I_ON/OFF of 2.5 × 10¹⁰ with low operation voltage range of ≥2 V and excellent stabilities (ΔV_TH of +0.35, -0.67, and +0.08 V for PBTS, NBIS, and CCS, respectively). This study suggests the feasibility of using high-performance ALD-derived oxide TFTs (which can compete with the performance of LTPO transistors) for high-end mobile AMOLED displays.

Highly Reliable Implementation of Optimized Multicomponent Oxide Systems Enabled by Machine Learning-Based Synthetic Protocol

Multicomponent oxide systems are one of the essential building blocks in a broad range of electronic devices. However, due to the complex physical correlation between the cation components and their relations with the system, finding an optimal combination for desired physical and/or chemical properties requires an exhaustive experimental procedure. Here, a machine learning (ML)-based synthetic approach is proposed to explore the optimal combination conditions in a ternary cationic compound indium-zinc-tin oxide (IZTO) semiconductor exhibiting high carrier mobility. In particular, by using support vector regression algorithm with radial basis function kernel, highly accurate mobility prediction can be achieved for multicomponent IZTO semiconductor with a sufficiently small number of train datasets (15-20 data points). With a synergetic combination of solution-based synthetic route for IZTO fabrication enabling a facile control of the composition ratio and tailored ML process for multicomponent system, the prediction of high-performance IZTO thin-film transistors is possible with expected field-effect mobility as high as 13.06 cm² V^-1 s^-1 at the In:Zn:Sn ratio of 63:27:10. The ML prediction is successfully translated into the empirical analysis with high accuracy, validating the protocol is reliable and a promising approach to accelerate the optimization process for multicomponent oxide systems.

Analysis of Interface Phenomena for High-Performance Dual-Stacked Oxide Thin-Film Transistors via Equivalent Circuit Modeling

Oxide thin-film transistors (TFTs) have attracted much attention because they can be applied to flexible and large-scaled switching devices. Especially, oxide semiconductors (OSs) have been developed as active layers of TFTs. Among them, indium-gallium-zinc oxide (IGZO) is actively used in the organic light-emitting diode display field. However, despite their superior off-state properties, IGZO TFTs are limited by low field-effect mobility, which critically affects display resolution and power consumption. Herein, we determine new working mechanisms in dual-stacked OS, and based on this, we develop a dual-stacked OS-based TFT with improved performance: high field-effect mobility (∼80 cm²/V·s), ideal threshold voltage near 0 V, high on-off current ratio (>10⁹), and good stability at bias stress. Induced areas are formed at the interface by the band offset: band offset-induced area (BOIA) and BOIA-induced area (BIA). They connect the gate bias-induced area (GBIA) and electrode bias-induced area (EBIA), resulting in high current flow. Equivalent circuit modeling and the transmission line method are also introduced for more precise verification. By verifying current change with gate voltage in the single OS layer, the current flowing direction in the dual-stacked OS is calculated and estimated. This is powerful evidence to understand the conduction mechanism in a dual-stacked OS-based TFT, and it will provide new design rules for high-performance OS-based TFTs.

A Review of Phototransistors Using Metal Oxide Semiconductors: Research Progress and Future Directions

Metal oxide thin-film transistors have been continuously researched and mass-produced in the display industry. However, their phototransistors are still in their infancy. In particular, utilizing metal oxide semiconductors as phototransistors is difficult because of the limited light absorption wavelength range and persistent photocurrent (PPC) phenomenon. Numerous studies have attempted to improve the detectable light wavelength range and the PPC phenomenon. Here, recent studies on metal oxide phototransistors are reviewed, which have improved the range of light wavelengths and the PPC phenomenon by introducing an absorption layer of oxide or non-oxide hybrid structure. The materials of the absorption layer applied to absorb long-wavelength light are classified into oxides, chalcogenides, organic materials, perovskites, and nanodots. Finally, next-generation convergence studies combined with other research fields are introduced and future research directions are detailed.

Effects of Al Precursors on the Characteristics of Indium-Aluminum Oxide Semiconductor Grown by Plasma-Enhanced Atomic Layer Deposition

Atomic layer deposition (ALD) has attracted much attention, particularly for applications in nanoelectronics because of its atomic-level controllability and high-quality products. In this study, we developed a plasma-enhanced atomic layer deposition (PEALD) process to fabricate a homogeneous indium aluminum oxide (IAO) semiconductor film. Trimethylaluminum (TMA) and dimethylaluminum isopropoxide (DMAI) were used as Al precursors, which yielded different compositions. Density functional theory (DFT) calculations on the surface reactions between indium and aluminum precursors showed that while highly reactive TMA would etch In, DMAI with lower reactivity would allow indium to persist in the films, resulting in a more controlled doping of Al. The In/Al composition ratio could be further precisely controlled by adjusting the indium precursor dose time to sub-saturation. IAO based on DMAI was applied to fabricate thin-film transistors (TFTs), showing that Al can be a carrier suppressor of indium oxide. TFTs with PEALD IAO containing 3.8 atomic % Al showed a turn-on voltage of -0.4 ± 0.3 V, a subthreshold slope of 0.09 V/decade, and a field effect mobility of 18.9 cm²/(V s).

Etching Characteristics and Changes in Surface Properties of IGZO Thin Films by O2 Addition in CF4/Ar Plasma

Plasma etching processes for multi-atomic oxide thin films have become increasingly important owing to the excellent material properties of such thin films, which can potentially be employed in next-generation displays. To fabricate high-performance and reproducible devices, the etching mechanism and surface properties must be understood. In this study, we investigated the etching characteristics and changes in the surface properties of InGaZnO4 (IGZO) thin films with the addition of O2 gases based on a CF4/Ar high-density-plasma system. A maximum etch rate of 32.7 nm/min for an IGZO thin film was achieved at an O2/CF4/Ar (=20:25:75 sccm) ratio. The etching mechanism was interpreted in detail through plasma analysis via optical emission spectroscopy and surface analysis via X-ray photoelectron microscopy. To determine the performance variation according to the alteration in the surface composition of the IGZO thin films, we investigated the changes in the work function, surface energy, and surface roughness through ultraviolet photoelectron spectroscopy, contact angle measurement, and atomic force microscopy, respectively. After the plasma etching process, the change in work function was up to 280 meV, the thin film surface became slightly hydrophilic, and the surface roughness slightly decreased. This work suggests that plasma etching causes various changes in thin-film surfaces, which affects device performance.

Significance of Pairing In/Ga Precursor Structures on PEALD InGaOx Thin-Film Transistor

Atomic layer deposition (ALD) is a promising deposition method to precisely control the thickness and metal composition of oxide semiconductors, making them attractive materials for use in thin-film transistors because of their high mobility and stability. However, multicomponent deposition using ALD is difficult to control without understanding the growth mechanisms of the precursors and reactants. Thus, the adsorption and surface reactivity of various precursors must be investigated. In this study, InGaO (IGO) semiconductors were deposited by plasma-enhanced atomic layer deposition (PEALD) using two sets of In and Ga precursors. The first set of precursors consisted of In(CH₃)₃[CH₃OCH₂CH₂NHtBu] (TMION) and Ga(CH₃)₃[CH₃OCH₂CH₂NHtBu]) (TMGON), denoted as TM-IGO; the other set of precursors was (CH₃)₂In(CH₂)₃N(CH₃)₂ (DADI) and (CH₃)₃Ga (TMGa), denoted as DT-IGO. We varied the number of InO subcycles between 3 and 19 to control the chemical composition of the ALD-processed films. The indium compositions of TM-IGO and DT-IGO thin films increased as the InO subcycles increased. However, the indium/gallium metal ratios of TM-IGO and DT-IGO were quite different, despite having the same InO subcycles. The steric hindrance of the precursors and different densities of the adsorption sites contributed to the different TM-IGO and DT-IGO metal ratios. The electrical properties of the precursors, such as Hall characteristics and device parameters of the thin-film transistors, were also different, even though the same deposition process was used. These differences might have resulted from the growth behavior, anion/cation ratios, and binding states of the IGO thin films.

Hydrogen Barriers Based on Chemical Trapping Using Chemically Modulated Al2O3 Grown by Atomic Layer Deposition for InGaZnO Thin-Film Transistors

In this study, the excellent hydrogen barrier properties of the atomic-layer-deposition-grown Al₂O₃ (ALD Al₂O₃) are first reported for improving the stability of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). Chemical species in Al₂O₃ were artificially modulated during the ALD process using different oxidants, such as H₂O and O₃ (H₂O-Al₂O₃ and O₃-Al₂O₃, respectively). When hydrogen was incorporated into the H₂O-Al₂O₃-passivated TFT, a large negative shift in V_th (ca. -12 V) was observed. In contrast, when hydrogen was incorporated into the O₃-Al₂O₃-passivated TFT, there was a negligible shift in V_th (ca. -0.66 V), which indicates that the O₃-Al₂O₃ has a remarkable hydrogen barrier property. We presented a mechanism for trapping hydrogen in a O₃-Al₂O₃ via various chemical and electrical analyses and revealed that hydrogen molecules were trapped by C-O bonds in the O₃-Al₂O₃, preventing the inflow of hydrogen to the a-IGZO. Additionally, to minimize the deterioration of the pristine device that occurs after a barrier deposition, a bi-layered hydrogen barrier by stacking H₂O- and O₃-Al₂O₃ is adopted. Such a barrier can provide ultrastable performance without degradation. Therefore, we envisioned that the excellent hydrogen barrier suggested in this paper can provide the possibility of improving the stability of devices in various fields by effectively blocking hydrogen inflows.

Amorphous NdIZO Thin Film Transistors with Contact-Resistance-Adjustable Cu S/D Electrodes

High-performance amorphous oxide semiconductor thin film transistors (AOS-TFT) with copper (Cu) electrodes are of great significance for next-generation large-size, high-refresh rate and high-resolution panel display technology. In this work, using rare earth dopant, neodymium-doped indium-zinc-oxide (NdIZO) film was optimized as the active layer of TFT with Cu source and drain (S/D) electrodes. Under the guidance of the Taguchi orthogonal design method from Minitab software, the semiconductor characteristics were evaluated by microwave photoconductivity decay (μ-PCD) measurement. The results show that moderate oxygen concentration (~5%), low sputtering pressure (≤5 mTorr) and annealing temperature (≤300 °C) are conducive to reducing the shallow localized states of NdIZO film. The optimized annealing temperature of this device configuration is as low as 250 °C, and the contact resistance (R_C) is modulated by gate voltage (V_G) instead of a constant value when annealed at 300 °C. It is believed that the adjustable R_C with V_G is the key to keeping both high mobility and compensation of the threshold voltage (V_th). The optimal device performance was obtained at 250 °C with an I_on/I_off ratio of 2.89 × 10⁷, a saturation mobility (μ_sat) of 24.48 cm²/(V·s) and V_th of 2.32 V.

Achieving a Low-Voltage, High-Mobility IGZO Transistor through an ALD-Derived Bilayer Channel and a Hafnia-Based Gate Dielectric Stack

Ultrahigh-resolution displays for augmented reality (AR) and virtual reality (VR) applications require a novel architecture and process. Atomic-layer deposition (ALD) enables the facile fabrication of indium-gallium zinc oxide (IGZO) thin-film transistors (TFTs) on a substrate with a nonplanar surface due to its excellent step coverage and accurate thickness control. Here, we report all-ALD-derived TFTs using IGZO and HfO₂ as the channel layer and gate insulator, respectively. A bilayer IGZO channel structure consisting of a 10 nm base layer (In_0.52Ga_0.29Zn_0.19O) with good stability and a 3 nm boost layer (In_0.82Ga_0.08Zn_0.10O) with extremely high mobility was designed based on a cation combinatorial study of the ALD-derived IGZO system. Reducing the thickness of the HfO₂ dielectric film by the ALD process offers high areal capacitance in field-effect transistors, which allows low-voltage drivability and enhanced carrier transport. The intrinsic inferior stability of the HfO₂ gate insulator was effectively mitigated by the insertion of an ALD-derived 4 nm Al₂O₃ interfacial layer between HfO₂ and the IGZO film. The optimized bilayer IGZO TFTs with HfO₂-based gate insulators exhibited excellent performances with a high field-effect mobility of 74.0 ± 0.91 cm²/(V s), a low subthreshold swing of 0.13 ± 0.01 V/dec, a threshold voltage of 0.20 ± 0.24 V, and an I_ON/OFF of ∼3.2 × 10⁸ in a low-operation-voltage (≤2 V) range. This promising result was due to the synergic effects of a bilayer IGZO channel and HfO₂-based gate insulator with a high permittivity, which were mainly attributed to the effective carrier confinement in the boost layer with high mobility, low free carrier density of the base layer with a low V_O concentration, and HfO₂-induced high effective capacitance.

Materials Science Challenges to Graphene Nanoribbon Electronics

Graphene nanoribbons (GNRs) have recently emerged as promising candidates for channel materials in future nanoelectronic devices due to their exceptional electronic, thermal, and mechanical properties and chemical inertness. However, the adoption of GNRs in commercial technologies is currently hampered by materials science and integration challenges pertaining to synthesis and devices. In this Review, we present an overview of the current status of challenges, recent breakthroughs toward overcoming these challenges, and possible future directions for the field of GNR electronics. We motivate the need for exploration of scalable synthetic techniques that yield atomically precise, placed, registered, and oriented GNRs on CMOS-compatible substrates and stimulate ideas for contact and dielectric engineering to realize experimental performance close to theoretically predicted metrics. We also briefly discuss unconventional device architectures that could be experimentally investigated to harness the maximum potential of GNRs in future spintronic and quantum information technologies.

Role of ALD Al2O3 Surface Passivation on the Performance of p-Type Cu2O Thin Film Transistors

High-performance p-type oxide thin film transistors (TFTs) have great potential for many semiconductor applications. However, these devices typically suffer from low hole mobility and high off-state currents. We fabricated p-type TFTs with a phase-pure polycrystalline Cu₂O semiconductor channel grown by atomic layer deposition (ALD). The TFT switching characteristics were improved by applying a thin ALD Al₂O₃ passivation layer on the Cu₂O channel, followed by vacuum annealing at 300 °C. Detailed characterization by transmission electron microscopy-energy dispersive X-ray analysis and X-ray photoelectron spectroscopy shows that the surface of Cu₂O is reduced following Al₂O₃ deposition and indicates the formation of a 1-2 nm thick CuAlO₂ interfacial layer. This, together with field-effect passivation caused by the high negative fixed charge of the ALD Al₂O₃, leads to an improvement in the TFT performance by reducing the density of deep trap states as well as by reducing the accumulation of electrons in the semiconducting layer in the device off-state.

Flexible electric-double-layer thin film transistors based on a vertical InGaZnO4 channel

Flexible electric-double-layer (EDL) thin film transistors (TFTs) based on a vertical InGaZnO₄ (IGZO) channel are fabricated at room temperature.

Area-Selective Atomic Layer Deposition Patterned by Electrohydrodynamic Jet Printing for Additive Manufacturing of Functional Materials and Devices

There is an increasing interest in additive nanomanufacturing processes, which enable customizable patterning of functional materials and devices on a wide range of substrates. However, there are relatively few techniques with the ability to directly 3D print patterns of functional materials with sub-micron resolution. In this study, we demonstrate the use of additive electrohydrodynamic jet (e-jet) printing with an average line width of 312 nm, which acts as an inhibitor for area-selective atomic layer deposition (AS-ALD) of a range of metal oxides. We also demonstrate subtractive e-jet printing with solvent inks that dissolve polymer inhibitor layers in specific regions, which enables localized AS-ALD within those regions. The chemical selectivity and morphology of e-jet patterned polymers towards binary and ternary oxides of ZnO, Al₂O₃, and SnO₂ were quantified using X-ray photoelectron spectroscopy, atomic force microscopy, and Auger electron spectroscopy. This approach enables patterning of functional oxide semiconductors, insulators, and transparent conducting oxides with tunable composition, Å-scale control of thickness, and sub-μm resolution in the x-y plane. Using a combination of additive and subtractive e-jet printing with AS-ALD, a thin-film transistor was fabricated using zinc-tin-oxide for the semiconductor channel and aluminum-doped zinc oxide as the source and drain electrical contacts. In the future, this technique can be used to print integrated electronics with sub-micron resolution on a variety of substrates.

High-Performance Thin-Film Transistors with an Atomic-Layer-Deposited Indium Gallium Oxide Channel: A Cation Combinatorial Approach

The effect of gallium (Ga) concentration on the structural evolution of atomic-layer-deposited indium gallium oxide (IGO) (In_1-xGa_xO) films as high-mobility n-channel semiconducting layers was investigated. Different Ga concentrations in 10-13 nm thick In_1-xGa_xO films allowed versatile phase structures to be amorphous, highly ordered, and randomly oriented crystalline by thermal annealing at either 400 or 700 °C for 1 h. Heavy Ga concentrations above 34 atom % caused a phase transformation from a polycrystalline bixbyite to an amorphous IGO film at 400 °C, while proper Ga concentration produced a highly ordered bixbyite crystal structure at 700 °C. The resulting highly ordered In_0.66Ga_0.34O film show unexpectedly high carrier mobility (μ_FE) values of 60.7 ± 1.0 cm² V^-1 s^-1, a threshold voltage (V_TH) of -0.80 ± 0.05 V, and an I_ON/OFF ratio of 5.1 × 10⁹ in field-effect transistors (FETs). In contrast, the FETs having polycrystalline In_1-xGa_xO films with higher In fractions (x = 0.18 and 0.25) showed reasonable μ_FE values of 40.3 ± 1.6 and 31.5 ± 2.4 cm² V^-1 s^-1, V_TH of -0.64 ± 0.40 and -0.43 ± 0.06 V, and I_ON/OFF ratios of 2.5 × 10⁹ and 1.4 × 10⁹, respectively. The resulting superior performance of the In_0.66Ga_0.34O-film-based FET was attributed to a morphology having fewer grain boundaries, with higher mass densification and lower oxygen vacancy defect density of the bixbyite crystallites. Also, the In_0.66Ga_0.34O transistor was found to show the most stable behavior against an external gate bias stress.

Comparative studies on vertical-channel charge-trap memory thin-film transistors using In-Ga-Zn-O active channels deposited by sputtering and atomic layer depositions

Vertical-channel charge-trap memory thin film-transistors (V-CTM TFTs) using oxide semiconductors were fabricated and characterized, in which In-Ga-Zn-O (IGZO) channels were prepared by sputtering and atomic-layer deposition (ALD) methods to elucidate the effects of deposition process. The vertical-channel gate stack of the fabricated device was verified to be well implemented on the vertical sidewall of the spacer patterns due to excellent step-coverage and self-limiting mechanisms of ALD process. The V-CTM TFTs using ALD-IGZO channel exhibited a wide memory window (MW) of 15.0 V at a V_GS sweep of ±20 V and a large memory margin of 1.6 × 10² at a program pulse duration as short as 5 ms. The programmed memory margin higher than 10⁵ did not experience any degradation with time evolution for 10⁴ s. The mechanical durability was also evaluated after the delamination process of polyimide (PI) film. There were no marked variations in charge-trap-assisted MW even at a curvature radius of 1 mm and programmed memory margin even after repeated program operations of 10⁴ cycles. The introduction of ALD process for the formation of IGZO active channel was suggested as a main process parameter to ensure the excellent memory device characteristics of the V-CTM TFTs.

Atomic Layer Deposition Process-Enabled Carrier Mobility Boosting in Field-Effect Transistors through a Nanoscale ZnO/IGO Heterojunction

Low-temperature (≤400 °C), stackable oxide semiconductors are promising as an upper transistor ingredient for monolithic three-dimensional integration. The atomic layer deposition (ALD) route provides a low-defect, high-quality semiconducting oxide channel layer and enables accurate controllability of the chemical composition and physical thickness as well as excellent step coverage on nanoscale trench structures. Here, we report a high-mobility heterojunction transistor in a ternary indium gallium zinc oxide system using the ALD technique. The heterojunction channel structure consists of a 10 nm thick indium gallium oxide (IGO) layer as an effective transporting layer and a 3 nm thick, wide band gap ZnO layer. The formation of a two-dimensional electron gas was suggested by controlling the band gap of the IGO quantum well through In/Ga ratio tailoring and reducing the physical thickness of the ZnO film. A field-effect transistor (FET) with a ZnO/In_0.83Ga_0.17O_1.5 heterojunction channel exhibited the highest field-effect mobility of 63.2 ± 0.26 cm²/V s, a low subthreshold gate swing of 0.26 ± 0.03 V/dec, a threshold voltage of -0.84 ± 0.85 V, and an I_ON/OFF ratio of 9 × 10⁸. This surpasses the performance (carrier mobility of ∼41.7 ± 1.43 cm²/V s) of an FET with a single In_0.83Ga_0.17O_1.5 channel. Furthermore, the gate bias stressing test results indicate that FETs with a ZnO/In_1-xGa_xO_1.5 (x = 0.25 and 0.17) heterojunction channel are much more stable than those with a single In_1-xGa_xO_1.5 (x = 0.35, 0.25, and 0.17) channel. Relevant discussion is given in detail on the basis of chemical characterization and technological computer-aided design simulation.

Structure-Property Relation in Organic-Metal Oxide Hybrid Phototransistors

We report an optoelectronic device consisting of a solution-processed indium gallium zinc oxide (IGZO) thin-film transistor and vacuum-deposited small organic molecules. Depending on the configurations of the organic materials, either bulk heterojunction or planar heterojunction (PHJ), the device assumes the functionality of either a photosensor or a photoinduced memory, respectively. Under λ = 625 nm light illumination, the photosensor shows response and recovery time of ∼50 ms, responsivity of ∼5 mA/W, sensitivity above 10⁴, and a linear response. The mechanism of the photoinduced memory is studied experimentally and verified using a device simulation. We find that the memory is due to long charge retention time at the organic PHJ interface which is stable for over 9 days. It is correlated with the low leakage current found in ordered organic junctions having low subgap tail states. The presented integration of the PHJ with the transistor constitutes a new design of write-once-read-many-times memory device that is likely to be attractive for low-cost applications.

Influence of Post-UV/Ozone Treatment of Ultrasonic-Sprayed Zirconium Oxide Dielectric Films for a Low-Temperature Oxide Thin Film Transistor

Solution-processed metal oxides require a great deal of thermal budget in order to achieve the desired film properties. Here, we show that the deposition temperature of sprayed zirconium oxide (ZrO_x) thin film can be lowered by exposing the film surface to an ultraviolet (UV) ozone treatment at room temperature. Atomic force microscopy reveals a smooth and uniform film with the root mean square roughness reduced from ~ 0.63 nm (UVO-O) to ~ 0.28 nm (UVO-120) in the UV–ozone treated ZrO_x films. X-ray photoelectron spectroscopy analysis indicates the formation of a Zr–O network on the surface film, and oxygen vacancy is reduced in the ZrO_x lattice by increasing the UV–ozone treatment time. The leakage current density in Al/ZrOx/p-Si structure was reduced by three orders of magnitude by increasing the UV-ozone exposure time, while the capacitance was in the range 290–266 nF/cm², corresponding to a relative permittivity (k) in the range 5.8–6.6 at 1 kHz. An indium gallium zinc oxide (IGZO)-based thin film transistor, employing a UV-treated ZrO_x gate dielectric deposited at 200 °C, exhibits negligible hysteresis, an I_on/I_off ratio of 10⁴, a saturation mobility of 8.4 cm² V⁻¹S⁻¹, a subthreshold slope of 0.21 V.dec⁻¹, and a V_on of 0.02 V. These results demonstrate the potentiality of low-temperature sprayed amorphous ZrO_x to be applied as a dielectric in flexible and low-power-consumption oxide electronics.